From: Dmitry Osipenko <digetx@gmail.com>
To: Ashish Mhetre <amhetre@nvidia.com>,
krzysztof.kozlowski@canonical.com, robh+dt@kernel.org,
thierry.reding@gmail.com, jonathanh@nvidia.com,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org
Cc: vdumpa@nvidia.com, Snikam@nvidia.com
Subject: Re: [Patch v5 2/4] memory: tegra: Add MC error logging on tegra186 onward
Date: Sun, 20 Mar 2022 15:53:21 +0300 [thread overview]
Message-ID: <55ae43f0-a22f-b532-2476-c3afa1e2cb73@gmail.com> (raw)
In-Reply-To: <20220316092525.4554-3-amhetre@nvidia.com>
16.03.2022 12:25, Ashish Mhetre пишет:
> +static int tegra186_mc_get_channel(const struct tegra_mc *mc, int *mc_channel)
> +{
> + u32 status;
> +
> + status = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, MC_GLOBAL_INTSTATUS);
> +
> + switch (status & mc->soc->int_channel_mask) {
> + case BIT(0):
> + *mc_channel = 0;
> + break;
> +
> + case BIT(1):
> + *mc_channel = 1;
> + break;
> +
> + case BIT(2):
> + *mc_channel = 2;
> + break;
> +
> + case BIT(3):
> + *mc_channel = 3;
> + break;
This won't work if multiple bits are set at once.
next prev parent reply other threads:[~2022-03-20 12:53 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-16 9:25 [Patch v5 0/4] memory: tegra: Add MC channels and error logging Ashish Mhetre
2022-03-16 9:25 ` [Patch v5 1/4] memory: tegra: Add memory controller channels support Ashish Mhetre
2022-03-19 15:42 ` Dmitry Osipenko
2022-03-22 16:13 ` Ashish Mhetre
2022-03-25 4:50 ` Ashish Mhetre
2022-03-29 23:48 ` Dmitry Osipenko
2022-03-30 5:07 ` Ashish Mhetre
2022-03-20 12:31 ` Krzysztof Kozlowski
2022-03-22 18:04 ` Ashish Mhetre
2022-03-22 18:24 ` Krzysztof Kozlowski
2022-03-16 9:25 ` [Patch v5 2/4] memory: tegra: Add MC error logging on tegra186 onward Ashish Mhetre
2022-03-19 15:50 ` Dmitry Osipenko
2022-03-19 16:19 ` Dmitry Osipenko
2022-03-22 17:51 ` Ashish Mhetre
2022-03-22 16:48 ` Ashish Mhetre
2022-03-19 15:59 ` Dmitry Osipenko
2022-03-22 17:23 ` Ashish Mhetre
2022-03-29 23:51 ` Dmitry Osipenko
2022-03-30 5:02 ` Ashish Mhetre
2022-03-19 16:14 ` Dmitry Osipenko
2022-03-22 17:34 ` Ashish Mhetre
2022-03-30 0:01 ` Dmitry Osipenko
2022-03-30 10:16 ` Ashish Mhetre
2022-03-30 10:36 ` Dmitry Osipenko
2022-03-30 11:22 ` Ashish Mhetre
2022-03-31 19:49 ` Dmitry Osipenko
2022-03-31 21:55 ` Ashish Mhetre
2022-03-20 12:53 ` Dmitry Osipenko [this message]
2022-03-23 8:36 ` Ashish Mhetre
2022-03-30 0:06 ` Dmitry Osipenko
2022-03-30 9:03 ` Ashish Mhetre
2022-03-30 10:19 ` Dmitry Osipenko
2022-03-30 10:34 ` Ashish Mhetre
2022-03-16 9:25 ` [Patch v5 3/4] dt-bindings: memory: Update reg maxitems for tegra186 Ashish Mhetre
2022-03-19 15:42 ` Dmitry Osipenko
2022-03-20 2:13 ` Rob Herring
2022-03-20 12:42 ` Krzysztof Kozlowski
2022-03-22 18:12 ` Ashish Mhetre
2022-03-22 18:42 ` Krzysztof Kozlowski
2022-03-16 9:25 ` [Patch v5 4/4] arm64: tegra: Add memory controller channels Ashish Mhetre
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