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[2001:14bb:ac:e5a8:ef73:73ed:75b3:8ed5]) by smtp.gmail.com with ESMTPSA id e16-20020ac24e10000000b00492ba56995asm630824lfr.101.2022.08.19.05.52.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Aug 2022 05:52:40 -0700 (PDT) Message-ID: <55c53ba1-8e13-599d-1b16-5dab417a3059@linaro.org> Date: Fri, 19 Aug 2022 15:52:38 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Subject: Re: [PATCH net-next 1/2] dt-bindings: net: tja11xx: add nxp,refclk_in property Content-Language: en-US To: Andrew Lunn Cc: Wei Fang , "davem@davemloft.net" , "edumazet@google.com" , "kuba@kernel.org" , "pabeni@redhat.com" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "f.fainelli@gmail.com" , "hkallweit1@gmail.com" , "linux@armlinux.org.uk" , "netdev@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" References: <20220819074729.1496088-1-wei.fang@nxp.com> <20220819074729.1496088-2-wei.fang@nxp.com> <9ec575ba-784d-74f7-8861-da2f62fe0773@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 19/08/2022 15:44, Andrew Lunn wrote: > On Fri, Aug 19, 2022 at 02:37:36PM +0300, Krzysztof Kozlowski wrote: >> On 19/08/2022 12:37, Wei Fang wrote: >>>> >>>>> + in RMII mode. This clock signal is provided by the PHY and is >>>>> + typically derived from an external 25MHz crystal. Alternatively, >>>>> + a 50MHz clock signal generated by an external oscillator can be >>>>> + connected to pin REF_CLK. A third option is to connect a 25MHz >>>>> + clock to pin CLK_IN_OUT. So, the REF_CLK should be configured >>>>> + as input or output according to the actual circuit connection. >>>>> + If present, indicates that the REF_CLK will be configured as >>>>> + interface reference clock input when RMII mode enabled. >>>>> + If not present, the REF_CLK will be configured as interface >>>>> + reference clock output when RMII mode enabled. >>>>> + Only supported on TJA1100 and TJA1101. >>>> >>>> Then disallow it on other variants. >>>> >>>> Shouldn't this be just "clocks" property? >>>> >>>> >>> This property is to configure the pin REF_CLK of PHY as a input pin through phy register, >>> indicates that the REF_CLK signal is provided by an external oscillator. so I don't think it's a >>> "clock" property. >> >> clocks, not clock. >> >> You just repeated pieces of description as an counter-argument, so this >> does not explain anything. >> >> If it is external oscillator shouldn't it be represented in DTS and then >> obtained by driver (clk_get + clk_prepare_enable)? Otherwise how are you >> sure that clock is actually enabled? And the lack of presence of the >> external clock means it is derived from PHY? > > Using the common clock framework has been discussed in the past. But > no PHY actually does this. When the SoC provides the clock, a few PHYs > do make use of the common clock framework as clock consumers to ensure > the clock is ticking. IOW, all DTSes would have a fixed clock stub without any logic usable by Common CF (like enabling)? > Plus, as the description says, this pin can be either a clock producer > or a consumer. I don't think the common clock code allows this. It is > also not something you negotiate between the MAC and PHY. The hardware > designer typically decides based on the MAC and PHY actually used. So > this is a fixed hardware property. Indeed. Anyway the property name and typo need fixes. Best regards, Krzysztof