* [PATCH V4 1/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings
@ 2015-09-17 12:00 Chen Feng
2015-09-17 12:00 ` [PATCH V4 2/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC Chen Feng
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Chen Feng @ 2015-09-17 12:00 UTC (permalink / raw)
To: p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
xuwei5-C8/M+/jPZTeaMJb+Lgu22Q,
haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
zhangfei.gao-H32Fclmsjq1BDgjK7y7TUQ, arnd-r2nGTMty4D4,
puck.chen-C8/M+/jPZTeaMJb+Lgu22Q
Cc: bintian.wang-hv44wF8Li93QT0dZR+AlfA,
xuyiping-C8/M+/jPZTeaMJb+Lgu22Q,
devicetree-u79uwXL29TY76Z2rM5mHXA,
dan.zhao-C8/M+/jPZTeaMJb+Lgu22Q,
suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q, w.f-hv44wF8Li93QT0dZR+AlfA,
kong.kongxinwei-C8/M+/jPZTeaMJb+Lgu22Q,
yudongbin-C8/M+/jPZTeaMJb+Lgu22Q,
peter.panshilin-C8/M+/jPZTeaMJb+Lgu22Q,
qijiwen-C8/M+/jPZTeaMJb+Lgu22Q
Add DT bindings documentation for hi6220 SoC reset controller.
Signed-off-by: Chen Feng <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
---
.../bindings/reset/hisilicon,hi6220-reset.txt | 97 ++++++++++++++++++++++
1 file changed, 97 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
new file mode 100644
index 0000000..c0f7928
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
@@ -0,0 +1,97 @@
+Hisilicon System Reset Controller
+======================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+The reset controller node must be a sub-node of the chip controller
+node on SoCs.
+
+Required properties:
+- compatible: may be "hisilicon,hi6220-reset-ctl"
+- reg: should be register base and length as documented in the
+ datasheet
+- #reset-cells: 1, see below
+
+Example:
+
+ reset_ctrl: reset_ctrl@f7030000 {
+ compatible = "hisilicon,hi6220-reset-ctl";
+ reg = <0x0 0xf7030000 0x0 0x1000>;
+ #reset-cells = <1>;
+ };
+
+Specifying reset lines connected to IP modules
+==============================================
+example:
+
+ uart1: uart1@..... {
+ ...
+ resets = <&reset_ctrl 0x305>;
+ ...
+ };
+
+The following RESET_INDEX values are valid for hi6220 SoC:
+ PERIPH_RSTDIS0_MMC0 = 0x000,
+ PERIPH_RSTDIS0_MMC1 = 0x001,
+ PERIPH_RSTDIS0_MMC2 = 0x002,
+ PERIPH_RSTDIS0_NANDC = 0x003,
+ PERIPH_RSTDIS0_USBOTG_BUS = 0x004,
+ PERIPH_RSTDIS0_POR_PICOPHY = 0x005,
+ PERIPH_RSTDIS0_USBOTG = 0x006,
+ PERIPH_RSTDIS0_USBOTG_32K = 0x007,
+
+ PERIPH_RSTDIS1_HIFI = 0x100,
+ PERIPH_RSTDIS1_DIGACODEC = 0x105,
+
+ PERIPH_RSTEN2_IPF = 0x200,
+ PERIPH_RSTEN2_SOCP = 0x201,
+ PERIPH_RSTEN2_DMAC = 0x202,
+ PERIPH_RSTEN2_SECENG = 0x203,
+ PERIPH_RSTEN2_ABB = 0x204,
+ PERIPH_RSTEN2_HPM0 = 0x205,
+ PERIPH_RSTEN2_HPM1 = 0x206,
+ PERIPH_RSTEN2_HPM2 = 0x207,
+ PERIPH_RSTEN2_HPM3 = 0x208,
+
+ PERIPH_RSTEN3_CSSYS = 0x300,
+ PERIPH_RSTEN3_I2C0 = 0x301,
+ PERIPH_RSTEN3_I2C1 = 0x302,
+ PERIPH_RSTEN3_I2C2 = 0x303,
+ PERIPH_RSTEN3_I2C3 = 0x304,
+ PERIPH_RSTEN3_UART1 = 0x305,
+ PERIPH_RSTEN3_UART2 = 0x306,
+ PERIPH_RSTEN3_UART3 = 0x307,
+ PERIPH_RSTEN3_UART4 = 0x308,
+ PERIPH_RSTEN3_SSP = 0x309,
+ PERIPH_RSTEN3_PWM = 0x30a,
+ PERIPH_RSTEN3_BLPWM = 0x30b,
+ PERIPH_RSTEN3_TSENSOR = 0x30c,
+ PERIPH_RSTEN3_DAPB = 0x312,
+ PERIPH_RSTEN3_HKADC = 0x313,
+ PERIPH_RSTEN3_CODEC_SSI = 0x314,
+ PERIPH_RSTEN3_PMUSSI1 = 0x316,
+
+ PERIPH_RSTEN8_RS0 = 0x400,
+ PERIPH_RSTEN8_RS2 = 0x401,
+ PERIPH_RSTEN8_RS3 = 0x402,
+ PERIPH_RSTEN8_MS0 = 0x403,
+ PERIPH_RSTEN8_MS2 = 0x405,
+ PERIPH_RSTEN8_XG2RAM0 = 0x406,
+ PERIPH_RSTEN8_X2SRAM_TZMA = 0x407,
+ PERIPH_RSTEN8_SRAM = 0x408,
+ PERIPH_RSTEN8_HARQ = 0x40a,
+ PERIPH_RSTEN8_DDRC = 0x40c,
+ PERIPH_RSTEN8_DDRC_APB = 0x40d,
+ PERIPH_RSTEN8_DDRPACK_APB = 0x40e,
+ PERIPH_RSTEN8_DDRT = 0x411,
+
+ PERIPH_RSDIST9_CARM_DAP = 0x500,
+ PERIPH_RSDIST9_CARM_ATB = 0x501,
+ PERIPH_RSDIST9_CARM_LBUS = 0x502,
+ PERIPH_RSDIST9_CARM_POR = 0x503,
+ PERIPH_RSDIST9_CARM_CORE = 0x504,
+ PERIPH_RSDIST9_CARM_DBG = 0x505,
+ PERIPH_RSDIST9_CARM_L2 = 0x506,
+ PERIPH_RSDIST9_CARM_SOCDBG = 0x507,
+ PERIPH_RSDIST9_CARM_ETM = 0x508,
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH V4 2/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC
2015-09-17 12:00 [PATCH V4 1/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings Chen Feng
@ 2015-09-17 12:00 ` Chen Feng
2015-09-17 12:00 ` [PATCH V4 3/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC Chen Feng
2015-09-21 14:18 ` [PATCH V4 1/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings Rob Herring
2 siblings, 0 replies; 6+ messages in thread
From: Chen Feng @ 2015-09-17 12:00 UTC (permalink / raw)
To: p.zabel, linux-kernel, robh+dt, pawel.moll, xuwei5,
haojian.zhuang, zhangfei.gao, arnd, puck.chen
Cc: bintian.wang, xuyiping, devicetree, dan.zhao, suzhuangluan, w.f,
kong.kongxinwei, yudongbin, peter.panshilin, qijiwen
Add reset driver for hi6220-hikey board,this driver supply deassert
of IP. on hi6220 SoC.
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
---
drivers/reset/Kconfig | 1 +
drivers/reset/Makefile | 1 +
drivers/reset/hisilicon/Kconfig | 5 ++
drivers/reset/hisilicon/Makefile | 1 +
drivers/reset/hisilicon/hi6220_reset.c | 107 +++++++++++++++++++++++++++++++++
5 files changed, 115 insertions(+)
create mode 100644 drivers/reset/hisilicon/Kconfig
create mode 100644 drivers/reset/hisilicon/Makefile
create mode 100644 drivers/reset/hisilicon/hi6220_reset.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 0615f50..df37212 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER
If unsure, say no.
source "drivers/reset/sti/Kconfig"
+source "drivers/reset/hisilicon/Kconfig"
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 157d421..331d7b2 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
obj-$(CONFIG_ARCH_STI) += sti/
+obj-$(CONFIG_ARCH_HISI) += hisilicon/
diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig
new file mode 100644
index 0000000..26bf95a
--- /dev/null
+++ b/drivers/reset/hisilicon/Kconfig
@@ -0,0 +1,5 @@
+config COMMON_RESET_HI6220
+ tristate "Hi6220 Reset Driver"
+ depends on (ARCH_HISI && RESET_CONTROLLER)
+ help
+ Build the Hisilicon Hi6220 reset driver.
diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
new file mode 100644
index 0000000..c932f86
--- /dev/null
+++ b/drivers/reset/hisilicon/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c
new file mode 100644
index 0000000..eac9531
--- /dev/null
+++ b/drivers/reset/hisilicon/hi6220_reset.c
@@ -0,0 +1,107 @@
+/*
+ * Hisilicon Hi6220 reset controller driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Feng Chen <puck.chen@hisilicon.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/bitops.h>
+#include <linux/of.h>
+#include <linux/reset-controller.h>
+#include <linux/reset.h>
+#include <linux/platform_device.h>
+
+#define ASSERT_OFFSET 0x300
+#define DEASSERT_OFFSET 0x304
+#define MAX_INDEX 0x509
+
+#define to_reset_data(x) container_of(x, struct hi6220_reset_data, rc_dev)
+
+struct hi6220_reset_data {
+ void __iomem *assert_base;
+ void __iomem *deassert_base;
+ struct reset_controller_dev rc_dev;
+};
+
+static int hi6220_reset_assert(struct reset_controller_dev *rc_dev,
+ unsigned long idx)
+{
+ struct hi6220_reset_data *data = to_reset_data(rc_dev);
+
+ int bank = idx >> 8;
+ int offset = idx & 0xff;
+
+ writel(BIT(offset), data->assert_base + (bank * 0x10));
+
+ return 0;
+}
+
+static int hi6220_reset_deassert(struct reset_controller_dev *rc_dev,
+ unsigned long idx)
+{
+ struct hi6220_reset_data *data = to_reset_data(rc_dev);
+
+ int bank = idx >> 8;
+ int offset = idx & 0xff;
+
+ writel(BIT(offset), data->deassert_base + (bank * 0x10));
+
+ return 0;
+}
+
+static struct reset_control_ops hi6220_reset_ops = {
+ .assert = hi6220_reset_assert,
+ .deassert = hi6220_reset_deassert,
+};
+
+static int hi6220_reset_probe(struct platform_device *pdev)
+{
+ struct hi6220_reset_data *data;
+ struct resource *res;
+ void __iomem *src_base;
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ src_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(src_base))
+ return PTR_ERR(src_base);
+
+ data->assert_base = src_base + ASSERT_OFFSET;
+ data->deassert_base = src_base + DEASSERT_OFFSET;
+ data->rc_dev.nr_resets = MAX_INDEX;
+ data->rc_dev.ops = &hi6220_reset_ops;
+ data->rc_dev.of_node = pdev->dev.of_node;
+
+ reset_controller_register(&data->rc_dev);
+
+ return 0;
+}
+
+static const struct of_device_id hi6220_reset_match[] = {
+ { .compatible = "hisilicon,hi6220-reset-ctl" },
+ { },
+};
+
+static struct platform_driver hi6220_reset_driver = {
+ .probe = hi6220_reset_probe,
+ .driver = {
+ .name = "reset-hi6220",
+ .of_match_table = hi6220_reset_match,
+ },
+};
+
+static int __init hi6220_reset_init(void)
+{
+ return platform_driver_register(&hi6220_reset_driver);
+}
+
+postcore_initcall(hi6220_reset_init);
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH V4 3/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC
2015-09-17 12:00 [PATCH V4 1/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings Chen Feng
2015-09-17 12:00 ` [PATCH V4 2/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC Chen Feng
@ 2015-09-17 12:00 ` Chen Feng
2015-09-18 15:23 ` Philipp Zabel
2015-09-21 14:18 ` [PATCH V4 1/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings Rob Herring
2 siblings, 1 reply; 6+ messages in thread
From: Chen Feng @ 2015-09-17 12:00 UTC (permalink / raw)
To: p.zabel, linux-kernel, robh+dt, pawel.moll, xuwei5,
haojian.zhuang, zhangfei.gao, arnd, puck.chen
Cc: bintian.wang, xuyiping, devicetree, dan.zhao, suzhuangluan, w.f,
kong.kongxinwei, yudongbin, peter.panshilin, qijiwen
Add reset controller for hi6220 hikey-board.
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 3f03380..3f055e2 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -167,5 +167,12 @@
clocks = <&ao_ctrl 36>, <&ao_ctrl 36>;
clock-names = "uartclk", "apb_pclk";
};
+
+ reset_ctrl: reset_ctrl@f7030000 {
+ compatible = "hisilicon,hi6220-reset-ctl";
+ reg = <0x0 0xf7030000 0x0 0x1000>;
+ #reset-cells = <1>;
+ };
+
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH V4 3/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC
2015-09-17 12:00 ` [PATCH V4 3/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC Chen Feng
@ 2015-09-18 15:23 ` Philipp Zabel
2015-09-19 1:53 ` chenfeng
0 siblings, 1 reply; 6+ messages in thread
From: Philipp Zabel @ 2015-09-18 15:23 UTC (permalink / raw)
To: Chen Feng
Cc: linux-kernel, robh+dt, pawel.moll, xuwei5, haojian.zhuang,
zhangfei.gao, arnd, bintian.wang, xuyiping, devicetree, dan.zhao,
suzhuangluan, w.f, kong.kongxinwei, yudongbin, peter.panshilin,
qijiwen
Am Donnerstag, den 17.09.2015, 20:00 +0800 schrieb Chen Feng:
> Add reset controller for hi6220 hikey-board.
>
> Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
> ---
> arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> index 3f03380..3f055e2 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> @@ -167,5 +167,12 @@
> clocks = <&ao_ctrl 36>, <&ao_ctrl 36>;
> clock-names = "uartclk", "apb_pclk";
> };
> +
> + reset_ctrl: reset_ctrl@f7030000 {
> + compatible = "hisilicon,hi6220-reset-ctl";
> + reg = <0x0 0xf7030000 0x0 0x1000>;
> + #reset-cells = <1>;
> + };
> +
> };
> };
Applied all three, thanks.
If you want to take patch 3 through the hisilicon git tree instead, let
me know and I'll drop patch 3.
best regards
Philipp
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH V4 3/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC
2015-09-18 15:23 ` Philipp Zabel
@ 2015-09-19 1:53 ` chenfeng
0 siblings, 0 replies; 6+ messages in thread
From: chenfeng @ 2015-09-19 1:53 UTC (permalink / raw)
To: Philipp Zabel
Cc: linux-kernel, robh+dt, pawel.moll, xuwei5, haojian.zhuang,
zhangfei.gao, arnd, bintian.wang, xuyiping, devicetree, dan.zhao,
suzhuangluan, w.f, kong.kongxinwei, yudongbin, peter.panshilin,
qijiwen
Philipp,
On 2015/9/18 23:23, Philipp Zabel wrote:
> Am Donnerstag, den 17.09.2015, 20:00 +0800 schrieb Chen Feng:
>> Add reset controller for hi6220 hikey-board.
>>
>> Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
>> ---
>> arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 7 +++++++
>> 1 file changed, 7 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
>> index 3f03380..3f055e2 100644
>> --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
>> +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
>> @@ -167,5 +167,12 @@
>> clocks = <&ao_ctrl 36>, <&ao_ctrl 36>;
>> clock-names = "uartclk", "apb_pclk";
>> };
>> +
>> + reset_ctrl: reset_ctrl@f7030000 {
>> + compatible = "hisilicon,hi6220-reset-ctl";
>> + reg = <0x0 0xf7030000 0x0 0x1000>;
>> + #reset-cells = <1>;
>> + };
>> +
>> };
>> };
>
> Applied all three, thanks.
> If you want to take patch 3 through the hisilicon git tree instead, let
> me know and I'll drop patch 3.
>
Agree.
Please help apply all three. Thanks!
Puck
> best regards
> Philipp
>
>
> .
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V4 1/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings
2015-09-17 12:00 [PATCH V4 1/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings Chen Feng
2015-09-17 12:00 ` [PATCH V4 2/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC Chen Feng
2015-09-17 12:00 ` [PATCH V4 3/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC Chen Feng
@ 2015-09-21 14:18 ` Rob Herring
2 siblings, 0 replies; 6+ messages in thread
From: Rob Herring @ 2015-09-21 14:18 UTC (permalink / raw)
To: Chen Feng
Cc: p.zabel, linux-kernel, robh+dt, pawel.moll, xuwei5,
haojian.zhuang, zhangfei.gao, arnd, bintian.wang, xuyiping,
devicetree, dan.zhao, suzhuangluan, w.f, kong.kongxinwei,
yudongbin, peter.panshilin, qijiwen
On 09/17/2015 07:00 AM, Chen Feng wrote:
> Add DT bindings documentation for hi6220 SoC reset controller.
>
> Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
> ---
> .../bindings/reset/hisilicon,hi6220-reset.txt | 97 ++++++++++++++++++++++
> 1 file changed, 97 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
>
> diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
> new file mode 100644
> index 0000000..c0f7928
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
> @@ -0,0 +1,97 @@
> +Hisilicon System Reset Controller
> +======================================
> +
> +Please also refer to reset.txt in this directory for common reset
> +controller binding usage.
> +
> +The reset controller node must be a sub-node of the chip controller
> +node on SoCs.
> +
> +Required properties:
> +- compatible: may be "hisilicon,hi6220-reset-ctl"
> +- reg: should be register base and length as documented in the
> + datasheet
> +- #reset-cells: 1, see below
> +
> +Example:
> +
> + reset_ctrl: reset_ctrl@f7030000 {
> + compatible = "hisilicon,hi6220-reset-ctl";
> + reg = <0x0 0xf7030000 0x0 0x1000>;
> + #reset-cells = <1>;
> + };
> +
> +Specifying reset lines connected to IP modules
> +==============================================
> +example:
> +
> + uart1: uart1@..... {
serial@...
> + ...
> + resets = <&reset_ctrl 0x305>;
> + ...
> + };
> +
> +The following RESET_INDEX values are valid for hi6220 SoC:
Include the header file for these with this patch and just refer to it
rather than listing here.
Rob
> + PERIPH_RSTDIS0_MMC0 = 0x000,
> + PERIPH_RSTDIS0_MMC1 = 0x001,
> + PERIPH_RSTDIS0_MMC2 = 0x002,
> + PERIPH_RSTDIS0_NANDC = 0x003,
> + PERIPH_RSTDIS0_USBOTG_BUS = 0x004,
> + PERIPH_RSTDIS0_POR_PICOPHY = 0x005,
> + PERIPH_RSTDIS0_USBOTG = 0x006,
> + PERIPH_RSTDIS0_USBOTG_32K = 0x007,
> +
> + PERIPH_RSTDIS1_HIFI = 0x100,
> + PERIPH_RSTDIS1_DIGACODEC = 0x105,
> +
> + PERIPH_RSTEN2_IPF = 0x200,
> + PERIPH_RSTEN2_SOCP = 0x201,
> + PERIPH_RSTEN2_DMAC = 0x202,
> + PERIPH_RSTEN2_SECENG = 0x203,
> + PERIPH_RSTEN2_ABB = 0x204,
> + PERIPH_RSTEN2_HPM0 = 0x205,
> + PERIPH_RSTEN2_HPM1 = 0x206,
> + PERIPH_RSTEN2_HPM2 = 0x207,
> + PERIPH_RSTEN2_HPM3 = 0x208,
> +
> + PERIPH_RSTEN3_CSSYS = 0x300,
> + PERIPH_RSTEN3_I2C0 = 0x301,
> + PERIPH_RSTEN3_I2C1 = 0x302,
> + PERIPH_RSTEN3_I2C2 = 0x303,
> + PERIPH_RSTEN3_I2C3 = 0x304,
> + PERIPH_RSTEN3_UART1 = 0x305,
> + PERIPH_RSTEN3_UART2 = 0x306,
> + PERIPH_RSTEN3_UART3 = 0x307,
> + PERIPH_RSTEN3_UART4 = 0x308,
> + PERIPH_RSTEN3_SSP = 0x309,
> + PERIPH_RSTEN3_PWM = 0x30a,
> + PERIPH_RSTEN3_BLPWM = 0x30b,
> + PERIPH_RSTEN3_TSENSOR = 0x30c,
> + PERIPH_RSTEN3_DAPB = 0x312,
> + PERIPH_RSTEN3_HKADC = 0x313,
> + PERIPH_RSTEN3_CODEC_SSI = 0x314,
> + PERIPH_RSTEN3_PMUSSI1 = 0x316,
> +
> + PERIPH_RSTEN8_RS0 = 0x400,
> + PERIPH_RSTEN8_RS2 = 0x401,
> + PERIPH_RSTEN8_RS3 = 0x402,
> + PERIPH_RSTEN8_MS0 = 0x403,
> + PERIPH_RSTEN8_MS2 = 0x405,
> + PERIPH_RSTEN8_XG2RAM0 = 0x406,
> + PERIPH_RSTEN8_X2SRAM_TZMA = 0x407,
> + PERIPH_RSTEN8_SRAM = 0x408,
> + PERIPH_RSTEN8_HARQ = 0x40a,
> + PERIPH_RSTEN8_DDRC = 0x40c,
> + PERIPH_RSTEN8_DDRC_APB = 0x40d,
> + PERIPH_RSTEN8_DDRPACK_APB = 0x40e,
> + PERIPH_RSTEN8_DDRT = 0x411,
> +
> + PERIPH_RSDIST9_CARM_DAP = 0x500,
> + PERIPH_RSDIST9_CARM_ATB = 0x501,
> + PERIPH_RSDIST9_CARM_LBUS = 0x502,
> + PERIPH_RSDIST9_CARM_POR = 0x503,
> + PERIPH_RSDIST9_CARM_CORE = 0x504,
> + PERIPH_RSDIST9_CARM_DBG = 0x505,
> + PERIPH_RSDIST9_CARM_L2 = 0x506,
> + PERIPH_RSDIST9_CARM_SOCDBG = 0x507,
> + PERIPH_RSDIST9_CARM_ETM = 0x508,
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-09-21 14:18 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-09-17 12:00 [PATCH V4 1/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings Chen Feng
2015-09-17 12:00 ` [PATCH V4 2/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC Chen Feng
2015-09-17 12:00 ` [PATCH V4 3/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC Chen Feng
2015-09-18 15:23 ` Philipp Zabel
2015-09-19 1:53 ` chenfeng
2015-09-21 14:18 ` [PATCH V4 1/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings Rob Herring
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