From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sergei Shtylyov Subject: Re: [PATCH v10 3/3] arm64: dts: mediatek: add xHCI & usb phy for mt8173 Date: Sun, 18 Oct 2015 14:01:06 +0300 Message-ID: <56237BF2.5070809@cogentembedded.com> References: <1445140279-18121-1-git-send-email-chunfeng.yun@mediatek.com> <1445140279-18121-4-git-send-email-chunfeng.yun@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1445140279-18121-4-git-send-email-chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+glpam-linux-mediatek=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Chunfeng Yun , Mathias Nyman Cc: Mark Rutland , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Pawel Moll , Ian Campbell , Greg Kroah-Hartman , Sascha Hauer , linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Felipe Balbi , Kishon Vijay Abraham I , Rob Herring , linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Kumar Gala , Matthias Brugger , John Crispin , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Roger Quadros List-Id: devicetree@vger.kernel.org Hello. On 10/18/2015 6:51 AM, Chunfeng Yun wrote: > add xHCI and phy drivers for MT8173-EVB > > Signed-off-by: Chunfeng Yun [...] > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi > index d18ee42..46f5f50 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi [...] > @@ -487,6 +488,47 @@ > clock-names = "source", "hclk"; > status = "disabled"; > }; > + > + usb30: usb@11270000 { > + compatible = "mediatek,mt8173-xhci"; > + reg = <0 0x11270000 0 0x1000>, > + <0 0x11280700 0 0x0100>; > + interrupts = ; > + power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; > + clocks = <&topckgen CLK_TOP_USB30_SEL>, > + <&pericfg CLK_PERI_USB0>, > + <&pericfg CLK_PERI_USB1>; > + clock-names = "sys_ck", > + "wakeup_deb_p0", > + "wakeup_deb_p1"; > + phys = <&phy_port0 PHY_TYPE_USB3>, > + <&phy_port1 PHY_TYPE_USB2>; > + mediatek,syscon-wakeup = <&pericfg>; > + status = "okay"; > + }; > + > + u3phy: usb-phy@11290000 { > + compatible = "mediatek,mt8173-u3phy"; > + reg = <0 0x11290000 0 0x800>; > + clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; > + clock-names = "u3phya_ref"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + status = "okay"; Don't you need the "power-domains" prop here as well? > + > + phy_port0: port@11290800 { > + reg = <0 0x11290800 0 0x800>; > + #phy-cells = <1>; > + status = "okay"; > + }; > + > + phy_port1: port@11291000 { > + reg = <0 0x11291000 0 0x800>; > + #phy-cells = <1>; > + status = "okay"; > + }; > + }; > }; > }; > MBR, Sergei