[PATCH 0/4]

[PATCH 0/4]

[Caesar Wang]

We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.

Says:
The TSHUT temperature is setting more than 80 degree, the default
tshut polarity is HIGH.

If T > 80C, the OTP output the High Signal.
If T < 80C, the OTP output the Low Signal.

On the moment, the TSADC controller is reset, the tshut polarity will be
Low in a short period of time.

So:
If T < 80C, the OTP output the High Signal.
If T > 80C, the OTP output the Low Signal.

In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can
accept the reset response time to avoid this issue.

In other words, the system will be always reboot if we make the OTP pin
is connected the others IC to control the power.

Tested on box board.



Caesar Wang (4):
  dt-bindings: Sync the dts to this document
  thermal: rockchip: ensure the otp state before resetting the
    controller
  thermal: rockchip: change the TSHUT default state
  ARM: dts: rockchip: Add the OTP gpio pinctrl

 .../bindings/thermal/rockchip-thermal.txt          |  5 ++--
 arch/arm/boot/dts/rk3288.dtsi                      |  9 ++++--
 drivers/thermal/rockchip_thermal.c                 | 34 +++++++++++++++++++++-
 3 files changed, 43 insertions(+), 5 deletions(-)

-- 
1.9.1

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[PATCH 1/4] dt-bindings: Sync the dts to this document

[Caesar Wang]

Add the OTP gpio state, we need switch the pin to gpio state
before the TSADC controller is reset.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

 Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
index ef802de..2587f34b 100644
--- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
@@ -27,8 +27,9 @@ tsadc: tsadc@ff280000 {
 	clock-names = "tsadc", "apb_pclk";
 	resets = <&cru SRST_TSADC>;
 	reset-names = "tsadc-apb";
-	pinctrl-names = "default";
-	pinctrl-0 = <&otp_out>;
+	pinctrl-names = "default", "otp_out";
+	pinctrl-0 = <&otp_gpio>;
+	pinctrl-1 = <&otp_out>;
 	#thermal-sensor-cells = <1>;
 	rockchip,hw-tshut-temp = <95000>;
 	rockchip,hw-tshut-mode = <0>;
-- 
1.9.1

[PATCH 4/4] ARM: dts: rockchip: Add the OTP gpio pinctrl

[Caesar Wang]

We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.

Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---

 arch/arm/boot/dts/rk3288.dtsi | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 906e938..b59c451 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -447,8 +447,9 @@
 		clock-names = "tsadc", "apb_pclk";
 		resets = <&cru SRST_TSADC>;
 		reset-names = "tsadc-apb";
-		pinctrl-names = "default";
-		pinctrl-0 = <&otp_out>;
+		pinctrl-names = "default", "otp_out";
+		pinctrl-0 = <&otp_gpio>;
+		pinctrl-1 = <&otp_out>;
 		#thermal-sensor-cells = <1>;
 		rockchip,hw-tshut-temp = <95000>;
 		status = "disabled";
@@ -1273,6 +1274,10 @@
 		};
 
 		tsadc {
+			otp_gpio: otp-gpio {
+				rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
+
 			otp_out: otp-out {
 				rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
 			};
-- 
1.9.1

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Re: [PATCH 0/4] Add the OTP gpio pinctrl to fix the TSHUT issue

[Caesar Wang]

The subject is deleted by my finger.

在 2015年10月20日 17:11, Caesar Wang 写道:
> We need the OTP pin is gpio state before resetting the TSADC controller,
> since the tshut polarity will generate a high signal.
>
> Says:
> The TSHUT temperature is setting more than 80 degree, the default
> tshut polarity is HIGH.
>
> If T > 80C, the OTP output the High Signal.
> If T < 80C, the OTP output the Low Signal.
>
> On the moment, the TSADC controller is reset, the tshut polarity will be
> Low in a short period of time.
>
> So:
> If T < 80C, the OTP output the High Signal.
> If T > 80C, the OTP output the Low Signal.
>
> In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can
> accept the reset response time to avoid this issue.
>
> In other words, the system will be always reboot if we make the OTP pin
> is connected the others IC to control the power.
>
> Tested on box board.
>
>
>
> Caesar Wang (4):
>    dt-bindings: Sync the dts to this document
>    thermal: rockchip: ensure the otp state before resetting the
>      controller
>    thermal: rockchip: change the TSHUT default state
>    ARM: dts: rockchip: Add the OTP gpio pinctrl
>
>   .../bindings/thermal/rockchip-thermal.txt          |  5 ++--
>   arch/arm/boot/dts/rk3288.dtsi                      |  9 ++++--
>   drivers/thermal/rockchip_thermal.c                 | 34 +++++++++++++++++++++-
>   3 files changed, 43 insertions(+), 5 deletions(-)
>

-- 
Thanks,
Caesar