[v2 00/10] add support SATA for BMIPS_GENERIC

[v2 00/10] add support SATA for BMIPS_GENERIC

[Jaedon Shin]

Hi all,

This patch series add support SATA for BMIPS_GENERIC.

Ralf,
I request you to drop already submitted patches for NAND deivce nodes.
They are merge conflict with these.
http://patchwork.linux-mips.org/patch/10577/
http://patchwork.linux-mips.org/patch/10578/
http://patchwork.linux-mips.org/patch/10579/
http://patchwork.linux-mips.org/patch/10580/

Changes in v2:
- Adds quick for ncq
- Adds quick for phy interface control
- Remove unused definitions in ahci_brcmstb
- Combines compatible string

Jaedon Shin (10):
  ata: ahci_brcmstb: add quick for broken ncq
  ata: ahci_brcmstb: add support MIPS-based platforms
  ata: ahci_brcmstb: add quick for broken phy
  ata: ahci_brcmstb: remove unused definitions
  phy: phy_brcmstb_sata: remove duplicate definitions
  phy: phy_brcmstb_sata: add data for phy version
  phy: phy_brcmstb_sata: add support MIPS-based platforms
  MIPS: BMIPS: brcmstb: add SATA/PHY nodes for bcm7425
  MIPS: BMIPS: brcmstb: add SATA/PHY nodes for bcm7346
  MIPS: BMIPS: brcmstb: add SATA/PHY nodes for bcm7362

 .../devicetree/bindings/ata/brcm,sata-brcmstb.txt  |  8 +++-
 .../bindings/phy/brcm,brcmstb-sata-phy.txt         |  1 +
 arch/mips/boot/dts/brcm/bcm7346.dtsi               | 42 +++++++++++++++++
 arch/mips/boot/dts/brcm/bcm7362.dtsi               | 42 +++++++++++++++++
 arch/mips/boot/dts/brcm/bcm7425.dtsi               | 42 +++++++++++++++++
 arch/mips/boot/dts/brcm/bcm97346dbsmb.dts          |  8 ++++
 arch/mips/boot/dts/brcm/bcm97362svmb.dts           |  8 ++++
 drivers/ata/Kconfig                                |  2 +-
 drivers/ata/ahci_brcmstb.c                         | 55 +++++++++++++++++++++-
 drivers/phy/Kconfig                                |  4 +-
 drivers/phy/phy-brcmstb-sata.c                     | 47 ++++++++++++++----
 11 files changed, 242 insertions(+), 17 deletions(-)

-- 
2.6.2

[v2 01/10] ata: ahci_brcmstb: add quick for broken ncq

[Jaedon Shin]

Add quick for bronken ncq. The chipsets (eg. BCM7439A0, BCM7445A0 and
BCM7445B0) need a workaround disabling NCQ. and it may need the
MIPS-based set-top box platforms.

Signed-off-by: Jaedon Shin <jaedon.shin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 .../devicetree/bindings/ata/brcm,sata-brcmstb.txt  |  3 ++
 drivers/ata/ahci_brcmstb.c                         | 42 ++++++++++++++++++++++
 2 files changed, 45 insertions(+)

diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt b/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
index 20ac9bbfa1fd..4650c0aff6b3 100644
--- a/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
+++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
@@ -10,6 +10,9 @@ Required properties:
 - reg-names          : "ahci" and "top-ctrl"
 - interrupts         : interrupt mapping for SATA IRQ
 
+Optional properties:
+- brcm,broken-ncq    : if present, NCQ is unusable
+
 Also see ahci-platform.txt.
 
 Example:
diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
index 14b7305d2ba0..a2df76698adb 100644
--- a/drivers/ata/ahci_brcmstb.c
+++ b/drivers/ata/ahci_brcmstb.c
@@ -69,10 +69,15 @@
 	(DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) |		\
 	(MMIO_ENDIAN << MMIO_ENDIAN_SHIFT))
 
+enum brcm_ahci_quicks {
+	BRCM_AHCI_QUICK_NONCQ		= BIT(0),
+};
+
 struct brcm_ahci_priv {
 	struct device *dev;
 	void __iomem *top_ctrl;
 	u32 port_mask;
+	u32 quicks;
 };
 
 static const struct ata_port_info ahci_brcm_port_info = {
@@ -209,6 +214,39 @@ static void brcm_sata_init(struct brcm_ahci_priv *priv)
 			   priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
 }
 
+static void brcm_sata_quick(struct platform_device *pdev,
+			    struct brcm_ahci_priv *priv)
+{
+	void __iomem *ahci;
+	struct resource *res;
+	u32 reg;
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ahci");
+	ahci = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(ahci))
+		return;
+
+	if (priv->quicks & BRCM_AHCI_QUICK_NONCQ) {
+		reg  = readl(priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
+		reg |= OVERRIDE_HWINIT;
+		writel(reg, priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
+
+		/* Clear out the NCQ bit so the AHCI driver will not issue
+		 * FPDMA/NCQ commands.
+		 */
+		reg = readl(ahci + HOST_CAP);
+		reg &= ~HOST_CAP_NCQ;
+		writel(reg, ahci + HOST_CAP);
+
+		reg = readl(priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
+		reg &= ~OVERRIDE_HWINIT;
+		writel(reg, priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
+	}
+
+	devm_iounmap(&pdev->dev, ahci);
+	devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
+}
+
 #ifdef CONFIG_PM_SLEEP
 static int brcm_ahci_suspend(struct device *dev)
 {
@@ -256,7 +294,11 @@ static int brcm_ahci_probe(struct platform_device *pdev)
 	if (IS_ERR(priv->top_ctrl))
 		return PTR_ERR(priv->top_ctrl);
 
+	if (of_property_read_bool(dev->of_node, "brcm,broken-ncq"))
+		priv->quicks |= BRCM_AHCI_QUICK_NONCQ;
+
 	brcm_sata_init(priv);
+	brcm_sata_quick(pdev, priv);
 
 	priv->port_mask = brcm_ahci_get_portmask(pdev, priv);
 	if (!priv->port_mask)
-- 
2.6.2

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[v2 02/10] ata: ahci_brcmstb: add support MIPS-based platforms

[Jaedon Shin]

The BCM7xxx ARM-based and MIPS-based platforms share a similar hardware
block for AHCI SATA3.

The BCM7425 is flagship chipset of 40nm class. Other MIPS-based 40nm
chipsets has same hardware block. so the compatible string may be use
brcm,bcm7425-ahci.

Signed-off-by: Jaedon Shin <jaedon.shin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt | 4 ++--
 drivers/ata/Kconfig                                         | 2 +-
 drivers/ata/ahci_brcmstb.c                                  | 1 +
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt b/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
index 4650c0aff6b3..488a383ce202 100644
--- a/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
+++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
@@ -4,8 +4,8 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
 Each SATA controller should have its own node.
 
 Required properties:
-- compatible         : compatible list, may contain "brcm,bcm7445-ahci" and/or
-                       "brcm,sata3-ahci"
+- compatible         : compatible list, may contain "brcm,bcm7445-ahci" or
+                       "brcm,bcm7425-ahci" or "brcm,sata3-ahci"
 - reg                : register mappings for AHCI and SATA_TOP_CTRL
 - reg-names          : "ahci" and "top-ctrl"
 - interrupts         : interrupt mapping for SATA IRQ
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 15e40ee62a94..8f535a88a0c7 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -100,7 +100,7 @@ config SATA_AHCI_PLATFORM
 
 config AHCI_BRCMSTB
 	tristate "Broadcom STB AHCI SATA support"
-	depends on ARCH_BRCMSTB
+	depends on ARCH_BRCMSTB || BMIPS_GENERIC
 	help
 	  This option enables support for the AHCI SATA3 controller found on
 	  STB SoC's.
diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
index a2df76698adb..e53962cb48ee 100644
--- a/drivers/ata/ahci_brcmstb.c
+++ b/drivers/ata/ahci_brcmstb.c
@@ -343,6 +343,7 @@ static int brcm_ahci_remove(struct platform_device *pdev)
 
 static const struct of_device_id ahci_of_match[] = {
 	{.compatible = "brcm,bcm7445-ahci"},
+	{.compatible = "brcm,bcm7425-ahci"},
 	{},
 };
 MODULE_DEVICE_TABLE(of, ahci_of_match);
-- 
2.6.2

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[v2 03/10] ata: ahci_brcmstb: add quick for broken phy

[Jaedon Shin]

Add quick for broken phy. The ARM-based 28nm chipsets have four phy
interface control registers and each port has two registers. But, The
MIPS-based 40nm chipsets have three. and there are no information and
documentation. The legacy version of broadcom's strict-ahci based
initial code did not control these registers.

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
---
 Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt |  1 +
 drivers/ata/ahci_brcmstb.c                                  | 10 ++++++++++
 2 files changed, 11 insertions(+)

diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt b/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
index 488a383ce202..0f0925d58188 100644
--- a/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
+++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
@@ -12,6 +12,7 @@ Required properties:
 
 Optional properties:
 - brcm,broken-ncq    : if present, NCQ is unusable
+- brcm,broken-phy    : if present, to control phy interface is unusable
 
 Also see ahci-platform.txt.
 
diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
index e53962cb48ee..c61303f7c7dc 100644
--- a/drivers/ata/ahci_brcmstb.c
+++ b/drivers/ata/ahci_brcmstb.c
@@ -71,6 +71,7 @@
 
 enum brcm_ahci_quicks {
 	BRCM_AHCI_QUICK_NONCQ		= BIT(0),
+	BRCM_AHCI_QUICK_NOPHY		= BIT(1),
 };
 
 struct brcm_ahci_priv {
@@ -119,6 +120,9 @@ static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
 	void __iomem *p;
 	u32 reg;
 
+	if (priv->quicks & BRCM_AHCI_QUICK_NOPHY)
+		return;
+
 	/* clear PHY_DEFAULT_POWER_STATE */
 	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
 	reg = brcm_sata_readreg(p);
@@ -148,6 +152,9 @@ static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
 	void __iomem *p;
 	u32 reg;
 
+	if (priv->quicks & BRCM_AHCI_QUICK_NOPHY)
+		return;
+
 	/* power-off the PHY digital logic */
 	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
 	reg = brcm_sata_readreg(p);
@@ -297,6 +304,9 @@ static int brcm_ahci_probe(struct platform_device *pdev)
 	if (of_property_read_bool(dev->of_node, "brcm,broken-ncq"))
 		priv->quicks |= BRCM_AHCI_QUICK_NONCQ;
 
+	if (of_property_read_bool(dev->of_node, "brcm,broken-phy"))
+		priv->quicks |= BRCM_AHCI_QUICK_NOPHY;
+
 	brcm_sata_init(priv);
 	brcm_sata_quick(pdev, priv);
 
-- 
2.6.2

[v2 04/10] ata: ahci_brcmstb: remove unused definitions

[Jaedon Shin]

Remove unused definitions.

The MIPS-based 40nm chipsets has different offset. The
SATA_TOP_CTRL_SATA_TP_OUT offset is 0x18 and the
SATA_TOP_CTRL_CLIENT_INIT_CTRL is not exist. So, To remove do to avoid
confusion.

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
---
 drivers/ata/ahci_brcmstb.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
index c61303f7c7dc..2d25a28f4f64 100644
--- a/drivers/ata/ahci_brcmstb.c
+++ b/drivers/ata/ahci_brcmstb.c
@@ -52,8 +52,6 @@
   #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET		BIT(14)
  #define SATA_TOP_CTRL_PHY_OFFS				0x8
  #define SATA_TOP_MAX_PHYS				2
-#define SATA_TOP_CTRL_SATA_TP_OUT			0x1c
-#define SATA_TOP_CTRL_CLIENT_INIT_CTRL			0x20
 
 /* On big-endian MIPS, buses are reversed to big endian, so switch them back */
 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
-- 
2.6.2

[v2 05/10] phy: phy_brcmstb_sata: remove duplicate definitions

[Jaedon Shin]

Remove duplicate definitions.

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
---
 drivers/phy/phy-brcmstb-sata.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/phy/phy-brcmstb-sata.c b/drivers/phy/phy-brcmstb-sata.c
index 8a2cb16a1937..0be55dafe9ea 100644
--- a/drivers/phy/phy-brcmstb-sata.c
+++ b/drivers/phy/phy-brcmstb-sata.c
@@ -26,8 +26,6 @@
 
 #define SATA_MDIO_BANK_OFFSET				0x23c
 #define SATA_MDIO_REG_OFFSET(ofs)			((ofs) * 4)
-#define SATA_MDIO_REG_SPACE_SIZE			0x1000
-#define SATA_MDIO_REG_LENGTH				0x1f00
 
 #define MAX_PORTS					2
 
-- 
2.6.2

[v2 06/10] phy: phy_brcmstb_sata: add data for phy version

[Jaedon Shin]

Add data of device for phy version. and 28nm version is default.

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
---
 drivers/phy/phy-brcmstb-sata.c | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/drivers/phy/phy-brcmstb-sata.c b/drivers/phy/phy-brcmstb-sata.c
index 0be55dafe9ea..5de394f589c8 100644
--- a/drivers/phy/phy-brcmstb-sata.c
+++ b/drivers/phy/phy-brcmstb-sata.c
@@ -30,7 +30,11 @@
 #define MAX_PORTS					2
 
 /* Register offset between PHYs in PCB space */
-#define SATA_MDIO_REG_SPACE_SIZE			0x1000
+#define SATA_MDIO_REG_28NM_SPACE_SIZE			0x1000
+
+enum brcm_sata_phy_version {
+	BRCM_SATA_PHY_28NM,
+};
 
 struct brcm_sata_port {
 	int portnum;
@@ -42,6 +46,7 @@ struct brcm_sata_port {
 struct brcm_sata_phy {
 	struct device *dev;
 	void __iomem *phy_base;
+	enum brcm_sata_phy_version version;
 
 	struct brcm_sata_port phys[MAX_PORTS];
 };
@@ -64,8 +69,12 @@ enum sata_mdio_phy_regs_28nm {
 static inline void __iomem *brcm_sata_phy_base(struct brcm_sata_port *port)
 {
 	struct brcm_sata_phy *priv = port->phy_priv;
+	u32 offset;
 
-	return priv->phy_base + (port->portnum * SATA_MDIO_REG_SPACE_SIZE);
+	if (priv->version == BRCM_SATA_PHY_28NM)
+		offset = SATA_MDIO_REG_28NM_SPACE_SIZE;
+
+	return priv->phy_base + (port->portnum * offset);
 }
 
 static void brcm_sata_mdio_wr(void __iomem *addr, u32 bank, u32 ofs,
@@ -126,7 +135,8 @@ static const struct phy_ops phy_ops_28nm = {
 };
 
 static const struct of_device_id brcm_sata_phy_of_match[] = {
-	{ .compatible	= "brcm,bcm7445-sata-phy" },
+	{ .compatible	= "brcm,bcm7445-sata-phy",
+	  .data = (void *)BRCM_SATA_PHY_28NM },
 	{},
 };
 MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
@@ -135,6 +145,7 @@ static int brcm_sata_phy_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct device_node *dn = dev->of_node, *child;
+	const struct of_device_id *of_id;
 	struct brcm_sata_phy *priv;
 	struct resource *res;
 	struct phy_provider *provider;
@@ -154,6 +165,12 @@ static int brcm_sata_phy_probe(struct platform_device *pdev)
 	if (IS_ERR(priv->phy_base))
 		return PTR_ERR(priv->phy_base);
 
+	of_id = of_match_node(brcm_sata_phy_of_match, dn);
+	if (of_id)
+		priv->version = (enum brcm_sata_phy_version)of_id->data;
+	else
+		priv->version = BRCM_SATA_PHY_28NM;
+
 	for_each_available_child_of_node(dn, child) {
 		unsigned int id;
 		struct brcm_sata_port *port;
-- 
2.6.2

[v2 07/10] phy: phy_brcmstb_sata: add support MIPS-based platforms

[Jaedon Shin]

The BCM7xxx ARM-based and MIPS-based platforms share a similar hardware
block for AHCI SATA3.

The BCM7425 is flagship chipset of 40nm class. Other MIPS-based 40nm
chipsets has same hardware block. so the compatible string may be use
brcm,bcm7425-sata-phy.

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
---
 .../bindings/phy/brcm,brcmstb-sata-phy.txt         |  1 +
 drivers/phy/Kconfig                                |  4 ++--
 drivers/phy/phy-brcmstb-sata.c                     | 24 ++++++++++++++++------
 3 files changed, 21 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt b/Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt
index 7f81ef90146a..c4b31075ffef 100644
--- a/Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt
+++ b/Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt
@@ -3,6 +3,7 @@
 Required properties:
 - compatible: should be one or more of
      "brcm,bcm7445-sata-phy"
+     "brcm,bcm7425-sata-phy"
      "brcm,phy-sata3"
 - address-cells: should be 1
 - size-cells: should be 0
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 47da573d0bab..c83e48661fd7 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -364,11 +364,11 @@ config PHY_TUSB1210
 
 config PHY_BRCMSTB_SATA
 	tristate "Broadcom STB SATA PHY driver"
-	depends on ARCH_BRCMSTB
+	depends on ARCH_BRCMSTB || BMIPS_GENERIC
 	depends on OF
 	select GENERIC_PHY
 	help
-	  Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
+	  Enable this to support the SATA3 PHY on 28nm or 40nm Broadcom STB SoCs.
 	  Likely useful only with CONFIG_SATA_BRCMSTB enabled.
 
 endmenu
diff --git a/drivers/phy/phy-brcmstb-sata.c b/drivers/phy/phy-brcmstb-sata.c
index 5de394f589c8..c8243581f196 100644
--- a/drivers/phy/phy-brcmstb-sata.c
+++ b/drivers/phy/phy-brcmstb-sata.c
@@ -32,8 +32,14 @@
 /* Register offset between PHYs in PCB space */
 #define SATA_MDIO_REG_28NM_SPACE_SIZE			0x1000
 
+/* The older SATA PHY registers duplicated per port registers within the map,
+ * rather than having a separate map per port.
+ */
+#define SATA_MDIO_REG_40NM_SPACE_SIZE			0x10
+
 enum brcm_sata_phy_version {
 	BRCM_SATA_PHY_28NM,
+	BRCM_SATA_PHY_40NM,
 };
 
 struct brcm_sata_port {
@@ -51,7 +57,7 @@ struct brcm_sata_phy {
 	struct brcm_sata_port phys[MAX_PORTS];
 };
 
-enum sata_mdio_phy_regs_28nm {
+enum sata_mdio_phy_regs {
 	PLL_REG_BANK_0				= 0x50,
 	PLL_REG_BANK_0_PLLCONTROL_0		= 0x81,
 
@@ -69,10 +75,14 @@ enum sata_mdio_phy_regs_28nm {
 static inline void __iomem *brcm_sata_phy_base(struct brcm_sata_port *port)
 {
 	struct brcm_sata_phy *priv = port->phy_priv;
-	u32 offset;
+	u32 offset = 0;
 
 	if (priv->version == BRCM_SATA_PHY_28NM)
 		offset = SATA_MDIO_REG_28NM_SPACE_SIZE;
+	else if (priv->version == BRCM_SATA_PHY_40NM)
+		offset = SATA_MDIO_REG_40NM_SPACE_SIZE;
+	else
+		dev_err(priv->dev, "should not happen\n");
 
 	return priv->phy_base + (port->portnum * offset);
 }
@@ -93,7 +103,7 @@ static void brcm_sata_mdio_wr(void __iomem *addr, u32 bank, u32 ofs,
 #define FMAX_VAL_DEFAULT	0x3df
 #define FMAX_VAL_SSC		0x83
 
-static void brcm_sata_cfg_ssc_28nm(struct brcm_sata_port *port)
+static void brcm_sata_cfg_ssc(struct brcm_sata_port *port)
 {
 	void __iomem *base = brcm_sata_phy_base(port);
 	struct brcm_sata_phy *priv = port->phy_priv;
@@ -124,12 +134,12 @@ static int brcm_sata_phy_init(struct phy *phy)
 {
 	struct brcm_sata_port *port = phy_get_drvdata(phy);
 
-	brcm_sata_cfg_ssc_28nm(port);
+	brcm_sata_cfg_ssc(port);
 
 	return 0;
 }
 
-static const struct phy_ops phy_ops_28nm = {
+static const struct phy_ops phy_ops = {
 	.init		= brcm_sata_phy_init,
 	.owner		= THIS_MODULE,
 };
@@ -137,6 +147,8 @@ static const struct phy_ops phy_ops_28nm = {
 static const struct of_device_id brcm_sata_phy_of_match[] = {
 	{ .compatible	= "brcm,bcm7445-sata-phy",
 	  .data = (void *)BRCM_SATA_PHY_28NM },
+	{ .compatible	= "brcm,bcm7425-sata-phy",
+	  .data = (void *)BRCM_SATA_PHY_40NM },
 	{},
 };
 MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
@@ -193,7 +205,7 @@ static int brcm_sata_phy_probe(struct platform_device *pdev)
 		port = &priv->phys[id];
 		port->portnum = id;
 		port->phy_priv = priv;
-		port->phy = devm_phy_create(dev, child, &phy_ops_28nm);
+		port->phy = devm_phy_create(dev, child, &phy_ops);
 		port->ssc_en = of_property_read_bool(child, "brcm,enable-ssc");
 		if (IS_ERR(port->phy)) {
 			dev_err(dev, "failed to create PHY\n");
-- 
2.6.2

[v2 08/10] MIPS: BMIPS: brcmstb: add SATA/PHY nodes for bcm7425

[Jaedon Shin]

Add AHCI and PHY device nodes to MIPS-based BCM7425 set-top box
platform.

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
---
 arch/mips/boot/dts/brcm/bcm7425.dtsi | 42 ++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi b/arch/mips/boot/dts/brcm/bcm7425.dtsi
index 5b660b617ead..e24d41ab4e30 100644
--- a/arch/mips/boot/dts/brcm/bcm7425.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi
@@ -221,5 +221,47 @@
 			interrupts = <73>;
 			status = "disabled";
 		};
+
+		sata: sata@181000 {
+			compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
+			reg-names = "ahci", "top-ctrl";
+			reg = <0x181000 0xa9c>, <0x180020 0x1c>;
+			interrupt-parent = <&periph_intc>;
+			interrupts = <40>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			brcm,broken-ncq;
+			brcm,broken-phy;
+			status = "disabled";
+
+			sata0: sata-port@0 {
+				reg = <0>;
+				phys = <&sata_phy0>;
+			};
+
+			sata1: sata-port@1 {
+				reg = <1>;
+				phys = <&sata_phy1>;
+			};
+		};
+
+		sata_phy: sata-phy@1800000 {
+			compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
+			reg = <0x180100 0x0eff>;
+			reg-names = "phy";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			sata_phy0: sata-phy@0 {
+				reg = <0>;
+				#phy-cells = <0>;
+			};
+
+			sata_phy1: sata-phy@1 {
+				reg = <1>;
+				#phy-cells = <0>;
+			};
+		};
 	};
 };
-- 
2.6.2

[v2 09/10] MIPS: BMIPS: brcmstb: add SATA/PHY nodes for bcm7346

[Jaedon Shin]

Add AHCI and PHY device nodes to MIPS-based BCM7346 set-top box
platform.

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
---
 arch/mips/boot/dts/brcm/bcm7346.dtsi      | 42 +++++++++++++++++++++++++++++++
 arch/mips/boot/dts/brcm/bcm97346dbsmb.dts |  8 ++++++
 2 files changed, 50 insertions(+)

diff --git a/arch/mips/boot/dts/brcm/bcm7346.dtsi b/arch/mips/boot/dts/brcm/bcm7346.dtsi
index d817bb46b934..8535a5676d48 100644
--- a/arch/mips/boot/dts/brcm/bcm7346.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7346.dtsi
@@ -246,5 +246,47 @@
 			interrupts = <76>;
 			status = "disabled";
 		};
+
+		sata: sata@181000 {
+			compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
+			reg-names = "ahci", "top-ctrl";
+			reg = <0x181000 0xa9c>, <0x180020 0x1c>;
+			interrupt-parent = <&periph_intc>;
+			interrupts = <40>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			brcm,broken-ncq;
+			brcm,broken-phy;
+			status = "disabled";
+
+			sata0: sata-port@0 {
+				reg = <0>;
+				phys = <&sata_phy0>;
+			};
+
+			sata1: sata-port@1 {
+				reg = <1>;
+				phys = <&sata_phy1>;
+			};
+		};
+
+		sata_phy: sata-phy@1800000 {
+			compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
+			reg = <0x180100 0x0eff>;
+			reg-names = "phy";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			sata_phy0: sata-phy@0 {
+				reg = <0>;
+				#phy-cells = <0>;
+			};
+
+			sata_phy1: sata-phy@1 {
+				reg = <1>;
+				#phy-cells = <0>;
+			};
+		};
 	};
 };
diff --git a/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts b/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
index 3fe0445b9d37..e147c61178cc 100644
--- a/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
@@ -64,3 +64,11 @@
 &ohci3 {
 	status = "okay";
 };
+
+&sata {
+	status = "okay";
+};
+
+&sata_phy {
+	status = "okay";
+};
-- 
2.6.2

[v2 10/10] MIPS: BMIPS: brcmstb: add SATA/PHY nodes for bcm7362

[Jaedon Shin]

Add AHCI and PHY device nodes to MIPS-based BCM7362 set-top box
platform.

Signed-off-by: Jaedon Shin <jaedon.shin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/mips/boot/dts/brcm/bcm7362.dtsi     | 42 ++++++++++++++++++++++++++++++++
 arch/mips/boot/dts/brcm/bcm97362svmb.dts |  8 ++++++
 2 files changed, 50 insertions(+)

diff --git a/arch/mips/boot/dts/brcm/bcm7362.dtsi b/arch/mips/boot/dts/brcm/bcm7362.dtsi
index 6e65db86fc61..53b73de9066c 100644
--- a/arch/mips/boot/dts/brcm/bcm7362.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7362.dtsi
@@ -189,5 +189,47 @@
 			interrupts = <66>;
 			status = "disabled";
 		};
+
+		sata: sata@181000 {
+			compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
+			reg-names = "ahci", "top-ctrl";
+			reg = <0x181000 0xa9c>, <0x180020 0x1c>;
+			interrupt-parent = <&periph_intc>;
+			interrupts = <86>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			brcm,broken-ncq;
+			brcm,broken-phy;
+			status = "disabled";
+
+			sata0: sata-port@0 {
+				reg = <0>;
+				phys = <&sata_phy0>;
+			};
+
+			sata1: sata-port@1 {
+				reg = <1>;
+				phys = <&sata_phy1>;
+			};
+		};
+
+		sata_phy: sata-phy@1800000 {
+			compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
+			reg = <0x180100 0x0eff>;
+			reg-names = "phy";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			sata_phy0: sata-phy@0 {
+				reg = <0>;
+				#phy-cells = <0>;
+			};
+
+			sata_phy1: sata-phy@1 {
+				reg = <1>;
+				#phy-cells = <0>;
+			};
+		};
 	};
 };
diff --git a/arch/mips/boot/dts/brcm/bcm97362svmb.dts b/arch/mips/boot/dts/brcm/bcm97362svmb.dts
index 739c2ef5663b..ef9a69b79bc4 100644
--- a/arch/mips/boot/dts/brcm/bcm97362svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97362svmb.dts
@@ -40,3 +40,11 @@
 &ohci0 {
 	status = "okay";
 };
+
+&sata {
+	status = "okay";
+};
+
+&sata_phy {
+	status = "okay";
+};
-- 
2.6.2

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Re: [v2 03/10] ata: ahci_brcmstb: add quick for broken phy

[Rob Herring]

On Tue, Oct 27, 2015 at 1:48 AM, Jaedon Shin <jaedon.shin@gmail.com> wrote:
> Add quick for broken phy. The ARM-based 28nm chipsets have four phy

I believe you mean "quirk".

> interface control registers and each port has two registers. But, The

registers, but the...

> MIPS-based 40nm chipsets have three. and there are no information and

s/and there/There/

> documentation. The legacy version of broadcom's strict-ahci based
> initial code did not control these registers.
>
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
> ---
>  Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt |  1 +

Other than the commit message:

Acked-by: Rob Herring <robh@kernel.org>

>  drivers/ata/ahci_brcmstb.c                                  | 10 ++++++++++
>  2 files changed, 11 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt b/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
> index 488a383ce202..0f0925d58188 100644
> --- a/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
> +++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
> @@ -12,6 +12,7 @@ Required properties:
>
>  Optional properties:
>  - brcm,broken-ncq    : if present, NCQ is unusable
> +- brcm,broken-phy    : if present, to control phy interface is unusable
>
>  Also see ahci-platform.txt.
>
> diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
> index e53962cb48ee..c61303f7c7dc 100644
> --- a/drivers/ata/ahci_brcmstb.c
> +++ b/drivers/ata/ahci_brcmstb.c
> @@ -71,6 +71,7 @@
>
>  enum brcm_ahci_quicks {
>         BRCM_AHCI_QUICK_NONCQ           = BIT(0),
> +       BRCM_AHCI_QUICK_NOPHY           = BIT(1),
>  };
>
>  struct brcm_ahci_priv {
> @@ -119,6 +120,9 @@ static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
>         void __iomem *p;
>         u32 reg;
>
> +       if (priv->quicks & BRCM_AHCI_QUICK_NOPHY)
> +               return;
> +
>         /* clear PHY_DEFAULT_POWER_STATE */
>         p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
>         reg = brcm_sata_readreg(p);
> @@ -148,6 +152,9 @@ static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
>         void __iomem *p;
>         u32 reg;
>
> +       if (priv->quicks & BRCM_AHCI_QUICK_NOPHY)
> +               return;
> +
>         /* power-off the PHY digital logic */
>         p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
>         reg = brcm_sata_readreg(p);
> @@ -297,6 +304,9 @@ static int brcm_ahci_probe(struct platform_device *pdev)
>         if (of_property_read_bool(dev->of_node, "brcm,broken-ncq"))
>                 priv->quicks |= BRCM_AHCI_QUICK_NONCQ;
>
> +       if (of_property_read_bool(dev->of_node, "brcm,broken-phy"))
> +               priv->quicks |= BRCM_AHCI_QUICK_NOPHY;
> +
>         brcm_sata_init(priv);
>         brcm_sata_quick(pdev, priv);
>
> --
> 2.6.2
>

Re: [v2 03/10] ata: ahci_brcmstb: add quick for broken phy

[Jaedon Shin]

On Oct 27, 2015, at 5:17 PM, Rob Herring <robh+dt@kernel.org> wrote:
> 
> On Tue, Oct 27, 2015 at 1:48 AM, Jaedon Shin <jaedon.shin@gmail.com> wrote:
>> Add quick for broken phy. The ARM-based 28nm chipsets have four phy
> 
> I believe you mean "quirk".
> 

Oops! All the "quick" of patches should be changed to a "quirk".

Thanks.

>> interface control registers and each port has two registers. But, The
> 
> registers, but the...
> 
>> MIPS-based 40nm chipsets have three. and there are no information and
> 
> s/and there/There/
> 
>> documentation. The legacy version of broadcom's strict-ahci based
>> initial code did not control these registers.
>> 
>> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
>> ---
>> Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt |  1 +
> 
> Other than the commit message:
> 
> Acked-by: Rob Herring <robh@kernel.org>
> 
>> drivers/ata/ahci_brcmstb.c                                  | 10 ++++++++++
>> 2 files changed, 11 insertions(+)
>> 
>> diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt b/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
>> index 488a383ce202..0f0925d58188 100644
>> --- a/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
>> +++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
>> @@ -12,6 +12,7 @@ Required properties:
>> 
>> Optional properties:
>> - brcm,broken-ncq    : if present, NCQ is unusable
>> +- brcm,broken-phy    : if present, to control phy interface is unusable
>> 
>> Also see ahci-platform.txt.
>> 
>> diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
>> index e53962cb48ee..c61303f7c7dc 100644
>> --- a/drivers/ata/ahci_brcmstb.c
>> +++ b/drivers/ata/ahci_brcmstb.c
>> @@ -71,6 +71,7 @@
>> 
>> enum brcm_ahci_quicks {
>>        BRCM_AHCI_QUICK_NONCQ           = BIT(0),
>> +       BRCM_AHCI_QUICK_NOPHY           = BIT(1),
>> };
>> 
>> struct brcm_ahci_priv {
>> @@ -119,6 +120,9 @@ static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
>>        void __iomem *p;
>>        u32 reg;
>> 
>> +       if (priv->quicks & BRCM_AHCI_QUICK_NOPHY)
>> +               return;
>> +
>>        /* clear PHY_DEFAULT_POWER_STATE */
>>        p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
>>        reg = brcm_sata_readreg(p);
>> @@ -148,6 +152,9 @@ static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
>>        void __iomem *p;
>>        u32 reg;
>> 
>> +       if (priv->quicks & BRCM_AHCI_QUICK_NOPHY)
>> +               return;
>> +
>>        /* power-off the PHY digital logic */
>>        p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
>>        reg = brcm_sata_readreg(p);
>> @@ -297,6 +304,9 @@ static int brcm_ahci_probe(struct platform_device *pdev)
>>        if (of_property_read_bool(dev->of_node, "brcm,broken-ncq"))
>>                priv->quicks |= BRCM_AHCI_QUICK_NONCQ;
>> 
>> +       if (of_property_read_bool(dev->of_node, "brcm,broken-phy"))
>> +               priv->quicks |= BRCM_AHCI_QUICK_NOPHY;
>> +
>>        brcm_sata_init(priv);
>>        brcm_sata_quick(pdev, priv);
>> 
>> --
>> 2.6.2
>> 

Re: [v2 01/10] ata: ahci_brcmstb: add quick for broken ncq

[Florian Fainelli]

On 26/10/15 23:48, Jaedon Shin wrote:
> Add quick for bronken ncq. The chipsets (eg. BCM7439A0, BCM7445A0 and
> BCM7445B0) need a workaround disabling NCQ. and it may need the
> MIPS-based set-top box platforms.

None of these chips are production chips, so at this point, disabling
NCQ should be done based on the compatible string we probed the driver
with, not using a specific property.

There are more comments below

> 
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
> ---

[snip]

>  
> +static void brcm_sata_quick(struct platform_device *pdev,
> +			    struct brcm_ahci_priv *priv)
> +{
> +	void __iomem *ahci;
> +	struct resource *res;
> +	u32 reg;
> +
> +	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ahci");
> +	ahci = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(ahci))
> +		return;
> +
> +	if (priv->quicks & BRCM_AHCI_QUICK_NONCQ) {
> +		reg  = readl(priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
> +		reg |= OVERRIDE_HWINIT;
> +		writel(reg, priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
> +
> +		/* Clear out the NCQ bit so the AHCI driver will not issue
> +		 * FPDMA/NCQ commands.
> +		 */
> +		reg = readl(ahci + HOST_CAP);
> +		reg &= ~HOST_CAP_NCQ;
> +		writel(reg, ahci + HOST_CAP);
> +
> +		reg = readl(priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
> +		reg &= ~OVERRIDE_HWINIT;
> +		writel(reg, priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
> +	}

In the original BSP, the NCQ disabling occurs prior to initializing the
SATA controller endianess. We would want to keep doing that in the same
order, and use brcm_sata_readreg() and brcm_sata_writereg() which take
care of doing these accesses in the native endianess of the system.

Reference is here:

https://github.com/Broadcom/stblinux-3.3/blob/master/linux/drivers/brcmstb/bchip.c#L254

> +
> +	devm_iounmap(&pdev->dev, ahci);
> +	devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
> +}
> +
>  #ifdef CONFIG_PM_SLEEP
>  static int brcm_ahci_suspend(struct device *dev)
>  {
> @@ -256,7 +294,11 @@ static int brcm_ahci_probe(struct platform_device *pdev)
>  	if (IS_ERR(priv->top_ctrl))
>  		return PTR_ERR(priv->top_ctrl);
>  
> +	if (of_property_read_bool(dev->of_node, "brcm,broken-ncq"))
> +		priv->quicks |= BRCM_AHCI_QUICK_NONCQ;
> +
>  	brcm_sata_init(priv);
> +	brcm_sata_quick(pdev, priv);
Florian

Re: [v2 03/10] ata: ahci_brcmstb: add quick for broken phy

[Florian Fainelli]

On 26/10/15 23:48, Jaedon Shin wrote:
> Add quick for broken phy. The ARM-based 28nm chipsets have four phy
> interface control registers and each port has two registers. But, The
> MIPS-based 40nm chipsets have three. and there are no information and
> documentation. The legacy version of broadcom's strict-ahci based
> initial code did not control these registers.

Qualifying this of a broken PHY is a misnomer, this is more about the
fact that the PHY control registers have a different layout and behavior
on 40nm vs 28nm chips, but more importantly, do not require any kind of
configuration.

> 
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
> ---
>  Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt |  1 +
>  drivers/ata/ahci_brcmstb.c                                  | 10 ++++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt b/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
> index 488a383ce202..0f0925d58188 100644
> --- a/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
> +++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
> @@ -12,6 +12,7 @@ Required properties:
>  
>  Optional properties:
>  - brcm,broken-ncq    : if present, NCQ is unusable
> +- brcm,broken-phy    : if present, to control phy interface is unusable

Same comment as in patch 1, this is something that can be known based on
the compatible string, and the name of the property is misleading.

>  
>  Also see ahci-platform.txt.
>  
> diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
> index e53962cb48ee..c61303f7c7dc 100644
> --- a/drivers/ata/ahci_brcmstb.c
> +++ b/drivers/ata/ahci_brcmstb.c
> @@ -71,6 +71,7 @@
>  
>  enum brcm_ahci_quicks {
>  	BRCM_AHCI_QUICK_NONCQ		= BIT(0),
> +	BRCM_AHCI_QUICK_NOPHY		= BIT(1),

I would use something like BRCM_AHCI_SKIP_PHY_ENABLE or something like
that to illustrate what this really is about.

>  };
>  
>  struct brcm_ahci_priv {
> @@ -119,6 +120,9 @@ static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
>  	void __iomem *p;
>  	u32 reg;
>  
> +	if (priv->quicks & BRCM_AHCI_QUICK_NOPHY)
> +		return;
> +
>  	/* clear PHY_DEFAULT_POWER_STATE */
>  	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
>  	reg = brcm_sata_readreg(p);
> @@ -148,6 +152,9 @@ static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
>  	void __iomem *p;
>  	u32 reg;
>  
> +	if (priv->quicks & BRCM_AHCI_QUICK_NOPHY)
> +		return;
> +
>  	/* power-off the PHY digital logic */
>  	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
>  	reg = brcm_sata_readreg(p);
> @@ -297,6 +304,9 @@ static int brcm_ahci_probe(struct platform_device *pdev)
>  	if (of_property_read_bool(dev->of_node, "brcm,broken-ncq"))
>  		priv->quicks |= BRCM_AHCI_QUICK_NONCQ;
>  
> +	if (of_property_read_bool(dev->of_node, "brcm,broken-phy"))
> +		priv->quicks |= BRCM_AHCI_QUICK_NOPHY;
> +
>  	brcm_sata_init(priv);
>  	brcm_sata_quick(pdev, priv);
>  
> 


-- 
Florian

Re: [v2 02/10] ata: ahci_brcmstb: add support MIPS-based platforms

[Brian Norris]

On Tue, Oct 27, 2015 at 03:48:03PM +0900, Jaedon Shin wrote:
> The BCM7xxx ARM-based and MIPS-based platforms share a similar hardware
> block for AHCI SATA3.
> 
> The BCM7425 is flagship chipset of 40nm class. Other MIPS-based 40nm
> chipsets has same hardware block. so the compatible string may be use
> brcm,bcm7425-ahci.
> 
> Signed-off-by: Jaedon Shin <jaedon.shin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt | 4 ++--
>  drivers/ata/Kconfig                                         | 2 +-
>  drivers/ata/ahci_brcmstb.c                                  | 1 +
>  3 files changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt b/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
> index 4650c0aff6b3..488a383ce202 100644
> --- a/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
> +++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcmstb.txt
> @@ -4,8 +4,8 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
>  Each SATA controller should have its own node.
>  
>  Required properties:
> -- compatible         : compatible list, may contain "brcm,bcm7445-ahci" and/or
> -                       "brcm,sata3-ahci"
> +- compatible         : compatible list, may contain "brcm,bcm7445-ahci" or
> +                       "brcm,bcm7425-ahci" or "brcm,sata3-ahci"

If you're going to spin this series anyway, you might as well turn this
into a list, with one compatible string per line. That way it's easier
to expand if needed.

Brian

>  - reg                : register mappings for AHCI and SATA_TOP_CTRL
>  - reg-names          : "ahci" and "top-ctrl"
>  - interrupts         : interrupt mapping for SATA IRQ
> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
> index 15e40ee62a94..8f535a88a0c7 100644
> --- a/drivers/ata/Kconfig
> +++ b/drivers/ata/Kconfig
> @@ -100,7 +100,7 @@ config SATA_AHCI_PLATFORM
>  
>  config AHCI_BRCMSTB
>  	tristate "Broadcom STB AHCI SATA support"
> -	depends on ARCH_BRCMSTB
> +	depends on ARCH_BRCMSTB || BMIPS_GENERIC
>  	help
>  	  This option enables support for the AHCI SATA3 controller found on
>  	  STB SoC's.
> diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
> index a2df76698adb..e53962cb48ee 100644
> --- a/drivers/ata/ahci_brcmstb.c
> +++ b/drivers/ata/ahci_brcmstb.c
> @@ -343,6 +343,7 @@ static int brcm_ahci_remove(struct platform_device *pdev)
>  
>  static const struct of_device_id ahci_of_match[] = {
>  	{.compatible = "brcm,bcm7445-ahci"},
> +	{.compatible = "brcm,bcm7425-ahci"},
>  	{},
>  };
>  MODULE_DEVICE_TABLE(of, ahci_of_match);
> -- 
> 2.6.2
> 
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Re: [v2 07/10] phy: phy_brcmstb_sata: add support MIPS-based platforms

[Rob Herring]

On Tue, Oct 27, 2015 at 1:48 AM, Jaedon Shin <jaedon.shin@gmail.com> wrote:
> The BCM7xxx ARM-based and MIPS-based platforms share a similar hardware
> block for AHCI SATA3.
>
> The BCM7425 is flagship chipset of 40nm class. Other MIPS-based 40nm
> chipsets has same hardware block. so the compatible string may be use
> brcm,bcm7425-sata-phy.
>
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>

Acked-by: Rob Herring <robh@kernel.org>

> ---
>  .../bindings/phy/brcm,brcmstb-sata-phy.txt         |  1 +
>  drivers/phy/Kconfig                                |  4 ++--
>  drivers/phy/phy-brcmstb-sata.c                     | 24 ++++++++++++++++------
>  3 files changed, 21 insertions(+), 8 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt b/Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt
> index 7f81ef90146a..c4b31075ffef 100644
> --- a/Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt
> @@ -3,6 +3,7 @@
>  Required properties:
>  - compatible: should be one or more of
>       "brcm,bcm7445-sata-phy"
> +     "brcm,bcm7425-sata-phy"
>       "brcm,phy-sata3"
>  - address-cells: should be 1
>  - size-cells: should be 0
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 47da573d0bab..c83e48661fd7 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -364,11 +364,11 @@ config PHY_TUSB1210
>
>  config PHY_BRCMSTB_SATA
>         tristate "Broadcom STB SATA PHY driver"
> -       depends on ARCH_BRCMSTB
> +       depends on ARCH_BRCMSTB || BMIPS_GENERIC
>         depends on OF
>         select GENERIC_PHY
>         help
> -         Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
> +         Enable this to support the SATA3 PHY on 28nm or 40nm Broadcom STB SoCs.
>           Likely useful only with CONFIG_SATA_BRCMSTB enabled.
>
>  endmenu
> diff --git a/drivers/phy/phy-brcmstb-sata.c b/drivers/phy/phy-brcmstb-sata.c
> index 5de394f589c8..c8243581f196 100644
> --- a/drivers/phy/phy-brcmstb-sata.c
> +++ b/drivers/phy/phy-brcmstb-sata.c
> @@ -32,8 +32,14 @@
>  /* Register offset between PHYs in PCB space */
>  #define SATA_MDIO_REG_28NM_SPACE_SIZE                  0x1000
>
> +/* The older SATA PHY registers duplicated per port registers within the map,
> + * rather than having a separate map per port.
> + */
> +#define SATA_MDIO_REG_40NM_SPACE_SIZE                  0x10
> +
>  enum brcm_sata_phy_version {
>         BRCM_SATA_PHY_28NM,
> +       BRCM_SATA_PHY_40NM,
>  };
>
>  struct brcm_sata_port {
> @@ -51,7 +57,7 @@ struct brcm_sata_phy {
>         struct brcm_sata_port phys[MAX_PORTS];
>  };
>
> -enum sata_mdio_phy_regs_28nm {
> +enum sata_mdio_phy_regs {
>         PLL_REG_BANK_0                          = 0x50,
>         PLL_REG_BANK_0_PLLCONTROL_0             = 0x81,
>
> @@ -69,10 +75,14 @@ enum sata_mdio_phy_regs_28nm {
>  static inline void __iomem *brcm_sata_phy_base(struct brcm_sata_port *port)
>  {
>         struct brcm_sata_phy *priv = port->phy_priv;
> -       u32 offset;
> +       u32 offset = 0;
>
>         if (priv->version == BRCM_SATA_PHY_28NM)
>                 offset = SATA_MDIO_REG_28NM_SPACE_SIZE;
> +       else if (priv->version == BRCM_SATA_PHY_40NM)
> +               offset = SATA_MDIO_REG_40NM_SPACE_SIZE;
> +       else
> +               dev_err(priv->dev, "should not happen\n");
>
>         return priv->phy_base + (port->portnum * offset);
>  }
> @@ -93,7 +103,7 @@ static void brcm_sata_mdio_wr(void __iomem *addr, u32 bank, u32 ofs,
>  #define FMAX_VAL_DEFAULT       0x3df
>  #define FMAX_VAL_SSC           0x83
>
> -static void brcm_sata_cfg_ssc_28nm(struct brcm_sata_port *port)
> +static void brcm_sata_cfg_ssc(struct brcm_sata_port *port)
>  {
>         void __iomem *base = brcm_sata_phy_base(port);
>         struct brcm_sata_phy *priv = port->phy_priv;
> @@ -124,12 +134,12 @@ static int brcm_sata_phy_init(struct phy *phy)
>  {
>         struct brcm_sata_port *port = phy_get_drvdata(phy);
>
> -       brcm_sata_cfg_ssc_28nm(port);
> +       brcm_sata_cfg_ssc(port);
>
>         return 0;
>  }
>
> -static const struct phy_ops phy_ops_28nm = {
> +static const struct phy_ops phy_ops = {
>         .init           = brcm_sata_phy_init,
>         .owner          = THIS_MODULE,
>  };
> @@ -137,6 +147,8 @@ static const struct phy_ops phy_ops_28nm = {
>  static const struct of_device_id brcm_sata_phy_of_match[] = {
>         { .compatible   = "brcm,bcm7445-sata-phy",
>           .data = (void *)BRCM_SATA_PHY_28NM },
> +       { .compatible   = "brcm,bcm7425-sata-phy",
> +         .data = (void *)BRCM_SATA_PHY_40NM },
>         {},
>  };
>  MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
> @@ -193,7 +205,7 @@ static int brcm_sata_phy_probe(struct platform_device *pdev)
>                 port = &priv->phys[id];
>                 port->portnum = id;
>                 port->phy_priv = priv;
> -               port->phy = devm_phy_create(dev, child, &phy_ops_28nm);
> +               port->phy = devm_phy_create(dev, child, &phy_ops);
>                 port->ssc_en = of_property_read_bool(child, "brcm,enable-ssc");
>                 if (IS_ERR(port->phy)) {
>                         dev_err(dev, "failed to create PHY\n");
> --
> 2.6.2
>

Re: [v2 06/10] phy: phy_brcmstb_sata: add data for phy version

[Arnd Bergmann]

On Tuesday 27 October 2015 15:48:07 Jaedon Shin wrote:
> 
>  static const struct of_device_id brcm_sata_phy_of_match[] = {
> -       { .compatible   = "brcm,bcm7445-sata-phy" },
> +       { .compatible   = "brcm,bcm7445-sata-phy",
> +         .data = (void *)BRCM_SATA_PHY_28NM },
>         {},
>  };
>  MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
> @@ -135,6 +145,7 @@ static int brcm_sata_phy_probe(struct platform_device *pdev)
>  {
>         struct device *dev = &pdev->dev;
>         struct device_node *dn = dev->of_node, *child;
> +       const struct of_device_id *of_id;
>         struct brcm_sata_phy *priv;
>         struct resource *res;
>         struct phy_provider *provider;
> @@ -154,6 +165,12 @@ static int brcm_sata_phy_probe(struct platform_device *pdev)
>         if (IS_ERR(priv->phy_base))
>                 return PTR_ERR(priv->phy_base);
>  
> +       of_id = of_match_node(brcm_sata_phy_of_match, dn);
> +       if (of_id)
> +               priv->version = (enum brcm_sata_phy_version)of_id->data;
> +       else
> +               priv->version = BRCM_SATA_PHY_28NM;
> +
> 

As you don't actually use that variable except to set the 'offset' for
phy_base, it would be nicer to use a structure that you can point to:

struct brcm_sata_phy_data {
	unsigned long offset;
};

const struct brcm_sata_phy_data brcm_sata_phy_28nm = {
	.offset = SATA_MDIO_REG_28NM_SPACE_SIZE,
};

static const struct of_device_id brcm_sata_phy_of_match[] = {
	{ .compatible   = "brcm,bcm7445-sata-phy", .data = &brcm_sata_phy_28nm },
	{},
};

	Arnd