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From: Icenowy Zheng <uwu@icenowy.me>
To: Jisheng Zhang <jszhang@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, Guo Ren <guoren@kernel.org>
Subject: Re: [PATCH 1/5] irqchip/sifive-plic: Support T-HEAD's C910 PLIC
Date: Mon, 08 May 2023 11:14:32 +0800	[thread overview]
Message-ID: <56489d3f1b23a90baf3ef024da09b4c8c02a2204.camel@icenowy.me> (raw)
In-Reply-To: <20230507182304.2934-2-jszhang@kernel.org>

在 2023-05-08星期一的 02:23 +0800,Jisheng Zhang写道:
> The T-HEAD's C910 PLIC still needs the delegation bit settingto allow
> access from S-mode, but it doesn't need the edge quirk.

No, the PLIC controller seems to be the same between C906 and C910,
which has level/edge selectable via external signal.

See openc906 and openc910 repositories, especially the documents with
it: 玄铁C9{06,10}集成手册.pdf .

In addition, such problem won't arise when the system uses only level-
triggered interrupts.

> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml      | 4
> ++++
>  drivers/irqchip/irq-sifive-plic.c                             | 1 +
>  2 files changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-
> controller/sifive,plic-1.0.0.yaml
> b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-
> 1.0.0.yaml
> index f75736a061af..64b43a3c3748 100644
> --- a/Documentation/devicetree/bindings/interrupt-
> controller/sifive,plic-1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-
> controller/sifive,plic-1.0.0.yaml
> @@ -62,6 +62,10 @@ properties:
>                - starfive,jh7110-plic
>                - canaan,k210-plic
>            - const: sifive,plic-1.0.0
> +      - items:
> +          - enum:
> +              - thead,light-plic
> +          - const: thead,c910-plic
>        - items:
>            - enum:
>                - allwinner,sun20i-d1-plic
> diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-
> sifive-plic.c
> index e1484905b7bd..71afa2a584d9 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -569,6 +569,7 @@ static int __init plic_init(struct device_node
> *node,
>  }
>  
>  IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
> +IRQCHIP_DECLARE(thead_c910_plic, "thead,c910-plic", plic_init);
>  IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for
> legacy systems */
>  
>  static int __init plic_edge_init(struct device_node *node,


  parent reply	other threads:[~2023-05-08  3:17 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-07 18:22 [PATCH 0/5] Add Sipeed Lichee Pi 4A RISC-V board support Jisheng Zhang
2023-05-07 18:23 ` [PATCH 1/5] irqchip/sifive-plic: Support T-HEAD's C910 PLIC Jisheng Zhang
2023-05-07 21:18   ` Conor Dooley
2023-05-08  3:14   ` Icenowy Zheng [this message]
2023-05-08  6:52   ` Guo Ren
2023-05-08  7:07     ` Conor Dooley
2023-05-08 16:09     ` Jisheng Zhang
2023-05-08  9:17   ` Krzysztof Kozlowski
2023-05-07 18:23 ` [PATCH 2/5] riscv: Add the T-HEAD SoC family Kconfig option Jisheng Zhang
2023-05-07 21:22   ` Conor Dooley
2023-05-08  6:42     ` Guo Ren
2023-05-08  6:52       ` Conor Dooley
2023-05-08  6:58         ` Guo Ren
2023-05-08  7:04           ` Conor Dooley
2023-05-07 18:23 ` [PATCH 3/5] riscv: dts: add initial T-HEAD light SoC device tree Jisheng Zhang
2023-05-07 21:35   ` Conor Dooley
2023-05-08  3:32     ` Icenowy Zheng
2023-05-08  7:01       ` Conor Dooley
2023-05-08  8:23       ` Heiko Stübner
2023-05-08  8:35         ` Conor Dooley
2023-05-08 15:56           ` Heiko Stübner
2023-05-08 16:26     ` Jisheng Zhang
2023-05-08 16:44       ` Conor Dooley
2023-05-08 17:09         ` Heiko Stübner
2023-05-21 15:37         ` Guo Ren
2023-05-21 17:08           ` Conor Dooley
2023-05-22  1:36             ` Guo Ren
2023-05-08  9:20   ` Krzysztof Kozlowski
2023-05-07 18:23 ` [PATCH 4/5] riscv: dts: thead: add sipeed Lichee Pi 4A board " Jisheng Zhang
2023-05-07 21:27   ` Conor Dooley
2023-05-08  6:44   ` Guo Ren
2023-05-07 18:23 ` [PATCH 5/5] MAINTAINERS: add entry for T-HEAD RISC-V SoC Jisheng Zhang
2023-05-07 21:21   ` Conor Dooley
2023-05-08 16:17     ` Jisheng Zhang
2023-05-08 17:23       ` Conor Dooley
2023-05-08  6:22   ` Guo Ren
2023-05-08  6:16 ` [PATCH 0/5] Add Sipeed Lichee Pi 4A RISC-V board support Guo Ren

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