From: Marc Zyngier <marc.zyngier@arm.com>
To: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>,
robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
michals@xilinx.com, sorenb@xilinx.com, bhelgaas@google.com,
arnd@arndb.de, tinamdar@apm.com, treding@nvidia.com,
rjui@broadcom.com, Minghuan.Lian@freescale.com,
m-karicheri2@ti.com, hauke@hauke-m.de, dhdang@apm.com,
sbranden@broadcom.com
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
Bharat Kumar Gogada <bharatku@xilinx.com>,
Ravi Kiran Gummaluri <rgummal@xilinx.com>
Subject: Re: [PATCH v8] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller
Date: Mon, 16 Nov 2015 15:14:33 +0000 [thread overview]
Message-ID: <5649F2D9.7070902@arm.com> (raw)
In-Reply-To: <1447223619-30945-1-git-send-email-bharatku@xilinx.com>
On 11/11/15 06:33, Bharat Kumar Gogada wrote:
> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
>
> Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
> ---
> Added logic to allocate contiguous hwirq in nwl_irq_domain_alloc function.
> Moved MSI functionality to separate functions.
> Changed error return values.
> ---
> .../devicetree/bindings/pci/xilinx-nwl-pcie.txt | 68 ++
> drivers/pci/host/Kconfig | 16 +-
> drivers/pci/host/Makefile | 1 +
> drivers/pci/host/pcie-xilinx-nwl.c | 1062 ++++++++++++++++++++
> 4 files changed, 1144 insertions(+), 3 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
> create mode 100644 drivers/pci/host/pcie-xilinx-nwl.c
>
[...]
> +static int nwl_pcie_enable_msi(struct nwl_pcie *pcie, struct pci_bus *bus)
> +{
> + struct platform_device *pdev = to_platform_device(pcie->dev);
> + struct nwl_msi *msi = &pcie->msi;
> + unsigned long base;
> + int ret;
> +
> + mutex_init(&msi->lock);
> +
> + /* Check for msii_present bit */
> + ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
> + if (!ret) {
> + dev_err(pcie->dev, "MSI not present\n");
> + ret = -EIO;
> + goto err;
> + }
> +
> + /* Enable MSII */
> + nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
> + MSII_ENABLE, I_MSII_CONTROL);
> +
> + /* Enable MSII status */
> + nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
> + MSII_STATUS_ENABLE, I_MSII_CONTROL);
> +
> + /* setup AFI/FPCI range */
> + msi->pages = __get_free_pages(GFP_KERNEL, 0);
> + base = virt_to_phys((void *)msi->pages);
> + nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
> + nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
BTW, you still haven't answered my question as to why you need to waste
a page of memory here, and why putting a device address doesn't work.
As this is (to the best of my knowledge) the only driver doing so, I'd
really like you to explain the rational behind this.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2015-11-16 15:14 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-11 6:33 [PATCH v8] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller Bharat Kumar Gogada
2015-11-11 17:37 ` Marc Zyngier
2015-11-17 5:06 ` Bharat Kumar Gogada
[not found] ` <1447223619-30945-1-git-send-email-bharatku-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
2015-11-11 20:29 ` Rob Herring
2015-11-16 10:27 ` Bharat Kumar Gogada
2015-11-16 22:16 ` Ray Jui
2015-11-17 5:01 ` Bharat Kumar Gogada
2015-11-16 15:14 ` Marc Zyngier [this message]
2015-11-16 22:01 ` Ray Jui
2015-11-17 4:59 ` Bharat Kumar Gogada
2015-11-17 9:21 ` Marc Zyngier
[not found] ` <20151117092100.76babf7f-5wv7dgnIgG8@public.gmane.org>
2015-11-17 13:27 ` Bharat Kumar Gogada
2015-11-17 13:55 ` Marc Zyngier
2015-11-17 16:24 ` Ray Jui
2015-11-18 6:51 ` Bharat Kumar Gogada
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