From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Subject: Re: [PATCH 2/2] dt-bindings: phy: tegra-xusb-padctl: Add Tegra210 support Date: Mon, 16 Nov 2015 13:30:59 -0700 Message-ID: <564A3D03.70001@wwwdotorg.org> References: <1446657109-15568-1-git-send-email-thierry.reding@gmail.com> <1446657109-15568-3-git-send-email-thierry.reding@gmail.com> <563A71C7.9030002@wwwdotorg.org> <20151113163239.GB7219@ulmo> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Andrew Bresticker , Thierry Reding Cc: "linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Jon Hunter , Martyn Welch , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" List-Id: devicetree@vger.kernel.org On 11/13/2015 10:58 AM, Andrew Bresticker wrote: > On Fri, Nov 13, 2015 at 8:32 AM, Thierry Reding > wrote: >> On Wed, Nov 04, 2015 at 01:59:51PM -0700, Stephen Warren wrote: >>> On 11/04/2015 10:11 AM, Thierry Reding wrote: >>>> From: Thierry Reding >>>> >>>> Extend the binding to cover the set of feature found in Tegra210. >>> >>>> diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra-xusb-padctl.txt >>> >>>> +For Tegra210, the list of valid PHY nodes is given below: >>>> +- utmi: utmi-0, utmi-1, utmi-2, utmi-3 >>>> + - functions: "snps", "xusb", "uart" >>>> +- hsic: hsic-0, hsic-1 >>>> + - functions: "snps", "xusb" >>>> +- pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6 >>>> + - functions: "pcie-x1", "usb3-ss", "pcie-x4" >>>> +- sata: sata-0 >>>> + - functions: "usb3-ss", "sata" >>> >>> usb2-bias also needs to be present. >> >> I'm not sure about this. All of the driver code that I've looked deals >> with the usb2-bias pad internally. As far as I can tell, this pad needs >> to be configured to whatever any of the other pads is configured for. I >> think that means if any of the UTMI pads is configured for XUSB then the >> usb2-bias pad must also be configured for XUSB. Which would also imply >> that if one of the UTMI pads is configured for XUSB, all of them must be >> configured for XUSB. > > I was told by hardware engineers at NVIDIA that (at least on > Tegra124/Tegra132) the usb2-bias pad must be configured in the > XUSB_PADCTL register space if UTMI pad 0 is muxed to XUSB. If UTMI > pad 0 is muxed to SNPS, then the usb2-bias pad is configured in the > USB register space (base 0x7d000000). You may want to follow up > internally to confirm this. If it's true, that could make things here > a bit nastier, especially if we want to support configurations where > some pads are muxed to XUSB while others are muxed to SNPS. Hmm. I've certainly successfully tested a configuration where UTMI pad 0 was handled by the SNPS controller and other pads by the XUSB controller *and* where I set the usb2-bias "pad"'s muxing and configuration via the XUSB PADCTL module. In that case, I /had/ to configure usb2-bias via XUSB PADCTL or the other XUSB pads didn't work. However, perhaps that was because the XUSB controller driver probed before the SNPS driver; perhaps if they'd probed the other way around and the SNPS driver configured the bias pad, then everything would have worked without configuring the bias pad via XUSB PADCTL. I suppose I'll have to start another internal thread to get the full details, and differentiate between "recommended" and "supported" and "must" vs. "can"/"should".