From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7BF6C3DA78 for ; Tue, 17 Jan 2023 05:29:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235063AbjAQF3E (ORCPT ); Tue, 17 Jan 2023 00:29:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235177AbjAQF3C (ORCPT ); Tue, 17 Jan 2023 00:29:02 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB039233D2; Mon, 16 Jan 2023 21:29:01 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 30H5Si1c040614; Mon, 16 Jan 2023 23:28:44 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1673933324; bh=m6wYalfTMNF3q/k6hE7vf1IFXNcR4EAEmeW5euyuYvM=; h=Date:CC:Subject:To:References:From:In-Reply-To; b=RKXAy2bbS6FTxJddeKuTqFdawGMytEIgbEVb57Z7Kz5Yz7TMI0HwTKNxkM2ZR12e5 b96HQIyDjXWFuy2la5tSTy/6q/3NPo8c1y9vYa2xxLk9BuWaqJxL2jCKeX5mG5pl2d edebBk92rm2y4rAJ4HNui10ccs54MtlZ64COODcQ= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 30H5Siwr124918 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 16 Jan 2023 23:28:44 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Mon, 16 Jan 2023 23:28:44 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Mon, 16 Jan 2023 23:28:44 -0600 Received: from [172.24.145.61] (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 30H5Sdj1093170; Mon, 16 Jan 2023 23:28:39 -0600 Message-ID: <566700c6-df9b-739b-81ff-8745eea10ff3@ti.com> Date: Tue, 17 Jan 2023 10:58:38 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 CC: , , , , , , , Roger Quadros , , , , , , , , , Subject: Re: [PATCH net-next 5/5] arm64: dts: ti: k3-am625-sk: Add cpsw3g cpts PPS support Content-Language: en-US To: Vignesh Raghavendra References: <20230111114429.1297557-1-s-vadapalli@ti.com> <20230111114429.1297557-6-s-vadapalli@ti.com> <6ae650c9-d68d-d2fc-8319-b7784cd2a749@kernel.org> <2007adb5-0980-eee3-8d2f-e30183cf408e@kernel.org> <4d7ac24a-0a35-323c-045c-cc5b3d3c715a@ti.com> From: Siddharth Vadapalli In-Reply-To: <4d7ac24a-0a35-323c-045c-cc5b3d3c715a@ti.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Vignesh, On 16/01/23 22:00, Vignesh Raghavendra wrote: > > > On 16/01/23 9:35 pm, Roger Quadros wrote: >>>>> diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts >>>>> index 4f179b146cab..962a922cc94b 100644 >>>>> --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts >>>>> +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts >>>>> @@ -366,6 +366,10 @@ &cpsw3g { >>>>> pinctrl-names = "default"; >>>>> pinctrl-0 = <&main_rgmii1_pins_default >>>>> &main_rgmii2_pins_default>; >>>>> + >>>>> + cpts@3d000 { >>>>> + ti,pps = <2 1>; >>>>> + }; >>>>> }; >>>>> >>>>> &cpsw_port1 { >>>>> @@ -464,3 +468,19 @@ partition@3fc0000 { >>>>> }; >>>>> }; >>>>> }; >>>>> + >>>>> +#define TS_OFFSET(pa, val) (0x4+(pa)*4) (0x10000 | val) >>>> Should this go in ./include/dt-bindings/pinctrl/k3.h ? >>>> That way every board DT file doesn't have to define it. >>>> >>>> The name should be made more platform specific. >>>> e.g. K3_TS_OFFSET if it is the same for all K3 platforms. >>>> If not then please add Platform name instead of K3. >>> The offsets are board specific. If it is acceptable, I will add board specific >>> macro for the TS_OFFSET definition in the ./include/dt-bindings/pinctrl/k3.h >>> file. Please let me know. >> If it is board specific then it should remain in the board file. > > > The values you pass to macro maybe board specific. But the macro > definition itself same for a given SoC right? Also, is its same across > K3 family ? > > Please use SoC specific prefix like AM62X_TS_OFFSET() or K3_TS_OFFSET() > accordingly. For certain SoCs including AM62X, the macro is: #define TS_OFFSET(pa, val) (0x4+(pa)*4) (0x10000 | val) while for other SoCs (refer [0]), the macro is: #define TS_OFFSET(pa, val) (0x4+(pa)*4) (0x80000000 | val) Therefore, I will use SoC specific prefix in the macro. Please let me know if the SoC specific macro can be added to the ./include/dt-bindings/pinctrl/k3.h file for each SoC. If not, I will add the SoC specific macro in the board file itself. [0] https://lwn.net/Articles/819313/ Regards, Siddharth.