From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stanimir Varbanov Subject: Re: [PATCH 3/4] dmaengine: qcom_bam_dma: use correct pipe FIFO size Date: Thu, 10 Dec 2015 15:18:33 +0200 Message-ID: <56697BA9.5050805@linaro.org> References: <1448961299-15161-1-git-send-email-stanimir.varbanov@linaro.org> <1448961299-15161-4-git-send-email-stanimir.varbanov@linaro.org> <20151201172307.GA26687@Agamemnon.attlocal.net> <565F1FDB.4020106@linaro.org> <20151202172255.GA9599@Agamemnon.attlocal.net> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20151202172255.GA9599@Agamemnon.attlocal.net> Sender: linux-arm-msm-owner@vger.kernel.org To: Andy Gross , Stanimir Varbanov Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, dmaengine@vger.kernel.org, Vinod Koul , Rob Herring , Rob Herring , Mark Rutland , Pawel Moll , Ian Campbell , Archit Taneja List-Id: devicetree@vger.kernel.org On 12/02/2015 07:22 PM, Andy Gross wrote: > On Wed, Dec 02, 2015 at 06:44:11PM +0200, Stanimir Varbanov wrote: >> On 12/01/2015 07:23 PM, Andy Gross wrote: >>> On Tue, Dec 01, 2015 at 11:14:58AM +0200, Stanimir Varbanov wrote: >>>> The pipe fifo size register must instruct the bam hw >>>> how many hw descriptors can be pushed to fifo. Currently >>>> we isntruct the hw with 32KBytes but wrap the tail in >>>> bam_start_dma in BAM_P_EVNT_REG on 4095 i.e. 32760. This >>>> leads to stalled transactions when the tail wraps. >>>> >>>> Fix this by use the correct fifo size in BAM_P_FIFO_SIZES >>>> register i.e. 32K - 8. >>>> >>>> Signed-off-by: Stanimir Varbanov >>>> --- >>>> drivers/dma/qcom_bam_dma.c | 2 +- >>>> 1 file changed, 1 insertion(+), 1 deletion(-) >>>> >>>> diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c >>>> index 0f06f3b7a72b..6d290de9ab2b 100644 >>>> --- a/drivers/dma/qcom_bam_dma.c >>>> +++ b/drivers/dma/qcom_bam_dma.c >>>> @@ -458,7 +458,7 @@ static void bam_chan_init_hw(struct bam_chan *bchan, >>>> */ >>>> writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)), >>>> bam_addr(bdev, bchan->id, BAM_P_DESC_FIFO_ADDR)); >>>> - writel_relaxed(BAM_DESC_FIFO_SIZE, >>>> + writel_relaxed(BAM_MAX_DATA_SIZE, >>>> bam_addr(bdev, bchan->id, BAM_P_FIFO_SIZES)); >>> >>> This is just using the #define. That is ok, but if you use this instead of the >>> BAM_P_FIFO_SIZES then you need to fix your comment. Or actually use the >>> register value.... otherwise looks fine. >> >> I did not follow your comment, but the intension of the patch is to set >> the proper FIFO size in BAM_P_FIFO_SIZES register, i.e. 32K - 8. > > Sorry, I mixed up the usage and was thinking there was something you read out > that told you the size. That's not how it works, unfortunately. The > MAX_DATA_SIZE is fine, but the name is a little misleading. Perhaps just > BAM_FIFO_SIZE? OK I can rename BAM_MAX_DATA_SIZE to BAM_FIFO_SIZE, and use it when setting BAM_P_FIFO_SIZES register. Is that fine to you? -- regards, Stan