From: Arnd Bergmann <arnd@arndb.de>
To: Marc Zyngier <marc.zyngier@arm.com>
Cc: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"pawel.moll@arm.com" <pawel.moll@arm.com>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"ijc+devicetree@hellion.org.uk" <ijc+devicetree@hellion.org.uk>,
"galak@codeaurora.org" <galak@codeaurora.org>,
Michal Simek <michals@xilinx.com>,
Soren Brinkmann <sorenb@xilinx.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"tinamdar@apm.com" <tinamdar@apm.com>,
"treding@nvidia.com" <treding@nvidia.com>,
"rjui@broadcom.com" <rjui@broadcom.com>,
"Minghuan.Lian@freescale.com" <Minghuan.Lian@freescale.com>,
"m-karicheri2@ti.com" <m-karicheri2@ti.com>,
"hauke@hauke-m.de" <hauke@hauke-m.de>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Ravikiran
Subject: Re: [PATCH v3] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller
Date: Fri, 09 Oct 2015 10:18:21 +0200 [thread overview]
Message-ID: <5676910.8cxuyuvhpA@wuerfel> (raw)
In-Reply-To: <56177669.2000302@arm.com>
On Friday 09 October 2015 09:10:17 Marc Zyngier wrote:
> > Please let me know whether we require a separate msi file as
> > suggested in your previous comments to separate MSI controller and
> > PCIE controller in two files, if we don't have separate node. If we
> > do not need a separate node do we need to embed MSI controller child
> > node in PCIe controller node itself, and what properties does this
> > child node will require other than 'interrupts'.
>
> If you want to keep them in the same file, please at least have two
> separate patches. These are two different functions, and they should be
> reviewed separately.
>
> It will help everyone to understand your code, and speed up the
> reviewing process.
Agreed. Also, the part we really want is to have the PCI controller
code decoupled enough from the MSI code that it will not require
further changes once Xilinx comes out with a chip that has a modern
GIC in it and the same PCIe host.
Arnd
next prev parent reply other threads:[~2015-10-09 8:18 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-06 15:44 [PATCH v3] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller Bharat Kumar Gogada
[not found] ` <1444146289-28940-1-git-send-email-bharatku-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
2015-10-06 16:13 ` Marc Zyngier
2015-10-06 16:27 ` Bharat Kumar Gogada
2015-10-06 16:41 ` Marc Zyngier
2015-10-09 2:53 ` Bharat Kumar Gogada
2015-10-09 5:11 ` Bharat Kumar Gogada
[not found] ` <8520D5D51A55D047800579B09414719801690CD0-4lKfpRxZ5enZMOc0yg5rMog+Gb3gawCHQz34XiSyOiE@public.gmane.org>
2015-10-09 8:10 ` Marc Zyngier
2015-10-09 8:18 ` Arnd Bergmann [this message]
2015-10-09 8:51 ` Bharat Kumar Gogada
[not found] ` <8520D5D51A55D047800579B09414719801690D3D-4lKfpRxZ5enZMOc0yg5rMog+Gb3gawCHQz34XiSyOiE@public.gmane.org>
2015-10-09 9:02 ` Marc Zyngier
2015-10-09 13:47 ` Bharat Kumar Gogada
2015-10-09 14:18 ` Marc Zyngier
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