From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Lezcano Subject: Re: [PATCH v4 1/4] RISC-V: Remove per cpu clocksource Date: Wed, 7 Aug 2019 10:04:01 +0200 Message-ID: <5687851a-2cdb-95a2-708f-30f6c14ba817@linaro.org> References: <20190803042723.7163-1-atish.patra@wdc.com> <20190803042723.7163-2-atish.patra@wdc.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Paul Walmsley , Atish Patra Cc: linux-kernel@vger.kernel.org, Alan Kao , Albert Ou , Anup Patel , devicetree@vger.kernel.org, Enrico Weigelt , Greg Kroah-Hartman , Johan Hovold , linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Rob Herring , Thomas Gleixner List-Id: devicetree@vger.kernel.org On 06/08/2019 23:37, Paul Walmsley wrote: > On Fri, 2 Aug 2019, Atish Patra wrote: > >> There is only one clocksource in RISC-V. The boot cpu initializes >> that clocksource. No need to keep a percpu data structure. >> >> Signed-off-by: Atish Patra > > Thanks, queued for v5.3-rc4. Please, in the future wait for my: Acked-by: Daniel Lezcano -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog