[PATCH v3 0/3] Enable X-Gene standby GPIO as interrupt controller

[PATCH v3 0/3] Enable X-Gene standby GPIO as interrupt controller

[Quan Nguyen]

V3 Changes:
        - Picking up from version 2 of "Y Vo <yvo@apm.com>"
        - Get HW resource information from DT
        - Avoid keeping parent IRQ controller
V2 Changes:
        - Support X-Gene standby GPIO as an interrupt controller.

Quan Nguyen (3):
  gpio: xgene: Enable X-Gene standby GPIO as interrupt controller
  Documentation: gpio: Update description for X-Gene standby GPIO
    controller DTS binding
  arm64: dts: Update X-Gene standby GPIO controller DTS entries

 .../devicetree/bindings/gpio/gpio-xgene-sb.txt     |  49 +++-
 arch/arm64/boot/dts/apm/apm-storm.dtsi             |   5 +-
 drivers/gpio/gpio-xgene-sb.c                       | 289 ++++++++++++++++++---
 3 files changed, 289 insertions(+), 54 deletions(-)

-- 
2.2.0

[PATCH v3 1/3] gpio: xgene: Enable X-Gene standby GPIO as interrupt controller

[Quan Nguyen]

Enable X-Gene standby GPIO controller as interrupt controller to provide
its own resources. This avoids ambiguity where GIC interrupt resource is
use as X-Gene standby GPIO interrupt resource in user driver.

Signed-off-by: Y Vo <yvo@apm.com>
Signed-off-by: Quan Nguyen <qnguyen@apm.com>
---
 drivers/gpio/gpio-xgene-sb.c | 289 ++++++++++++++++++++++++++++++++++++-------
 1 file changed, 247 insertions(+), 42 deletions(-)

diff --git a/drivers/gpio/gpio-xgene-sb.c b/drivers/gpio/gpio-xgene-sb.c
index d57068b..a38c90a 100644
--- a/drivers/gpio/gpio-xgene-sb.c
+++ b/drivers/gpio/gpio-xgene-sb.c
@@ -2,8 +2,9 @@
  * AppliedMicro X-Gene SoC GPIO-Standby Driver
  *
  * Copyright (c) 2014, Applied Micro Circuits Corporation
- * Author: 	Tin Huynh <tnhuynh@apm.com>.
- * 		Y Vo <yvo@apm.com>.
+ * Author:	Tin Huynh <tnhuynh@apm.com>.
+ *		Y Vo <yvo@apm.com>.
+ *		Quan Nguyen <qnguyen@apm.com>.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -22,6 +23,7 @@
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
+#include <linux/of_platform.h>
 #include <linux/of_gpio.h>
 #include <linux/gpio.h>
 #include <linux/gpio/driver.h>
@@ -30,16 +32,22 @@
 
 #include "gpiolib.h"
 
-#define XGENE_MAX_GPIO_DS		22
-#define XGENE_MAX_GPIO_DS_IRQ		6
+#define XGENE_MAX_NGPIO		22
+#define XGENE_MAX_NIRQ		6
+#define XGENE_IRQ_START_PIN	8
+#define SBGPIO_XGENE		((XGENE_IRQ_START_PIN << 16) | \
+				(XGENE_MAX_NIRQ << 8) | XGENE_MAX_NGPIO)
 
-#define GPIO_MASK(x)			(1U << ((x) % 32))
+#define GPIO_MASK(x)		(1U << ((x) % 32))
 
-#define MPA_GPIO_INT_LVL		0x0290
-#define MPA_GPIO_OE_ADDR		0x029c
-#define MPA_GPIO_OUT_ADDR		0x02a0
-#define MPA_GPIO_IN_ADDR 		0x02a4
-#define MPA_GPIO_SEL_LO 		0x0294
+#define MPA_GPIO_INT_LVL	0x0290
+#define MPA_GPIO_OE_ADDR	0x029c
+#define MPA_GPIO_OUT_ADDR	0x02a0
+#define MPA_GPIO_IN_ADDR	0x02a4
+#define MPA_GPIO_SEL_LO		0x0294
+
+#define GPIO_INT_LEVEL_H	0x000001
+#define GPIO_INT_LEVEL_L	0x000000
 
 /**
  * struct xgene_gpio_sb - GPIO-Standby private data structure.
@@ -49,18 +57,30 @@
  */
 struct xgene_gpio_sb {
 	struct bgpio_chip	bgc;
-	u32 *irq;
+	void __iomem *regs;
+	u32    *gic_virq;
+	struct irq_domain *irq_domain;
 	u32 nirq;
+	u32 flags;
 };
 
-static inline struct xgene_gpio_sb *to_xgene_gpio_sb(struct gpio_chip *gc)
-{
-	struct bgpio_chip *bgc = to_bgpio_chip(gc);
+#define NIRQ_MAX(priv) (((priv)->flags >> 8) & 0xff)
+#define NGPIO_MAX(priv) ((priv)->flags & 0xff)
+#define IRQ_START_PIN(priv) (((priv)->flags >> 16) & 0xff)
 
-	return container_of(bgc, struct xgene_gpio_sb, bgc);
+static const struct of_device_id xgene_gpio_sb_of_match[];
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id xgene_gpio_sb_acpi_match[];
+#endif
+
+static unsigned long gic_irq_to_gpio_irq(struct xgene_gpio_sb *priv,
+							unsigned long hwirq)
+{
+	return hwirq - irq_get_irq_data(priv->gic_virq[0])->hwirq;
 }
 
-static void xgene_gpio_set_bit(struct bgpio_chip *bgc, void __iomem *reg, u32 gpio, int val)
+static void xgene_gpio_set_bit(struct bgpio_chip *bgc,
+				void __iomem *reg, u32 gpio, int val)
 {
 	u32 data;
 
@@ -72,23 +92,166 @@ static void xgene_gpio_set_bit(struct bgpio_chip *bgc, void __iomem *reg, u32 gp
 	bgc->write_reg(reg, data);
 }
 
-static int apm_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio)
+static void xgene_gpio_sb_irq_ack(struct irq_data *d)
+{
+	struct irq_data *irqdata;
+	struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
+
+	irqdata = irq_get_irq_data(priv->gic_virq[d->hwirq]);
+	if (!irqdata || !irqdata->chip)
+		return;
+
+	if (irqdata->chip->irq_ack)
+		irqdata->chip->irq_ack(irqdata);
+}
+
+static void xgene_gpio_sb_irq_mask(struct irq_data *d)
+{
+	struct irq_data *irqdata;
+	struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
+
+	irqdata = irq_get_irq_data(priv->gic_virq[d->hwirq]);
+	if (!irqdata || !irqdata->chip)
+		return;
+
+	if (irqdata->chip->irq_mask)
+		irqdata->chip->irq_mask(irqdata);
+}
+
+static void xgene_gpio_sb_irq_unmask(struct irq_data *d)
+{
+	struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
+	struct irq_data *irqdata;
+
+	irqdata = irq_get_irq_data(priv->gic_virq[d->hwirq]);
+	if (!irqdata || !irqdata->chip)
+		return;
+
+	if (irqdata->chip->irq_unmask)
+		irqdata->chip->irq_unmask(irqdata);
+}
+
+static int xgene_gpio_sb_irq_set_type(struct irq_data *d, unsigned int type)
+{
+	struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
+	struct irq_data *irqdata;
+	int gpio = d->hwirq + IRQ_START_PIN(priv);
+	int lvl_type;
+	int ret;
+
+	switch (type & IRQ_TYPE_SENSE_MASK) {
+	case IRQ_TYPE_EDGE_RISING:
+	case IRQ_TYPE_LEVEL_HIGH:
+		lvl_type = GPIO_INT_LEVEL_H;
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+	case IRQ_TYPE_LEVEL_LOW:
+		lvl_type = GPIO_INT_LEVEL_L;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	ret = gpiochip_lock_as_irq(&priv->bgc.gc, gpio);
+	if (ret) {
+		dev_err(priv->bgc.gc.parent,
+		"Unable to configure XGene GPIO standby pin %d as IRQ\n",
+								gpio);
+		return ret;
+	}
+
+	if ((gpio >= IRQ_START_PIN(priv)) &&
+			(d->hwirq < NIRQ_MAX(priv))) {
+		xgene_gpio_set_bit(&priv->bgc, priv->regs + MPA_GPIO_SEL_LO,
+				gpio * 2, 1);
+		xgene_gpio_set_bit(&priv->bgc, priv->regs + MPA_GPIO_INT_LVL,
+				d->hwirq, lvl_type);
+	}
+	if (type & IRQ_TYPE_EDGE_BOTH)
+		irq_set_handler_locked(d, handle_edge_irq);
+	else
+		irq_set_handler_locked(d, handle_level_irq);
+
+	/* Propagate IRQ type setting to parent */
+	irqdata = irq_get_irq_data(priv->gic_virq[d->hwirq]);
+	if (!irqdata || !irqdata->chip || !!irqdata->chip->irq_set_type)
+		return 0;
+	if (type & IRQ_TYPE_EDGE_BOTH)
+		irqdata->chip->irq_set_type(irqdata, IRQ_TYPE_EDGE_RISING);
+	else
+		irqdata->chip->irq_set_type(irqdata, IRQ_TYPE_LEVEL_HIGH);
+
+	return 0;
+}
+
+static void xgene_gpio_sb_irq_shutdown(struct irq_data *d)
+{
+	struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
+
+	gpiochip_unlock_as_irq(&priv->bgc.gc, d->hwirq + IRQ_START_PIN(priv));
+}
+
+static void xgene_gpio_sb_irq_handler(struct irq_desc *desc)
+{
+	struct xgene_gpio_sb *priv = irq_desc_get_handler_data(desc);
+	unsigned int cascade_irq;
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+
+	chained_irq_enter(chip, desc);
+
+	cascade_irq = irq_find_mapping(priv->irq_domain,
+		gic_irq_to_gpio_irq(priv, irq_desc_get_irq_data(desc)->hwirq));
+
+	if (cascade_irq)
+		generic_handle_irq(cascade_irq);
+
+	chained_irq_exit(chip, desc);
+}
+
+static struct irq_chip xgene_gpio_sb_irq_chip = {
+	.name           = "sbgpio",
+	.irq_ack        = xgene_gpio_sb_irq_ack,
+	.irq_mask       = xgene_gpio_sb_irq_mask,
+	.irq_unmask     = xgene_gpio_sb_irq_unmask,
+	.irq_set_type   = xgene_gpio_sb_irq_set_type,
+	.irq_shutdown   = xgene_gpio_sb_irq_shutdown,
+};
+
+static inline struct xgene_gpio_sb *to_xgene_gpio_sb(struct gpio_chip *gc)
+{
+	struct bgpio_chip *bgc = to_bgpio_chip(gc);
+
+	return container_of(bgc, struct xgene_gpio_sb, bgc);
+}
+
+static int xgene_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio)
 {
 	struct xgene_gpio_sb *priv = to_xgene_gpio_sb(gc);
 
-	if (priv->irq[gpio])
-		return priv->irq[gpio];
+	if ((gpio < IRQ_START_PIN(priv)) ||
+	    (gpio > NIRQ_MAX(priv) + IRQ_START_PIN(priv)))
+		return -ENXIO;
 
-	return -ENXIO;
+	return irq_find_mapping(priv->irq_domain, gpio - IRQ_START_PIN(priv));
 }
 
+static int xgene_irq_to_line(struct xgene_gpio_sb *priv, u32 irq)
+{
+	u32 offset = gic_irq_to_gpio_irq(priv, irq_get_irq_data(irq)->hwirq);
+
+	return (offset < NIRQ_MAX(priv)) ?
+			(offset + IRQ_START_PIN(priv)) : -EINVAL;
+}
+
+
 static int xgene_gpio_sb_probe(struct platform_device *pdev)
 {
 	struct xgene_gpio_sb *priv;
 	u32 ret, i;
-	u32 default_lines[] = {0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D};
+	int virq, line;
 	struct resource *res;
 	void __iomem *regs;
+	const struct of_device_id *of_id;
 
 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 	if (!priv)
@@ -99,38 +262,79 @@ static int xgene_gpio_sb_probe(struct platform_device *pdev)
 	if (IS_ERR(regs))
 		return PTR_ERR(regs);
 
+	of_id = of_match_device(xgene_gpio_sb_of_match, &pdev->dev);
+	if (of_id)
+		priv->flags = (uintptr_t)of_id->data;
+#ifdef CONFIG_ACPI
+	else {
+		const struct acpi_device_id *acpi_id;
+
+		acpi_id = acpi_match_device(xgene_gpio_sb_acpi_match,
+								&pdev->dev);
+		if (acpi_id)
+			priv->flags = (uintptr_t)acpi_id->driver_data;
+	}
+#endif
+
+	priv->regs = regs;
 	ret = bgpio_init(&priv->bgc, &pdev->dev, 4,
 			regs + MPA_GPIO_IN_ADDR,
 			regs + MPA_GPIO_OUT_ADDR, NULL,
 			regs + MPA_GPIO_OE_ADDR, NULL, 0);
-        if (ret)
-                return ret;
-
-	priv->bgc.gc.to_irq = apm_gpio_sb_to_irq;
-	priv->bgc.gc.ngpio = XGENE_MAX_GPIO_DS;
+	if (ret)
+		return ret;
 
-	priv->nirq = XGENE_MAX_GPIO_DS_IRQ;
+	priv->bgc.gc.to_irq = xgene_gpio_sb_to_irq;
+	priv->bgc.gc.ngpio = NGPIO_MAX(priv);
 
-	priv->irq = devm_kzalloc(&pdev->dev, sizeof(u32) * XGENE_MAX_GPIO_DS,
-				   GFP_KERNEL);
-	if (!priv->irq)
+	priv->gic_virq = devm_kzalloc(&pdev->dev,
+			sizeof(u32) * NIRQ_MAX(priv),
+			GFP_KERNEL);
+	if (!priv->gic_virq)
 		return -ENOMEM;
 
-	for (i = 0; i < priv->nirq; i++) {
-		priv->irq[default_lines[i]] = platform_get_irq(pdev, i);
-		xgene_gpio_set_bit(&priv->bgc, regs + MPA_GPIO_SEL_LO,
-                                   default_lines[i] * 2, 1);
-		xgene_gpio_set_bit(&priv->bgc, regs + MPA_GPIO_INT_LVL, i, 1);
+	/* Mapping and handling GIC irqs*/
+	for (i = 0; i < NIRQ_MAX(priv); i++) {
+		virq = platform_get_irq(pdev, i);
+		if (virq < 0)
+			break;
+		priv->gic_virq[i] = virq;
+		line = xgene_irq_to_line(priv, virq);
+		if (line < IRQ_START_PIN(priv))
+			break;
+
+		irq_set_chained_handler_and_data(virq,
+				&xgene_gpio_sb_irq_handler, priv);
 	}
 
+	priv->nirq = i;
+
 	platform_set_drvdata(pdev, priv);
 
+	priv->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
+			priv->nirq,
+			&irq_domain_simple_ops, priv);
+	if (!priv->irq_domain)
+		return -ENODEV;
+
 	ret = gpiochip_add(&priv->bgc.gc);
-	if (ret)
-		dev_err(&pdev->dev, "failed to register X-Gene GPIO Standby driver\n");
-	else
+	if (ret) {
+		dev_err(&pdev->dev,
+			"failed to register X-Gene GPIO Standby driver\n");
+		irq_domain_remove(priv->irq_domain);
+	} else
 		dev_info(&pdev->dev, "X-Gene GPIO Standby driver registered\n");
 
+	priv->bgc.gc.irqdomain = priv->irq_domain;
+
+	/* Init for new mapped irqs*/
+	for (i = 0; i < priv->nirq; i++) {
+		int irq = irq_create_mapping(priv->irq_domain, i);
+
+		irq_set_chip_data(irq, priv);
+		irq_set_chip(irq, &xgene_gpio_sb_irq_chip);
+	}
+
 	if (priv->nirq > 0) {
 		/* Register interrupt handlers for gpio signaled acpi events */
 		acpi_gpiochip_request_interrupts(&priv->bgc.gc);
@@ -143,22 +347,23 @@ static int xgene_gpio_sb_remove(struct platform_device *pdev)
 {
 	struct xgene_gpio_sb *priv = platform_get_drvdata(pdev);
 
-	if (priv->nirq > 0) {
+	if (priv->nirq > 0)
 		acpi_gpiochip_free_interrupts(&priv->bgc.gc);
-	}
+
+	irq_domain_remove(priv->irq_domain);
 
 	return bgpio_remove(&priv->bgc);
 }
 
 static const struct of_device_id xgene_gpio_sb_of_match[] = {
-	{.compatible = "apm,xgene-gpio-sb", },
+	{.compatible = "apm,xgene-gpio-sb", .data = (const void *)SBGPIO_XGENE},
 	{},
 };
 MODULE_DEVICE_TABLE(of, xgene_gpio_sb_of_match);
 
 #ifdef CONFIG_ACPI
 static const struct acpi_device_id xgene_gpio_sb_acpi_match[] = {
-	{"APMC0D15", 0},
+	{"APMC0D15", SBGPIO_XGENE},
 	{},
 };
 MODULE_DEVICE_TABLE(acpi, xgene_gpio_sb_acpi_match);
-- 
2.2.0

[PATCH v3 2/3] Documentation: gpio: Update description for X-Gene standby GPIO controller DTS binding

[Quan Nguyen]

Update description for X-Gene standby GPIO controller DTS binding to
support GPIO line configuration as input, output or external IRQ pin.

Signed-off-by: Y Vo <yvo-qTEPVZfXA3Y@public.gmane.org>
Signed-off-by: Quan Nguyen <qnguyen-qTEPVZfXA3Y@public.gmane.org>
---
 .../devicetree/bindings/gpio/gpio-xgene-sb.txt     | 49 +++++++++++++++++-----
 1 file changed, 38 insertions(+), 11 deletions(-)

diff --git a/Documentation/devicetree/bindings/gpio/gpio-xgene-sb.txt b/Documentation/devicetree/bindings/gpio/gpio-xgene-sb.txt
index dae1300..a960d1b 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-xgene-sb.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-xgene-sb.txt
@@ -1,10 +1,20 @@
 APM X-Gene Standby GPIO controller bindings
 
-This is a gpio controller in the standby domain.
-
-There are 20 GPIO pins from 0..21. There is no GPIO_DS14 or GPIO_DS15,
-only GPIO_DS8..GPIO_DS13 support interrupts. The IRQ mapping
-is currently 1-to-1 on interrupts 0x28 thru 0x2d.
+This is a gpio controller in the standby domain. It also supports interrupt in
+some particular pins which are sourced to its parent interrupt controller
+as diagram below:
+                           +-----------------+
+                           | X-Gene standby  |
+                           | GPIO controller +--------- GPIO_0
++------------+             |                 | ...
+| Parent IRQ |             |                 +--------- GPIO_8/EXT_INT_0
+| controller |  EXT_INT_0  |                 | ...
+| (GICv2)    +-------------+                 +--------- GPIO_[N+8]/EXT_INT_N
+|            |  ...        |                 |
+|            |  EXT_INT_N  |                 +--------- GPIO_[N+9]
+|            +-------------+                 | ...
+|            |             |                 +--------- GPIO_MAX
++------------+             +-----------------+
 
 Required properties:
 - compatible: "apm,xgene-gpio-sb" for the X-Gene Standby GPIO controller
@@ -16,6 +26,11 @@ Required properties:
 		1 = active low
 - gpio-controller: Marks the device node as a GPIO controller.
 - interrupts: Shall contain exactly 6 interrupts.
+- interrupt-parent: Phandle of the parent interrupt controller.
+- interrupt-cells: Shoule be two.
+       - first cell is 0-N coresponding for EXT_INT_0 to EXT_INT_N.
+       - second cell is used to specify flags.
+- interrupt-controller: Marks the device node as an interrupt controller.
 
 Example:
 	sbgpio: sbgpio@17001000 {
@@ -23,10 +38,22 @@ Example:
 		reg = <0x0 0x17001000 0x0 0x400>;
 		#gpio-cells = <2>;
 		gpio-controller;
-		interrupts = 	<0x0 0x28 0x1>,
-				<0x0 0x29 0x1>,
-				<0x0 0x2a 0x1>,
-				<0x0 0x2b 0x1>,
-				<0x0 0x2c 0x1>,
-				<0x0 0x2d 0x1>;
+		interrupt-parent = <&gic>;
+		interrupts =    <0x0 0x28 0x4>,
+				<0x0 0x29 0x4>,
+				<0x0 0x2a 0x4>,
+				<0x0 0x2b 0x4>,
+				<0x0 0x2c 0x4>,
+				<0x0 0x2d 0x4>;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+	};
+
+	testuser {
+		compatible = "example,testuser";
+		/* Use the GPIO_13/EXT_INT_5 line as an active high triggered
+		 * level interrupt
+		 */
+		interrupts = <5 4>;
+		interrupt-parent = <&sbgpio>;
 	};
-- 
2.2.0

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[PATCH v3 3/3] arm64: dts: Update X-Gene standby GPIO controller DTS entries

[Quan Nguyen]

Update APM X-Gene standby GPIO controller DTS entries to support
GPIO line configuration as input, output or external IRQ pin.

Signed-off-by: Y Vo <yvo@apm.com>
Signed-off-by: Quan Nguyen <qnguyen@apm.com>
---
 arch/arm64/boot/dts/apm/apm-storm.dtsi | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index a21e08a..c534a19 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -891,12 +891,15 @@
 			reg = <0x0 0x17001000 0x0 0x400>;
 			#gpio-cells = <2>;
 			gpio-controller;
-			interrupts = 	<0x0 0x28 0x1>,
+			interrupt-parent = <&gic>;
+			interrupts =	<0x0 0x28 0x1>,
 					<0x0 0x29 0x1>,
 					<0x0 0x2a 0x1>,
 					<0x0 0x2b 0x1>,
 					<0x0 0x2c 0x1>,
 					<0x0 0x2d 0x1>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
 		};
 
 		rtc: rtc@10510000 {
-- 
2.2.0

Re: [PATCH v3 1/3] gpio: xgene: Enable X-Gene standby GPIO as interrupt controller

[Thomas Gleixner]

On Thu, 7 Jan 2016, Quan Nguyen wrote:
> -static int apm_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio)
> +static void xgene_gpio_sb_irq_ack(struct irq_data *d)
> +{
> +	struct irq_data *irqdata;
> +	struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
> +
> +	irqdata = irq_get_irq_data(priv->gic_virq[d->hwirq]);
> +	if (!irqdata || !irqdata->chip)
> +		return;

What the heck is this? Why are you looking up some random other irq and fiddle
with its irq chip?

This is a 1:1 mapping from your gpio irq to a gic irq. We have hierarchical
interrupt domains for this.

Thanks,

	tglx

Re: [PATCH v3 1/3] gpio: xgene: Enable X-Gene standby GPIO as interrupt controller

[Marc Zyngier]

On 08/01/16 08:45, Thomas Gleixner wrote:
> On Thu, 7 Jan 2016, Quan Nguyen wrote:
>> -static int apm_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio)
>> +static void xgene_gpio_sb_irq_ack(struct irq_data *d)
>> +{
>> +	struct irq_data *irqdata;
>> +	struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
>> +
>> +	irqdata = irq_get_irq_data(priv->gic_virq[d->hwirq]);
>> +	if (!irqdata || !irqdata->chip)
>> +		return;
> 
> What the heck is this? Why are you looking up some random other irq and fiddle
> with its irq chip?
> 
> This is a 1:1 mapping from your gpio irq to a gic irq. We have hierarchical
> interrupt domains for this.

I've said the exact same thing back in October:

http://lists.infradead.org/pipermail/linux-arm-kernel/2015-October/381996.html

but obviously I wasn't clear enough...

	M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH v3 2/3] Documentation: gpio: Update description for X-Gene standby GPIO controller DTS binding

[Rob Herring]

On Thu, Jan 07, 2016 at 05:27:07PM +0700, Quan Nguyen wrote:
> Update description for X-Gene standby GPIO controller DTS binding to
> support GPIO line configuration as input, output or external IRQ pin.
> 
> Signed-off-by: Y Vo <yvo@apm.com>
> Signed-off-by: Quan Nguyen <qnguyen@apm.com>
> ---
>  .../devicetree/bindings/gpio/gpio-xgene-sb.txt     | 49 +++++++++++++++++-----
>  1 file changed, 38 insertions(+), 11 deletions(-)

Acked-by: Rob Herring <robh@kernel.org>