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Mon, 09 Dec 2024 05:32:20 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B95WJx0022049 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 9 Dec 2024 05:32:19 GMT Received: from [10.151.36.43] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 8 Dec 2024 21:32:13 -0800 Message-ID: <569d2c24-daa9-65e2-e5a4-2c2ced2a3b57@quicinc.com> Date: Mon, 9 Dec 2024 11:02:11 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.0 Subject: Re: [PATCH v14 7/8] arm64: dts: qcom: ipq9574: Add SPI nand support Content-Language: en-US To: Konrad Dybcio , , , , , , , , , , , , , , , CC: , References: <20241120091507.1404368-1-quic_mdalam@quicinc.com> <20241120091507.1404368-8-quic_mdalam@quicinc.com> <4c1fe789-5190-465d-bb41-3fe1534d2523@oss.qualcomm.com> From: Md Sadre Alam In-Reply-To: <4c1fe789-5190-465d-bb41-3fe1534d2523@oss.qualcomm.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: j5vlEIXgkChl_JlH7o1N1NsBaDlrhm4m X-Proofpoint-GUID: j5vlEIXgkChl_JlH7o1N1NsBaDlrhm4m X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 spamscore=0 bulkscore=0 adultscore=0 clxscore=1015 mlxlogscore=999 malwarescore=0 phishscore=0 lowpriorityscore=0 impostorscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412090043 On 12/5/2024 10:49 PM, Konrad Dybcio wrote: > On 20.11.2024 10:15 AM, Md Sadre Alam wrote: >> Add SPI NAND support for ipq9574 SoC. >> >> Signed-off-by: Md Sadre Alam >> --- > > [...] > > Feel free to put dt patches in a separate series after Miquel picks > up the mtd changes Ok > >> &usb_0_dwc3 { >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> index d1fd35ebc4a2..45fb26bc9480 100644 > > board and dtsi patches should be 2 separate ones Ok > >> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> @@ -330,6 +330,33 @@ tcsr: syscon@1937000 { >> reg = <0x01937000 0x21000>; >> }; >> >> + qpic_bam: dma-controller@7984000 { >> + compatible = "qcom,bam-v1.7.0"; >> + reg = <0x7984000 0x1c000>; > > Please pad the address part to 8 hex digits with leading zeroes Ok > >> + interrupts = ; >> + clocks = <&gcc GCC_QPIC_AHB_CLK>; >> + clock-names = "bam_clk"; >> + #dma-cells = <1>; >> + qcom,ee = <0>; >> + status = "disabled"; >> + }; >> + >> + qpic_nand: spi@79b0000 { >> + compatible = "qcom,ipq9574-snand"; >> + reg = <0x79b0000 0x10000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + clocks = <&gcc GCC_QPIC_CLK>, >> + <&gcc GCC_QPIC_AHB_CLK>, >> + <&gcc GCC_QPIC_IO_MACRO_CLK>; >> + clock-names = "core", "aon", "iom"; >> + dmas = <&qpic_bam 0>, >> + <&qpic_bam 1>, >> + <&qpic_bam 2>; >> + dma-names = "tx", "rx", "cmd"; > > Please make clock/dma names a vertical list, like clocks/dmas Ok > > Also, is it okay not to use any of the GCC_QPIC_BCR/ > GCC_QPIC_AHB_ARES/GCC_QPIC_ARES resets found in GCC? It's recommended by HW team, will check once again with HW team. > > Konrad