From mboxrd@z Thu Jan 1 00:00:00 1970 From: Michal Simek Subject: Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze Date: Tue, 26 Jan 2016 10:59:12 +0100 Message-ID: <56A74370.4090000@xilinx.com> References: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> <1452620173-4905-4-git-send-email-bharatku@xilinx.com> <4734542.KZZp0TeeeM@wuerfel> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <4734542.KZZp0TeeeM@wuerfel> Sender: linux-kernel-owner@vger.kernel.org To: Arnd Bergmann , Bharat Kumar Gogada Cc: bhelgaas@google.com, lorenzo.pieralisi@arm.com, paul.burton@imgtec.com, yinghai@kernel.org, wangyijing@huawei.com, robh@kernel.org, russell.joyce@york.ac.uk, sorenb@xilinx.com, jiang.liu@linux.intel.com, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Bharat Kumar Gogada , Ravi Kiran Gummaluri List-Id: devicetree@vger.kernel.org On 12.1.2016 23:27, Arnd Bergmann wrote: > On Tuesday 12 January 2016 23:06:11 Bharat Kumar Gogada wrote: >> Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both >> Zynq and Microblaze Architectures. >> With these modifications drivers/pci/host/pcie-xilinx.c, will >> work on both Zynq and Microblaze Architectures. >> >> Signed-off-by: Bharat Kumar Gogada >> Signed-off-by: Ravi Kiran Gummaluri > > I think this patch should be split into three, as you are doing three > unrelated things here. > >> --- >> Changes: >> Changed Total number of MSI IRQ count logic according to both architectures. >> Updated MSI assigning functions accordingly to new count. >> Modified irq_domain_add_linear with new MSI IRQ count. >> Added #ifdef to pci_fixup_irqs which is ARM specific API. >> --- >> drivers/pci/host/pcie-xilinx.c | 22 +++++++++++++++++----- >> 1 file changed, 17 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c >> index 3e3757f..1981948 100644 >> --- a/drivers/pci/host/pcie-xilinx.c >> +++ b/drivers/pci/host/pcie-xilinx.c >> @@ -92,7 +92,12 @@ >> #define ECAM_DEV_NUM_SHIFT 12 >> >> /* Number of MSI IRQs */ >> -#define XILINX_NUM_MSI_IRQS 128 >> +#define XILINX_NUM_MSI_IRQS 128 >> +#ifdef CONFIG_ARM >> +#define TOT_NR_IRQS XILINX_NUM_MSI_IRQS >> +#else >> +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS) >> +#endif > > Something looks wrong here in the microblaze variant. What does NR_IRQS > have to do with it? Arnd: What was the story regarding NR_IRQS? I remember some discussion about it but just forget. Default value in include/asm-generic/irq.h is 64. Current value is 32 because microblaze primary interrupt controller is axi_intc core which has up to 32 input lines. Thanks, Michal