[PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC

[PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC

[Andre Przywara]

Based on the Allwinner A64 user manual and on the previous sunxi
pinctrl drivers this introduces the pin multiplex assignments for
the ARMv8 Allwinner A64 SoC.
Port A is apparently used for the fixed function DRAM controller, so
the ports start at B here (the manual mentions "n from 1 to 7", so
not starting at 0).

Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
---
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 arch/arm64/Kconfig.platforms                       |   1 +
 drivers/pinctrl/sunxi/Kconfig                      |   4 +
 drivers/pinctrl/sunxi/Makefile                     |   1 +
 drivers/pinctrl/sunxi/pinctrl-a64.c                | 606 +++++++++++++++++++++
 5 files changed, 613 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-a64.c

diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 9213b27..9050002 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -21,6 +21,7 @@ Required properties:
   "allwinner,sun9i-a80-r-pinctrl"
   "allwinner,sun8i-a83t-pinctrl"
   "allwinner,sun8i-h3-pinctrl"
+  "allwinner,a64-pinctrl"
 
 - reg: Should contain the register physical address and length for the
   pin controller.
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index fc7cf4b..03f0f9d 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -2,6 +2,7 @@ menu "Platform selection"
 
 config ARCH_SUNXI
 	bool "Allwinner sunxi 64-bit SoC Family"
+	select PINCTRL_A64
 	select SUNXI_MMC
 	help
 	  This enables support for Allwinner sunxi based SoCs like the A64.
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index f8dbc8b..68873f2 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -64,4 +64,8 @@ config PINCTRL_SUN9I_A80_R
 	depends on RESET_CONTROLLER
 	select PINCTRL_SUNXI_COMMON
 
+config PINCTRL_A64
+	bool
+	select PINCTRL_SUNXI_COMMON
+
 endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index ef82f22..e00ccde 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_SUN7I_A20)		+= pinctrl-sun7i-a20.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23)		+= pinctrl-sun8i-a23.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23_R)	+= pinctrl-sun8i-a23-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A33)		+= pinctrl-sun8i-a33.o
+obj-$(CONFIG_PINCTRL_A64)		+= pinctrl-a64.o
 obj-$(CONFIG_PINCTRL_SUN8I_A83T)	+= pinctrl-sun8i-a83t.o
 obj-$(CONFIG_PINCTRL_SUN8I_H3)		+= pinctrl-sun8i-h3.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80)		+= pinctrl-sun9i-a80.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-a64.c b/drivers/pinctrl/sunxi/pinctrl-a64.c
new file mode 100644
index 0000000..e72b079
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-a64.c
@@ -0,0 +1,606 @@
+/*
+ * Allwinner A64 SoCs pinctrl driver.
+ *
+ * Copyright (C) 2016 - ARM Ltd.
+ * Author: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
+ *
+ * Based on pinctrl-sun7i-a20.c, which is:
+ * Copyright (C) 2014 Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin a64_pins[] = {
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart2"),		/* TX */
+		  SUNXI_FUNCTION(0x4, "jtag"),		/* MS0 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),	/* EINT0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart2"),		/* RX */
+		  SUNXI_FUNCTION(0x4, "jtag"),		/* CK0 */
+		  SUNXI_FUNCTION(0x5, "sim"),		/* VCCEN */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),		/* EINT1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart2"),		/* RTS */
+		  SUNXI_FUNCTION(0x4, "jtag"),		/* DO0 */
+		  SUNXI_FUNCTION(0x5, "sim"),		/* VPPEN */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),		/* EINT2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart2"),		/* CTS */
+		  SUNXI_FUNCTION(0x3, "i2s0"),		/* MCLK */
+		  SUNXI_FUNCTION(0x4, "jtag"),		/* DI0 */
+		  SUNXI_FUNCTION(0x5, "sim"),		/* VPPPP */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),		/* EINT3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "aif2"),		/* SYNC */
+		  SUNXI_FUNCTION(0x3, "i2s0"),		/* SYNC */
+		  SUNXI_FUNCTION(0x5, "sim"),		/* CLK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),		/* EINT4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "aif2"),		/* BCLK */
+		  SUNXI_FUNCTION(0x3, "i2s0"),		/* BCLK */
+		  SUNXI_FUNCTION(0x5, "sim"),		/* DATA */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),		/* EINT5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "aif2"),		/* DOUT */
+		  SUNXI_FUNCTION(0x3, "i2s0"),		/* DOUT */
+		  SUNXI_FUNCTION(0x5, "sim"),		/* RST */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),		/* EINT6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "aif2"),		/* DIN */
+		  SUNXI_FUNCTION(0x3, "i2s0"),		/* DIN */
+		  SUNXI_FUNCTION(0x5, "sim"),		/* DET */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),		/* EINT7 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x4, "uart0"),		/* TX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),		/* EINT8 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x4, "uart0"),		/* RX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),		/* EINT9 */
+	/* Hole */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* NWE */
+		  SUNXI_FUNCTION(0x4, "spi0")),		/* MOSI */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* NALE */
+		  SUNXI_FUNCTION(0x3, "mmc2"),		/* DS */
+		  SUNXI_FUNCTION(0x4, "spi0")),		/* MISO */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCLE */
+		  SUNXI_FUNCTION(0x4, "spi0")),		/* SCK */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCE1 */
+		  SUNXI_FUNCTION(0x4, "spi0")),		/* CS */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0")),	/* NCE0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* NRE# */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* CLK */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* NRB0 */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* CMD */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0")),	/* NRB1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ0 */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ1 */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ2 */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ3 */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ4 */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ5 */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ6 */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ7 */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D7 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQS */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* RST */
+	/* Hole */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D2 */
+		  SUNXI_FUNCTION(0x3, "uart3"),		/* TX */
+		  SUNXI_FUNCTION(0x4, "spi1"),		/* CS */
+		  SUNXI_FUNCTION(0x5, "ccir")),		/* CLK */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D3 */
+		  SUNXI_FUNCTION(0x3, "uart3"),		/* RX */
+		  SUNXI_FUNCTION(0x4, "spi1"),		/* CLK */
+		  SUNXI_FUNCTION(0x5, "ccir")),		/* DE */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D4 */
+		  SUNXI_FUNCTION(0x3, "uart4"),		/* TX */
+		  SUNXI_FUNCTION(0x4, "spi1"),		/* MOSI */
+		  SUNXI_FUNCTION(0x5, "ccir")),		/* HSYNC */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D5 */
+		  SUNXI_FUNCTION(0x3, "uart4"),		/* RX */
+		  SUNXI_FUNCTION(0x4, "spi1"),		/* MISO */
+		  SUNXI_FUNCTION(0x5, "ccir")),		/* VSYNC */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D6 */
+		  SUNXI_FUNCTION(0x3, "uart4"),		/* RTS */
+		  SUNXI_FUNCTION(0x5, "ccir")),		/* D0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D7 */
+		  SUNXI_FUNCTION(0x3, "uart4"),		/* CTS */
+		  SUNXI_FUNCTION(0x5, "ccir")),		/* D1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D10 */
+		  SUNXI_FUNCTION(0x5, "ccir")),		/* D2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D11 */
+		  SUNXI_FUNCTION(0x5, "ccir")),		/* D3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D12 */
+		  SUNXI_FUNCTION(0x4, "emac"),		/* ERXD3 */
+		  SUNXI_FUNCTION(0x5, "ccir")),		/* D4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D13 */
+		  SUNXI_FUNCTION(0x4, "emac"),		/* ERXD2 */
+		  SUNXI_FUNCTION(0x5, "ccir")),		/* D5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D14 */
+		  SUNXI_FUNCTION(0x4, "emac")),		/* ERXD1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D15 */
+		  SUNXI_FUNCTION(0x4, "emac")),		/* ERXD0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D18 */
+		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VP0 */
+		  SUNXI_FUNCTION(0x4, "emac")),		/* ERXCK */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D19 */
+		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VN0 */
+		  SUNXI_FUNCTION(0x4, "emac")),		/* ERXCTL */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D20 */
+		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VP1 */
+		  SUNXI_FUNCTION(0x4, "emac")),		/* ENULL */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D21 */
+		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VN1 */
+		  SUNXI_FUNCTION(0x4, "emac"),		/* ETXD3 */
+		  SUNXI_FUNCTION(0x5, "ccir")),		/* D6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D22 */
+		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VP2 */
+		  SUNXI_FUNCTION(0x4, "emac"),		/* ETXD2 */
+		  SUNXI_FUNCTION(0x5, "ccir")),		/* D7 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D23 */
+		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VN2 */
+		  SUNXI_FUNCTION(0x4, "emac")),		/* ETXD1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* CLK */
+		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VPC */
+		  SUNXI_FUNCTION(0x4, "emac")),		/* ETXD0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* DE */
+		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VNC */
+		  SUNXI_FUNCTION(0x4, "emac")),		/* ETXCK */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* HSYNC */
+		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VP3 */
+		  SUNXI_FUNCTION(0x4, "emac")),		/* ETXCTL */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* VSYNC */
+		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VN3 */
+		  SUNXI_FUNCTION(0x4, "emac")),		/* ECLKIN */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "pwm"),		/* PWM0 */
+		  SUNXI_FUNCTION(0x4, "emac")),		/* EMDC */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x4, "emac")),		/* EMDIO */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out")),
+	/* Hole */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi0"),		/* PCK */
+		  SUNXI_FUNCTION(0x4, "ts0")),		/* CLK */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi0"),		/* CK */
+		  SUNXI_FUNCTION(0x4, "ts0")),		/* ERR */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi0"),		/* HSYNC */
+		  SUNXI_FUNCTION(0x4, "ts0")),		/* SYNC */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi0"),		/* VSYNC */
+		  SUNXI_FUNCTION(0x4, "ts0")),		/* DVLD */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi0"),		/* D0 */
+		  SUNXI_FUNCTION(0x4, "ts0")),		/* D0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi0"),		/* D1 */
+		  SUNXI_FUNCTION(0x4, "ts0")),		/* D1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi0"),		/* D2 */
+		  SUNXI_FUNCTION(0x4, "ts0")),		/* D2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi0"),		/* D3 */
+		  SUNXI_FUNCTION(0x4, "ts0")),		/* D3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi0"),		/* D4 */
+		  SUNXI_FUNCTION(0x4, "ts0")),		/* D4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi0"),		/* D5 */
+		  SUNXI_FUNCTION(0x4, "ts0")),		/* D5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi0"),		/* D6 */
+		  SUNXI_FUNCTION(0x4, "ts0")),		/* D6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi0"),		/* D7 */
+		  SUNXI_FUNCTION(0x4, "ts0")),		/* D7 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi0")),		/* SCK */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi0")),		/* SDA */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "pll"),		/* LOCK_DBG */
+		  SUNXI_FUNCTION(0x3, "i2c2")),		/* SCK */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x3, "i2c2")),		/* SDA */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out")),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out")),
+	/* Hole */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D1 */
+		  SUNXI_FUNCTION(0x3, "jtag")),		/* MSI */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D0 */
+		  SUNXI_FUNCTION(0x3, "jtag")),		/* DI1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc0"),		/* CLK */
+		  SUNXI_FUNCTION(0x3, "uart0")),	/* TX */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc0"),		/* CMD */
+		  SUNXI_FUNCTION(0x3, "jtag")),		/* DO1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D3 */
+		  SUNXI_FUNCTION(0x4, "uart0")),	/* RX */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D2 */
+		  SUNXI_FUNCTION(0x3, "jtag")),		/* CK1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out")),
+	/* Hole */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc1"),		/* CLK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),	/* EINT0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc1"),		/* CMD */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),	/* EINT1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D0 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),	/* EINT2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D1 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),	/* EINT3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D2 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),	/* EINT4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D3 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),	/* EINT5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart1"),		/* TX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),	/* EINT6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart1"),		/* RX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),	/* EINT7 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart1"),		/* RTS */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),	/* EINT8 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart1"),		/* CTS */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),	/* EINT9 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "aif3"),		/* SYNC */
+		  SUNXI_FUNCTION(0x3, "i2s1"),		/* SYNC */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),	/* EINT10 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "aif3"),		/* BCLK */
+		  SUNXI_FUNCTION(0x3, "i2s1"),		/* BCLK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),	/* EINT11 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "aif3"),		/* DOUT */
+		  SUNXI_FUNCTION(0x3, "i2s1"),		/* DOUT */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),	/* EINT12 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "aif3"),		/* DIN */
+		  SUNXI_FUNCTION(0x3, "i2s1"),		/* DIN */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)),	/* EINT13 */
+	/* Hole */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2c0"),		/* SCK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),	/* EINT0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2c0"),		/* SDA */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),	/* EINT1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2c1"),		/* SCK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),	/* EINT2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2c1"),		/* SDA */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),	/* EINT3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart3"),		/* TX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),	/* EINT4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart3"),		/* RX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),	/* EINT5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart3"),		/* RTS */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),	/* EINT6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart3"),		/* CTS */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),	/* EINT7 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "owa"),		/* OUT */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),	/* EINT8 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),	/* EINT9 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mic"),		/* CLK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)),	/* EINT10 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mic"),		/* DATA */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)),	/* EINT11 */
+};
+
+static const struct sunxi_pinctrl_desc a64_pinctrl_data = {
+	.pins = a64_pins,
+	.npins = ARRAY_SIZE(a64_pins),
+	.irq_banks = 3,
+};
+
+static int a64_pinctrl_probe(struct platform_device *pdev)
+{
+	return sunxi_pinctrl_init(pdev,
+				  &a64_pinctrl_data);
+}
+
+static const struct of_device_id a64_pinctrl_match[] = {
+	{ .compatible = "allwinner,a64-pinctrl", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, a64_pinctrl_match);
+
+static struct platform_driver a64_pinctrl_driver = {
+	.probe	= a64_pinctrl_probe,
+	.driver	= {
+		.name		= "a64-pinctrl",
+		.of_match_table	= a64_pinctrl_match,
+	},
+};
+module_platform_driver(a64_pinctrl_driver);
+
+MODULE_AUTHOR("Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>");
+MODULE_DESCRIPTION("Allwinner A64 pinctrl driver");
+MODULE_LICENSE("GPL");
-- 
2.6.4

Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC

[Karsten Merker]

On Mon, Feb 01, 2016 at 05:39:24PM +0000, Andre Przywara wrote:
> Based on the Allwinner A64 user manual and on the previous sunxi
> pinctrl drivers this introduces the pin multiplex assignments for
> the ARMv8 Allwinner A64 SoC.
> Port A is apparently used for the fixed function DRAM controller, so
> the ports start at B here (the manual mentions "n from 1 to 7", so
> not starting at 0).
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
>  arch/arm64/Kconfig.platforms                       |   1 +
>  drivers/pinctrl/sunxi/Kconfig                      |   4 +
>  drivers/pinctrl/sunxi/Makefile                     |   1 +
>  drivers/pinctrl/sunxi/pinctrl-a64.c                | 606 +++++++++++++++++++++
>  5 files changed, 613 insertions(+)
>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-a64.c
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> index 9213b27..9050002 100644
> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> @@ -21,6 +21,7 @@ Required properties:
>    "allwinner,sun9i-a80-r-pinctrl"
>    "allwinner,sun8i-a83t-pinctrl"
>    "allwinner,sun8i-h3-pinctrl"
> +  "allwinner,a64-pinctrl"

Hello,

on all other Allwinner SoCs we use the SoC family as part of the
compatible, as well as in the names of the Kconfig options. To
keep things consistent, I would like to propose doing the same on
Arm64, i.e. using allwinner,sun50i-a64-pinctrl instead of
allwinner,a64-pinctrl.

>  - reg: Should contain the register physical address and length for the
>    pin controller.
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index fc7cf4b..03f0f9d 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -2,6 +2,7 @@ menu "Platform selection"
>  
>  config ARCH_SUNXI
>  	bool "Allwinner sunxi 64-bit SoC Family"
> +	select PINCTRL_A64

Same as above, just with the name of the Kconfig option.
s/PINCTRL_A64/PINCTRL_SUN50I_A64/ ?

>  	select SUNXI_MMC
>  	help
>  	  This enables support for Allwinner sunxi based SoCs like the A64.
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index f8dbc8b..68873f2 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -64,4 +64,8 @@ config PINCTRL_SUN9I_A80_R
>  	depends on RESET_CONTROLLER
>  	select PINCTRL_SUNXI_COMMON
>  
> +config PINCTRL_A64

see above

> +	bool
> +	select PINCTRL_SUNXI_COMMON
> +
>  endif
> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
> index ef82f22..e00ccde 100644
> --- a/drivers/pinctrl/sunxi/Makefile
> +++ b/drivers/pinctrl/sunxi/Makefile
> @@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_SUN7I_A20)		+= pinctrl-sun7i-a20.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A23)		+= pinctrl-sun8i-a23.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A23_R)	+= pinctrl-sun8i-a23-r.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A33)		+= pinctrl-sun8i-a33.o
> +obj-$(CONFIG_PINCTRL_A64)		+= pinctrl-a64.o

see above

>  obj-$(CONFIG_PINCTRL_SUN8I_A83T)	+= pinctrl-sun8i-a83t.o
>  obj-$(CONFIG_PINCTRL_SUN8I_H3)		+= pinctrl-sun8i-h3.o
>  obj-$(CONFIG_PINCTRL_SUN9I_A80)		+= pinctrl-sun9i-a80.o
> diff --git a/drivers/pinctrl/sunxi/pinctrl-a64.c b/drivers/pinctrl/sunxi/pinctrl-a64.c
> new file mode 100644
> index 0000000..e72b079
> --- /dev/null
> +++ b/drivers/pinctrl/sunxi/pinctrl-a64.c
> @@ -0,0 +1,606 @@
> +/*
> + * Allwinner A64 SoCs pinctrl driver.
> + *
> + * Copyright (C) 2016 - ARM Ltd.
> + * Author: Andre Przywara <andre.przywara@arm.com>
> + *
> + * Based on pinctrl-sun7i-a20.c, which is:
> + * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +
> +#include "pinctrl-sunxi.h"
> +
> +static const struct sunxi_desc_pin a64_pins[] = {
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "uart2"),		/* TX */
> +		  SUNXI_FUNCTION(0x4, "jtag"),		/* MS0 */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),	/* EINT0 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "uart2"),		/* RX */
> +		  SUNXI_FUNCTION(0x4, "jtag"),		/* CK0 */
> +		  SUNXI_FUNCTION(0x5, "sim"),		/* VCCEN */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),		/* EINT1 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "uart2"),		/* RTS */
> +		  SUNXI_FUNCTION(0x4, "jtag"),		/* DO0 */
> +		  SUNXI_FUNCTION(0x5, "sim"),		/* VPPEN */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),		/* EINT2 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "uart2"),		/* CTS */
> +		  SUNXI_FUNCTION(0x3, "i2s0"),		/* MCLK */
> +		  SUNXI_FUNCTION(0x4, "jtag"),		/* DI0 */
> +		  SUNXI_FUNCTION(0x5, "sim"),		/* VPPPP */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),		/* EINT3 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "aif2"),		/* SYNC */
> +		  SUNXI_FUNCTION(0x3, "i2s0"),		/* SYNC */
> +		  SUNXI_FUNCTION(0x5, "sim"),		/* CLK */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),		/* EINT4 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "aif2"),		/* BCLK */
> +		  SUNXI_FUNCTION(0x3, "i2s0"),		/* BCLK */
> +		  SUNXI_FUNCTION(0x5, "sim"),		/* DATA */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),		/* EINT5 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "aif2"),		/* DOUT */
> +		  SUNXI_FUNCTION(0x3, "i2s0"),		/* DOUT */
> +		  SUNXI_FUNCTION(0x5, "sim"),		/* RST */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),		/* EINT6 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "aif2"),		/* DIN */
> +		  SUNXI_FUNCTION(0x3, "i2s0"),		/* DIN */
> +		  SUNXI_FUNCTION(0x5, "sim"),		/* DET */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),		/* EINT7 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x4, "uart0"),		/* TX */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),		/* EINT8 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x4, "uart0"),		/* RX */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),		/* EINT9 */
> +	/* Hole */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "nand0"),		/* NWE */
> +		  SUNXI_FUNCTION(0x4, "spi0")),		/* MOSI */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "nand0"),		/* NALE */
> +		  SUNXI_FUNCTION(0x3, "mmc2"),		/* DS */
> +		  SUNXI_FUNCTION(0x4, "spi0")),		/* MISO */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCLE */
> +		  SUNXI_FUNCTION(0x4, "spi0")),		/* SCK */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCE1 */
> +		  SUNXI_FUNCTION(0x4, "spi0")),		/* CS */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "nand0")),	/* NCE0 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "nand0"),		/* NRE# */
> +		  SUNXI_FUNCTION(0x3, "mmc2")),		/* CLK */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "nand0"),		/* NRB0 */
> +		  SUNXI_FUNCTION(0x3, "mmc2")),		/* CMD */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "nand0")),	/* NRB1 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ0 */
> +		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D0 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ1 */
> +		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D1 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ2 */
> +		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D2 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ3 */
> +		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D3 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ4 */
> +		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D4 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ5 */
> +		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D5 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ6 */
> +		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D6 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQ7 */
> +		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D7 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "nand0"),		/* NDQS */
> +		  SUNXI_FUNCTION(0x3, "mmc2")),		/* RST */
> +	/* Hole */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D2 */
> +		  SUNXI_FUNCTION(0x3, "uart3"),		/* TX */
> +		  SUNXI_FUNCTION(0x4, "spi1"),		/* CS */
> +		  SUNXI_FUNCTION(0x5, "ccir")),		/* CLK */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D3 */
> +		  SUNXI_FUNCTION(0x3, "uart3"),		/* RX */
> +		  SUNXI_FUNCTION(0x4, "spi1"),		/* CLK */
> +		  SUNXI_FUNCTION(0x5, "ccir")),		/* DE */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D4 */
> +		  SUNXI_FUNCTION(0x3, "uart4"),		/* TX */
> +		  SUNXI_FUNCTION(0x4, "spi1"),		/* MOSI */
> +		  SUNXI_FUNCTION(0x5, "ccir")),		/* HSYNC */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D5 */
> +		  SUNXI_FUNCTION(0x3, "uart4"),		/* RX */
> +		  SUNXI_FUNCTION(0x4, "spi1"),		/* MISO */
> +		  SUNXI_FUNCTION(0x5, "ccir")),		/* VSYNC */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D6 */
> +		  SUNXI_FUNCTION(0x3, "uart4"),		/* RTS */
> +		  SUNXI_FUNCTION(0x5, "ccir")),		/* D0 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D7 */
> +		  SUNXI_FUNCTION(0x3, "uart4"),		/* CTS */
> +		  SUNXI_FUNCTION(0x5, "ccir")),		/* D1 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D10 */
> +		  SUNXI_FUNCTION(0x5, "ccir")),		/* D2 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D11 */
> +		  SUNXI_FUNCTION(0x5, "ccir")),		/* D3 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D12 */
> +		  SUNXI_FUNCTION(0x4, "emac"),		/* ERXD3 */
> +		  SUNXI_FUNCTION(0x5, "ccir")),		/* D4 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D13 */
> +		  SUNXI_FUNCTION(0x4, "emac"),		/* ERXD2 */
> +		  SUNXI_FUNCTION(0x5, "ccir")),		/* D5 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D14 */
> +		  SUNXI_FUNCTION(0x4, "emac")),		/* ERXD1 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D15 */
> +		  SUNXI_FUNCTION(0x4, "emac")),		/* ERXD0 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D18 */
> +		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VP0 */
> +		  SUNXI_FUNCTION(0x4, "emac")),		/* ERXCK */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D19 */
> +		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VN0 */
> +		  SUNXI_FUNCTION(0x4, "emac")),		/* ERXCTL */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D20 */
> +		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VP1 */
> +		  SUNXI_FUNCTION(0x4, "emac")),		/* ENULL */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D21 */
> +		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VN1 */
> +		  SUNXI_FUNCTION(0x4, "emac"),		/* ETXD3 */
> +		  SUNXI_FUNCTION(0x5, "ccir")),		/* D6 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D22 */
> +		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VP2 */
> +		  SUNXI_FUNCTION(0x4, "emac"),		/* ETXD2 */
> +		  SUNXI_FUNCTION(0x5, "ccir")),		/* D7 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D23 */
> +		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VN2 */
> +		  SUNXI_FUNCTION(0x4, "emac")),		/* ETXD1 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* CLK */
> +		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VPC */
> +		  SUNXI_FUNCTION(0x4, "emac")),		/* ETXD0 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* DE */
> +		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VNC */
> +		  SUNXI_FUNCTION(0x4, "emac")),		/* ETXCK */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* HSYNC */
> +		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VP3 */
> +		  SUNXI_FUNCTION(0x4, "emac")),		/* ETXCTL */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "lcd0"),		/* VSYNC */
> +		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VN3 */
> +		  SUNXI_FUNCTION(0x4, "emac")),		/* ECLKIN */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "pwm"),		/* PWM0 */
> +		  SUNXI_FUNCTION(0x4, "emac")),		/* EMDC */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x4, "emac")),		/* EMDIO */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out")),
> +	/* Hole */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "csi0"),		/* PCK */
> +		  SUNXI_FUNCTION(0x4, "ts0")),		/* CLK */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "csi0"),		/* CK */
> +		  SUNXI_FUNCTION(0x4, "ts0")),		/* ERR */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "csi0"),		/* HSYNC */
> +		  SUNXI_FUNCTION(0x4, "ts0")),		/* SYNC */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "csi0"),		/* VSYNC */
> +		  SUNXI_FUNCTION(0x4, "ts0")),		/* DVLD */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "csi0"),		/* D0 */
> +		  SUNXI_FUNCTION(0x4, "ts0")),		/* D0 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "csi0"),		/* D1 */
> +		  SUNXI_FUNCTION(0x4, "ts0")),		/* D1 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "csi0"),		/* D2 */
> +		  SUNXI_FUNCTION(0x4, "ts0")),		/* D2 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "csi0"),		/* D3 */
> +		  SUNXI_FUNCTION(0x4, "ts0")),		/* D3 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "csi0"),		/* D4 */
> +		  SUNXI_FUNCTION(0x4, "ts0")),		/* D4 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "csi0"),		/* D5 */
> +		  SUNXI_FUNCTION(0x4, "ts0")),		/* D5 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "csi0"),		/* D6 */
> +		  SUNXI_FUNCTION(0x4, "ts0")),		/* D6 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "csi0"),		/* D7 */
> +		  SUNXI_FUNCTION(0x4, "ts0")),		/* D7 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "csi0")),		/* SCK */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "csi0")),		/* SDA */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "pll"),		/* LOCK_DBG */
> +		  SUNXI_FUNCTION(0x3, "i2c2")),		/* SCK */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x3, "i2c2")),		/* SDA */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out")),
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out")),
> +	/* Hole */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D1 */
> +		  SUNXI_FUNCTION(0x3, "jtag")),		/* MSI */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D0 */
> +		  SUNXI_FUNCTION(0x3, "jtag")),		/* DI1 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "mmc0"),		/* CLK */
> +		  SUNXI_FUNCTION(0x3, "uart0")),	/* TX */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "mmc0"),		/* CMD */
> +		  SUNXI_FUNCTION(0x3, "jtag")),		/* DO1 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D3 */
> +		  SUNXI_FUNCTION(0x4, "uart0")),	/* RX */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D2 */
> +		  SUNXI_FUNCTION(0x3, "jtag")),		/* CK1 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out")),
> +	/* Hole */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "mmc1"),		/* CLK */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),	/* EINT0 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "mmc1"),		/* CMD */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),	/* EINT1 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D0 */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),	/* EINT2 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D1 */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),	/* EINT3 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D2 */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),	/* EINT4 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D3 */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),	/* EINT5 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "uart1"),		/* TX */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),	/* EINT6 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "uart1"),		/* RX */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),	/* EINT7 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "uart1"),		/* RTS */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),	/* EINT8 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "uart1"),		/* CTS */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),	/* EINT9 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "aif3"),		/* SYNC */
> +		  SUNXI_FUNCTION(0x3, "i2s1"),		/* SYNC */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),	/* EINT10 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "aif3"),		/* BCLK */
> +		  SUNXI_FUNCTION(0x3, "i2s1"),		/* BCLK */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),	/* EINT11 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "aif3"),		/* DOUT */
> +		  SUNXI_FUNCTION(0x3, "i2s1"),		/* DOUT */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),	/* EINT12 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "aif3"),		/* DIN */
> +		  SUNXI_FUNCTION(0x3, "i2s1"),		/* DIN */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)),	/* EINT13 */
> +	/* Hole */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "i2c0"),		/* SCK */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),	/* EINT0 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "i2c0"),		/* SDA */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),	/* EINT1 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "i2c1"),		/* SCK */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),	/* EINT2 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "i2c1"),		/* SDA */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),	/* EINT3 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "uart3"),		/* TX */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),	/* EINT4 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "uart3"),		/* RX */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),	/* EINT5 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "uart3"),		/* RTS */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),	/* EINT6 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "uart3"),		/* CTS */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),	/* EINT7 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "owa"),		/* OUT */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),	/* EINT8 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),	/* EINT9 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "mic"),		/* CLK */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)),	/* EINT10 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "mic"),		/* DATA */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)),	/* EINT11 */
> +};
> +
> +static const struct sunxi_pinctrl_desc a64_pinctrl_data = {
> +	.pins = a64_pins,
> +	.npins = ARRAY_SIZE(a64_pins),
> +	.irq_banks = 3,
> +};
> +
> +static int a64_pinctrl_probe(struct platform_device *pdev)
> +{
> +	return sunxi_pinctrl_init(pdev,
> +				  &a64_pinctrl_data);
> +}
> +
> +static const struct of_device_id a64_pinctrl_match[] = {
> +	{ .compatible = "allwinner,a64-pinctrl", },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, a64_pinctrl_match);
> +
> +static struct platform_driver a64_pinctrl_driver = {
> +	.probe	= a64_pinctrl_probe,
> +	.driver	= {
> +		.name		= "a64-pinctrl",
> +		.of_match_table	= a64_pinctrl_match,
> +	},
> +};
> +module_platform_driver(a64_pinctrl_driver);
> +
> +MODULE_AUTHOR("Andre Przywara <andre.przywara@arm.com>");
> +MODULE_DESCRIPTION("Allwinner A64 pinctrl driver");
> +MODULE_LICENSE("GPL");

For the above function names one could also think about using the
existing naming scheme including the SoC family as we do in the
other sunxi pinctrl drivers, but as they are only internal to the
driver, that would really just be a matter of cosmetics :-).

Regards,
Karsten
-- 
Gem. Par. 28 Abs. 4 Bundesdatenschutzgesetz widerspreche ich der Nutzung
sowie der Weitergabe meiner personenbezogenen Daten für Zwecke der
Werbung sowie der Markt- oder Meinungsforschung.

Re: [linux-sunxi] Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC

[Karsten Merker]

Hello,

I by mistake pressed "send" on my previous mail when I intended
to further edit it, so here comes a followup.
I definitely need more coffee ;-).

On Mon, Feb 01, 2016 at 07:27:54PM +0100, Karsten Merker wrote:
> On Mon, Feb 01, 2016 at 05:39:24PM +0000, Andre Przywara wrote:

> > +static const struct sunxi_pinctrl_desc a64_pinctrl_data = {
> > +	.pins = a64_pins,
> > +	.npins = ARRAY_SIZE(a64_pins),
> > +	.irq_banks = 3,
> > +};
> > +
> > +static int a64_pinctrl_probe(struct platform_device *pdev)
> > +{
> > +	return sunxi_pinctrl_init(pdev,
> > +				  &a64_pinctrl_data);
> > +}
> > +
> > +static const struct of_device_id a64_pinctrl_match[] = {
> > +	{ .compatible = "allwinner,a64-pinctrl", },

s/allwinner,a64-pinctrl/allwinner,sun50i-a64-pinctrl/ ?

> > +	{}
> > +};
> > +MODULE_DEVICE_TABLE(of, a64_pinctrl_match);
> > +
> > +static struct platform_driver a64_pinctrl_driver = {
> > +	.probe	= a64_pinctrl_probe,
> > +	.driver	= {
> > +		.name		= "a64-pinctrl",
> > +		.of_match_table	= a64_pinctrl_match,
> > +	},
> > +};
> > +module_platform_driver(a64_pinctrl_driver);
> > +
> > +MODULE_AUTHOR("Andre Przywara <andre.przywara@arm.com>");
> > +MODULE_DESCRIPTION("Allwinner A64 pinctrl driver");
> > +MODULE_LICENSE("GPL");
> 
> For the above function names one could also think about using the

s/function names/variable definitions/

> existing naming scheme including the SoC family as we do in the
> other sunxi pinctrl drivers, but as they are only internal to the
> driver, that would really just be a matter of cosmetics :-).

Regards,
Karsten
-- 
Gem. Par. 28 Abs. 4 Bundesdatenschutzgesetz widerspreche ich der Nutzung
sowie der Weitergabe meiner personenbezogenen Daten für Zwecke der
Werbung sowie der Markt- oder Meinungsforschung.

Re: Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC

[André Przywara]

On 01/02/16 18:45, Karsten Merker wrote:
> Hello,
> 
> I by mistake pressed "send" on my previous mail when I intended
> to further edit it, so here comes a followup.
> I definitely need more coffee ;-).

Or less?  ;-)             vvvvvvvvvv Thinking of twitchy fingers...
> On Mon, Feb 01, 2016 at 07:27:54PM +0100, Karsten Merker wrote:
>> On Mon, Feb 01, 2016 at 05:39:24PM +0000, Andre Przywara wrote:
> 
>>> +static const struct sunxi_pinctrl_desc a64_pinctrl_data = {
>>> +	.pins = a64_pins,
>>> +	.npins = ARRAY_SIZE(a64_pins),
>>> +	.irq_banks = 3,
>>> +};
>>> +
>>> +static int a64_pinctrl_probe(struct platform_device *pdev)
>>> +{
>>> +	return sunxi_pinctrl_init(pdev,
>>> +				  &a64_pinctrl_data);
>>> +}
>>> +
>>> +static const struct of_device_id a64_pinctrl_match[] = {
>>> +	{ .compatible = "allwinner,a64-pinctrl", },
> 
> s/allwinner,a64-pinctrl/allwinner,sun50i-a64-pinctrl/ ?

As mentioned in the other mail, allwinner should be enough to make the
naming unique. Especially as this is about DT namings, which should be
valid outside of the Linux world even.

Cheers,
Andre.

> 
>>> +	{}
>>> +};
>>> +MODULE_DEVICE_TABLE(of, a64_pinctrl_match);
>>> +
>>> +static struct platform_driver a64_pinctrl_driver = {
>>> +	.probe	= a64_pinctrl_probe,
>>> +	.driver	= {
>>> +		.name		= "a64-pinctrl",
>>> +		.of_match_table	= a64_pinctrl_match,
>>> +	},
>>> +};
>>> +module_platform_driver(a64_pinctrl_driver);
>>> +
>>> +MODULE_AUTHOR("Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>");
>>> +MODULE_DESCRIPTION("Allwinner A64 pinctrl driver");
>>> +MODULE_LICENSE("GPL");
>>
>> For the above function names one could also think about using the
> 
> s/function names/variable definitions/
> 
>> existing naming scheme including the SoC family as we do in the
>> other sunxi pinctrl drivers, but as they are only internal to the
>> driver, that would really just be a matter of cosmetics :-).
> 
> Regards,
> Karsten
> 

Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC

[André Przywara]

On 01/02/16 18:27, Karsten Merker wrote:

Hi Karsten,

thank you very much for your feedback!

> On Mon, Feb 01, 2016 at 05:39:24PM +0000, Andre Przywara wrote:
>> Based on the Allwinner A64 user manual and on the previous sunxi
>> pinctrl drivers this introduces the pin multiplex assignments for
>> the ARMv8 Allwinner A64 SoC.
>> Port A is apparently used for the fixed function DRAM controller, so
>> the ports start at B here (the manual mentions "n from 1 to 7", so
>> not starting at 0).
>>
>> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
>> ---
>>  .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
>>  arch/arm64/Kconfig.platforms                       |   1 +
>>  drivers/pinctrl/sunxi/Kconfig                      |   4 +
>>  drivers/pinctrl/sunxi/Makefile                     |   1 +
>>  drivers/pinctrl/sunxi/pinctrl-a64.c                | 606 +++++++++++++++++++++
>>  5 files changed, 613 insertions(+)
>>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-a64.c
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>> index 9213b27..9050002 100644
>> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>> @@ -21,6 +21,7 @@ Required properties:
>>    "allwinner,sun9i-a80-r-pinctrl"
>>    "allwinner,sun8i-a83t-pinctrl"
>>    "allwinner,sun8i-h3-pinctrl"
>> +  "allwinner,a64-pinctrl"
> 
> Hello,
> 
> on all other Allwinner SoCs we use the SoC family as part of the
> compatible, as well as in the names of the Kconfig options. To
> keep things consistent, I would like to propose doing the same on
> Arm64, i.e. using allwinner,sun50i-a64-pinctrl instead of
> allwinner,a64-pinctrl.

Yes, I have been told this already. However I don't like this idea so
much, for the following reasons:
a) It is mostly redundant. The actual SoC (marketing) name is unique,
there is no sun6i-a20 or sun7i-a23.
b) It is not even helpful. If I got Maxime correctly, then the newer
sunxi generation numbers depend on the ARM _cores_ used in the SoC,
which is frankly the least interesting part from a Linux support
perspective. I would see some sense if it would reflect the generation
of IP blocks used, but so it is even more confusing to see that
sun7i-a20 and sun8i-a23 are related, but sun8i-h3 is a completely
different beast. The Allwinner marketing name tells you that, but the
sunxi one does not.
c) It is very confusing for people not dealing with it everyday. Just
because I own a BananaPi I know that the A20 is sun7i, but I am totally
lost when it comes to all the other names. And even now it took me about
a minute to find the appropriate Wiki page which explains part of that
story.
d) Most importantly ;-): It kills TAB completion, unless you know the
sunxi number, which is mostly not true as pointed out in c)

So while I see that just a<somenumber> is not really very specific, I'd
rather do away with current naming scheme for the future. In this
particular case we have the vendor name as a name space identifier
already, so there is no possible confusion with ARM Cortex naming, for
instance.

Also as this is now moving into the arm64 world, I'd like to use the
opportunity to fix things that are not really optimal, the naming is one
of them.

>>  - reg: Should contain the register physical address and length for the
>>    pin controller.
>> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
>> index fc7cf4b..03f0f9d 100644
>> --- a/arch/arm64/Kconfig.platforms
>> +++ b/arch/arm64/Kconfig.platforms
>> @@ -2,6 +2,7 @@ menu "Platform selection"
>>  
>>  config ARCH_SUNXI
>>  	bool "Allwinner sunxi 64-bit SoC Family"
>> +	select PINCTRL_A64
> 
> Same as above, just with the name of the Kconfig option.
> s/PINCTRL_A64/PINCTRL_SUN50I_A64/ ?

I can see the reasoning behind this particular one, as A64 is not very
specific. And indeed I had planned to replace this, but forgot it over
merging all the stuff together. However I'd rather go with the generic
"sunxi" as a stub name (PINCTRL_SUNXI_A64), as the "50" in there is now
completely stupi^Wconfusing and also kills my favorite sun.i regexp ;-)
I can see that the term "sunxi" is a shorthand for Allwinner in Linux,
so it looks reasonable to me to use that.

>>  	select SUNXI_MMC
>>  	help
>>  	  This enables support for Allwinner sunxi based SoCs like the A64.
>> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
>> index f8dbc8b..68873f2 100644
>> --- a/drivers/pinctrl/sunxi/Kconfig
>> +++ b/drivers/pinctrl/sunxi/Kconfig
>> @@ -64,4 +64,8 @@ config PINCTRL_SUN9I_A80_R
>>  	depends on RESET_CONTROLLER
>>  	select PINCTRL_SUNXI_COMMON
>>  
>> +config PINCTRL_A64
> 
> see above
> 
>> +	bool
>> +	select PINCTRL_SUNXI_COMMON
>> +
>>  endif
>> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
>> index ef82f22..e00ccde 100644
>> --- a/drivers/pinctrl/sunxi/Makefile
>> +++ b/drivers/pinctrl/sunxi/Makefile
>> @@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_SUN7I_A20)		+= pinctrl-sun7i-a20.o
>>  obj-$(CONFIG_PINCTRL_SUN8I_A23)		+= pinctrl-sun8i-a23.o
>>  obj-$(CONFIG_PINCTRL_SUN8I_A23_R)	+= pinctrl-sun8i-a23-r.o
>>  obj-$(CONFIG_PINCTRL_SUN8I_A33)		+= pinctrl-sun8i-a33.o
>> +obj-$(CONFIG_PINCTRL_A64)		+= pinctrl-a64.o
> 
> see above

same as above, I'd like to go with pinctrl-sunxi-a64.o.

>>  obj-$(CONFIG_PINCTRL_SUN8I_A83T)	+= pinctrl-sun8i-a83t.o
>>  obj-$(CONFIG_PINCTRL_SUN8I_H3)		+= pinctrl-sun8i-h3.o
>>  obj-$(CONFIG_PINCTRL_SUN9I_A80)		+= pinctrl-sun9i-a80.o
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-a64.c b/drivers/pinctrl/sunxi/pinctrl-a64.c
>> new file mode 100644
>> index 0000000..e72b079
>> --- /dev/null
>> +++ b/drivers/pinctrl/sunxi/pinctrl-a64.c
>> @@ -0,0 +1,606 @@
>> +/*
>> + * Allwinner A64 SoCs pinctrl driver.
>> + *
>> + * Copyright (C) 2016 - ARM Ltd.
>> + * Author: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
>> + *
>> + * Based on pinctrl-sun7i-a20.c, which is:
>> + * Copyright (C) 2014 Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2.  This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/pinctrl/pinctrl.h>
>> +
>> +#include "pinctrl-sunxi.h"
>> +
>> +static const struct sunxi_desc_pin a64_pins[] = {
>> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
>> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
>> +		  SUNXI_FUNCTION(0x1, "gpio_out"),

....

>> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)),	/* EINT11 */
>> +};
>> +
>> +static const struct sunxi_pinctrl_desc a64_pinctrl_data = {
>> +	.pins = a64_pins,
>> +	.npins = ARRAY_SIZE(a64_pins),
>> +	.irq_banks = 3,
>> +};
>> +
>> +static int a64_pinctrl_probe(struct platform_device *pdev)
>> +{
>> +	return sunxi_pinctrl_init(pdev,
>> +				  &a64_pinctrl_data);
>> +}
>> +
>> +static const struct of_device_id a64_pinctrl_match[] = {
>> +	{ .compatible = "allwinner,a64-pinctrl", },
>> +	{}
>> +};
>> +MODULE_DEVICE_TABLE(of, a64_pinctrl_match);
>> +
>> +static struct platform_driver a64_pinctrl_driver = {
>> +	.probe	= a64_pinctrl_probe,
>> +	.driver	= {
>> +		.name		= "a64-pinctrl",
>> +		.of_match_table	= a64_pinctrl_match,
>> +	},
>> +};
>> +module_platform_driver(a64_pinctrl_driver);
>> +
>> +MODULE_AUTHOR("Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>");
>> +MODULE_DESCRIPTION("Allwinner A64 pinctrl driver");
>> +MODULE_LICENSE("GPL");
> 
> For the above function names one could also think about using the
> existing naming scheme including the SoC family as we do in the
> other sunxi pinctrl drivers, but as they are only internal to the
> driver, that would really just be a matter of cosmetics :-).

Indeed ;-) And it is more to type and may potentially break 80 character
lines, so if you don't mind, I keep it that way (or could add a "sunxi_"
if that is really asked for).

Thanks for looking at this and your input!

Cheers,
Andre.

Re: Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC

[Siarhei Siamashka]

On Mon, 1 Feb 2016 22:49:16 +0000
André Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org> wrote:

> On 01/02/16 18:27, Karsten Merker wrote:
> 
> Hi Karsten,
> 
> thank you very much for your feedback!
> 
> > On Mon, Feb 01, 2016 at 05:39:24PM +0000, Andre Przywara wrote:  
> >> Based on the Allwinner A64 user manual and on the previous sunxi
> >> pinctrl drivers this introduces the pin multiplex assignments for
> >> the ARMv8 Allwinner A64 SoC.
> >> Port A is apparently used for the fixed function DRAM controller, so
> >> the ports start at B here (the manual mentions "n from 1 to 7", so
> >> not starting at 0).
> >>
> >> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
> >> ---
> >>  .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
> >>  arch/arm64/Kconfig.platforms                       |   1 +
> >>  drivers/pinctrl/sunxi/Kconfig                      |   4 +
> >>  drivers/pinctrl/sunxi/Makefile                     |   1 +
> >>  drivers/pinctrl/sunxi/pinctrl-a64.c                | 606 +++++++++++++++++++++
> >>  5 files changed, 613 insertions(+)
> >>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-a64.c
> >>
> >> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> >> index 9213b27..9050002 100644
> >> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> >> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> >> @@ -21,6 +21,7 @@ Required properties:
> >>    "allwinner,sun9i-a80-r-pinctrl"
> >>    "allwinner,sun8i-a83t-pinctrl"
> >>    "allwinner,sun8i-h3-pinctrl"
> >> +  "allwinner,a64-pinctrl"  
> > 
> > Hello,
> > 
> > on all other Allwinner SoCs we use the SoC family as part of the
> > compatible, as well as in the names of the Kconfig options. To
> > keep things consistent, I would like to propose doing the same on
> > Arm64, i.e. using allwinner,sun50i-a64-pinctrl instead of
> > allwinner,a64-pinctrl.  
> 
> Yes, I have been told this already. However I don't like this idea so
> much, for the following reasons:
> a) It is mostly redundant. The actual SoC (marketing) name is unique,
> there is no sun6i-a20 or sun7i-a23.
> b) It is not even helpful. If I got Maxime correctly, then the newer
> sunxi generation numbers depend on the ARM _cores_ used in the SoC,
> which is frankly the least interesting part from a Linux support
> perspective. I would see some sense if it would reflect the generation
> of IP blocks used, but so it is even more confusing to see that
> sun7i-a20 and sun8i-a23 are related, but sun8i-h3 is a completely
> different beast. The Allwinner marketing name tells you that, but the
> sunxi one does not.
> c) It is very confusing for people not dealing with it everyday. Just
> because I own a BananaPi I know that the A20 is sun7i, but I am totally
> lost when it comes to all the other names. And even now it took me about
> a minute to find the appropriate Wiki page which explains part of that
> story.
> d) Most importantly ;-): It kills TAB completion, unless you know the
> sunxi number, which is mostly not true as pointed out in c)
> 
> So while I see that just a<somenumber> is not really very specific, I'd
> rather do away with current naming scheme for the future. In this
> particular case we have the vendor name as a name space identifier
> already, so there is no possible confusion with ARM Cortex naming, for
> instance.
> 
> Also as this is now moving into the arm64 world, I'd like to use the
> opportunity to fix things that are not really optimal, the naming is one
> of them.

One of the problems is that A64 name is not unique. We have reasons
to believe that there are also H64 and R18 out there using exactly
the same die, but possibly available in different packaging (a different
ball grid pitch? or maybe a different set of peripherals routed to the
outside?). Early prototypes of the Pine64 board were using Allwinner R18
and the Jide Remix Mini HTPC box is using Allwinner H64.

The bootloader sources from Allwinner are also referring to A64 as
AW1689, which makes some sense because it is the chip id number that
is accessible for runtime identification via reading the SRAM_VER_REG
hardware register:

    http://linux-sunxi.org/SRAM_Controller_Register_Guide#SRAM_VER_REG

So would it be a good idea to use "aw1689" as a compatible property
in the DT instead of "a64"? Or maybe have "aw1689-a64" and
"aw1689-h64", which would be similar to the existing "sun5i-a13"
and "sun5i-a10s" naming convention?

-- 
Best regards,
Siarhei Siamashka

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Re: [linux-sunxi] Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC

[Andre Przywara]

Hi,

On 02/02/16 01:58, Siarhei Siamashka wrote:
> On Mon, 1 Feb 2016 22:49:16 +0000
> André Przywara <andre.przywara@arm.com> wrote:
> 
>> On 01/02/16 18:27, Karsten Merker wrote:
>>
>> Hi Karsten,
>>
>> thank you very much for your feedback!
>>
>>> On Mon, Feb 01, 2016 at 05:39:24PM +0000, Andre Przywara wrote:  
>>>> Based on the Allwinner A64 user manual and on the previous sunxi
>>>> pinctrl drivers this introduces the pin multiplex assignments for
>>>> the ARMv8 Allwinner A64 SoC.
>>>> Port A is apparently used for the fixed function DRAM controller, so
>>>> the ports start at B here (the manual mentions "n from 1 to 7", so
>>>> not starting at 0).
>>>>
>>>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>>>> ---
>>>>  .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
>>>>  arch/arm64/Kconfig.platforms                       |   1 +
>>>>  drivers/pinctrl/sunxi/Kconfig                      |   4 +
>>>>  drivers/pinctrl/sunxi/Makefile                     |   1 +
>>>>  drivers/pinctrl/sunxi/pinctrl-a64.c                | 606 +++++++++++++++++++++
>>>>  5 files changed, 613 insertions(+)
>>>>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-a64.c
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>>>> index 9213b27..9050002 100644
>>>> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>>>> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>>>> @@ -21,6 +21,7 @@ Required properties:
>>>>    "allwinner,sun9i-a80-r-pinctrl"
>>>>    "allwinner,sun8i-a83t-pinctrl"
>>>>    "allwinner,sun8i-h3-pinctrl"
>>>> +  "allwinner,a64-pinctrl"  
>>>
>>> Hello,
>>>
>>> on all other Allwinner SoCs we use the SoC family as part of the
>>> compatible, as well as in the names of the Kconfig options. To
>>> keep things consistent, I would like to propose doing the same on
>>> Arm64, i.e. using allwinner,sun50i-a64-pinctrl instead of
>>> allwinner,a64-pinctrl.  
>>
>> Yes, I have been told this already. However I don't like this idea so
>> much, for the following reasons:
>> a) It is mostly redundant. The actual SoC (marketing) name is unique,
>> there is no sun6i-a20 or sun7i-a23.
>> b) It is not even helpful. If I got Maxime correctly, then the newer
>> sunxi generation numbers depend on the ARM _cores_ used in the SoC,
>> which is frankly the least interesting part from a Linux support
>> perspective. I would see some sense if it would reflect the generation
>> of IP blocks used, but so it is even more confusing to see that
>> sun7i-a20 and sun8i-a23 are related, but sun8i-h3 is a completely
>> different beast. The Allwinner marketing name tells you that, but the
>> sunxi one does not.
>> c) It is very confusing for people not dealing with it everyday. Just
>> because I own a BananaPi I know that the A20 is sun7i, but I am totally
>> lost when it comes to all the other names. And even now it took me about
>> a minute to find the appropriate Wiki page which explains part of that
>> story.
>> d) Most importantly ;-): It kills TAB completion, unless you know the
>> sunxi number, which is mostly not true as pointed out in c)
>>
>> So while I see that just a<somenumber> is not really very specific, I'd
>> rather do away with current naming scheme for the future. In this
>> particular case we have the vendor name as a name space identifier
>> already, so there is no possible confusion with ARM Cortex naming, for
>> instance.
>>
>> Also as this is now moving into the arm64 world, I'd like to use the
>> opportunity to fix things that are not really optimal, the naming is one
>> of them.
> 
> One of the problems is that A64 name is not unique. We have reasons
> to believe that there are also H64 and R18 out there using exactly
> the same die, but possibly available in different packaging (a different
> ball grid pitch? or maybe a different set of peripherals routed to the
> outside?). Early prototypes of the Pine64 board were using Allwinner R18
> and the Jide Remix Mini HTPC box is using Allwinner H64.

So if the differences are actually hidden from software, why would we
care? See below for an example on using DT to cover this.

> The bootloader sources from Allwinner are also referring to A64 as
> AW1689, which makes some sense because it is the chip id number that
> is accessible for runtime identification via reading the SRAM_VER_REG
> hardware register:
> 
>     http://linux-sunxi.org/SRAM_Controller_Register_Guide#SRAM_VER_REG
> 
> So would it be a good idea to use "aw1689" as a compatible property
> in the DT instead of "a64"? Or maybe have "aw1689-a64" and
> "aw1689-h64", which would be similar to the existing "sun5i-a13"
> and "sun5i-a10s" naming convention?

I would be fine with that if it really reflects something in the
hardware. And I like it more than the rather arbitrary sun50i name. But
on the other hand it seems to be completely unknown so far (Google just
turns up this email and your sunxi-fel setup, basically). So I am not
sure we should introduce yet another naming scheme.

So looking at the compatible definition in the DT, this looks like a
perfect example of a fall-back name to me:
For the Pine64 we use "allwinner,a64", any other board could use say a:
"allwinner,h64", "allwinner,a64" compatible naming.
So as long as we don't need any h64 specifics, going with the A64
support code is fine. Should later the need arise to fix something for
the H64 only, we can add this easily and be covered automatically.

FWIW, I just have received this Remix Mini PC thing, which I ordered to
see what's with the H64 and to make sure the SoC/board abstraction is
right. So let me see what this version register looks like there and how
it behaves with the proposed kernel patches (should I be able to hack it).

Cheers,
Andre.
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Re: Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 4888 bytes --]

Hi,

On Tue, Feb 02, 2016 at 03:58:52AM +0200, Siarhei Siamashka wrote:
> > > On Mon, Feb 01, 2016 at 05:39:24PM +0000, Andre Przywara wrote:  
> > >> Based on the Allwinner A64 user manual and on the previous sunxi
> > >> pinctrl drivers this introduces the pin multiplex assignments for
> > >> the ARMv8 Allwinner A64 SoC.
> > >> Port A is apparently used for the fixed function DRAM controller, so
> > >> the ports start at B here (the manual mentions "n from 1 to 7", so
> > >> not starting at 0).
> > >>
> > >> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
> > >> ---
> > >>  .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
> > >>  arch/arm64/Kconfig.platforms                       |   1 +
> > >>  drivers/pinctrl/sunxi/Kconfig                      |   4 +
> > >>  drivers/pinctrl/sunxi/Makefile                     |   1 +
> > >>  drivers/pinctrl/sunxi/pinctrl-a64.c                | 606 +++++++++++++++++++++
> > >>  5 files changed, 613 insertions(+)
> > >>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-a64.c
> > >>
> > >> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> > >> index 9213b27..9050002 100644
> > >> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> > >> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> > >> @@ -21,6 +21,7 @@ Required properties:
> > >>    "allwinner,sun9i-a80-r-pinctrl"
> > >>    "allwinner,sun8i-a83t-pinctrl"
> > >>    "allwinner,sun8i-h3-pinctrl"
> > >> +  "allwinner,a64-pinctrl"  
> > > 
> > > Hello,
> > > 
> > > on all other Allwinner SoCs we use the SoC family as part of the
> > > compatible, as well as in the names of the Kconfig options. To
> > > keep things consistent, I would like to propose doing the same on
> > > Arm64, i.e. using allwinner,sun50i-a64-pinctrl instead of
> > > allwinner,a64-pinctrl.  
> > 
> > Yes, I have been told this already. However I don't like this idea so
> > much, for the following reasons:
> > a) It is mostly redundant. The actual SoC (marketing) name is unique,
> > there is no sun6i-a20 or sun7i-a23.
> > b) It is not even helpful. If I got Maxime correctly, then the newer
> > sunxi generation numbers depend on the ARM _cores_ used in the SoC,
> > which is frankly the least interesting part from a Linux support
> > perspective. I would see some sense if it would reflect the generation
> > of IP blocks used, but so it is even more confusing to see that
> > sun7i-a20 and sun8i-a23 are related, but sun8i-h3 is a completely
> > different beast. The Allwinner marketing name tells you that, but the
> > sunxi one does not.
> > c) It is very confusing for people not dealing with it everyday. Just
> > because I own a BananaPi I know that the A20 is sun7i, but I am totally
> > lost when it comes to all the other names. And even now it took me about
> > a minute to find the appropriate Wiki page which explains part of that
> > story.
> > d) Most importantly ;-): It kills TAB completion, unless you know the
> > sunxi number, which is mostly not true as pointed out in c)
> > 
> > So while I see that just a<somenumber> is not really very specific, I'd
> > rather do away with current naming scheme for the future. In this
> > particular case we have the vendor name as a name space identifier
> > already, so there is no possible confusion with ARM Cortex naming, for
> > instance.
> > 
> > Also as this is now moving into the arm64 world, I'd like to use the
> > opportunity to fix things that are not really optimal, the naming is one
> > of them.
> 
> One of the problems is that A64 name is not unique. We have reasons
> to believe that there are also H64 and R18 out there using exactly
> the same die, but possibly available in different packaging (a different
> ball grid pitch? or maybe a different set of peripherals routed to the
> outside?). Early prototypes of the Pine64 board were using Allwinner R18
> and the Jide Remix Mini HTPC box is using Allwinner H64.
> 
> The bootloader sources from Allwinner are also referring to A64 as
> AW1689, which makes some sense because it is the chip id number that
> is accessible for runtime identification via reading the SRAM_VER_REG
> hardware register:
> 
>     http://linux-sunxi.org/SRAM_Controller_Register_Guide#SRAM_VER_REG
> 
> So would it be a good idea to use "aw1689" as a compatible property
> in the DT instead of "a64"? Or maybe have "aw1689-a64" and
> "aw1689-h64", which would be similar to the existing "sun5i-a13"
> and "sun5i-a10s" naming convention?

If someone cannot find out the family name that is documented on
several places, I'm not sure he'll find the obscure, internal code
name.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 4678 bytes --]

Hi Andre,

On Mon, Feb 01, 2016 at 10:49:16PM +0000, André Przywara wrote:
> On 01/02/16 18:27, Karsten Merker wrote:
> 
> Hi Karsten,
> 
> thank you very much for your feedback!
> 
> > On Mon, Feb 01, 2016 at 05:39:24PM +0000, Andre Przywara wrote:
> >> Based on the Allwinner A64 user manual and on the previous sunxi
> >> pinctrl drivers this introduces the pin multiplex assignments for
> >> the ARMv8 Allwinner A64 SoC.
> >> Port A is apparently used for the fixed function DRAM controller, so
> >> the ports start at B here (the manual mentions "n from 1 to 7", so
> >> not starting at 0).
> >>
> >> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
> >> ---
> >>  .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
> >>  arch/arm64/Kconfig.platforms                       |   1 +
> >>  drivers/pinctrl/sunxi/Kconfig                      |   4 +
> >>  drivers/pinctrl/sunxi/Makefile                     |   1 +
> >>  drivers/pinctrl/sunxi/pinctrl-a64.c                | 606 +++++++++++++++++++++
> >>  5 files changed, 613 insertions(+)
> >>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-a64.c
> >>
> >> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> >> index 9213b27..9050002 100644
> >> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> >> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> >> @@ -21,6 +21,7 @@ Required properties:
> >>    "allwinner,sun9i-a80-r-pinctrl"
> >>    "allwinner,sun8i-a83t-pinctrl"
> >>    "allwinner,sun8i-h3-pinctrl"
> >> +  "allwinner,a64-pinctrl"
> > 
> > Hello,
> > 
> > on all other Allwinner SoCs we use the SoC family as part of the
> > compatible, as well as in the names of the Kconfig options. To
> > keep things consistent, I would like to propose doing the same on
> > Arm64, i.e. using allwinner,sun50i-a64-pinctrl instead of
> > allwinner,a64-pinctrl.
> 
> Yes, I have been told this already. However I don't like this idea so
> much, for the following reasons:
> a) It is mostly redundant. The actual SoC (marketing) name is unique,
> there is no sun6i-a20 or sun7i-a23.

At the same time, the family name is mostly valid too.

We do share some DTSI across some SoCs already by their family name
(sun5i.dtsi for the A10s/A13/R8, sun8i-a23-a33.dtsi for the A23 and
A33, etc.)

> b) It is not even helpful. If I got Maxime correctly, then the newer
> sunxi generation numbers depend on the ARM _cores_ used in the SoC,
> which is frankly the least interesting part from a Linux support
> perspective. I would see some sense if it would reflect the generation
> of IP blocks used, but so it is even more confusing to see that
> sun7i-a20 and sun8i-a23 are related, but sun8i-h3 is a completely
> different beast. The Allwinner marketing name tells you that, but the
> sunxi one does not.

The opposite can be said too.

The A31 is quite different from the A33, while the A83 is much closer
to the H3 than it is to the A80. Their marketing scheme is messy. In
all aspects. We have a scheme that worked, I'd really like to stick
with it.

> c) It is very confusing for people not dealing with it everyday. Just
> because I own a BananaPi I know that the A20 is sun7i, but I am totally
> lost when it comes to all the other names. And even now it took me about
> a minute to find the appropriate Wiki page which explains part of that
> story.
> d) Most importantly ;-): It kills TAB completion, unless you know the
> sunxi number, which is mostly not true as pointed out in c)

Both of these are true, but are about the DT filenames, and not the
compatibles. I'd agree with you on this one now that we have
per-vendor subfolders in boot/dts, but it was not the case before, and
I'm pretty sure that to anyone that is not aware of the Allwinner SoCs
names, having an A<number>.dtsi in arch/arm/boot/dts, it would be
about a Cortex-A<number>, and definitely not an SoC from some random
vendor.

So, droping it in the filenames, why not. But I'd really like to keep
the same compatible scheme.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC

[Chen-Yu Tsai]

On Tue, Feb 2, 2016 at 6:00 PM, Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> Hi Andre,
>
> On Mon, Feb 01, 2016 at 10:49:16PM +0000, André Przywara wrote:
>> On 01/02/16 18:27, Karsten Merker wrote:
>>
>> Hi Karsten,
>>
>> thank you very much for your feedback!
>>
>> > On Mon, Feb 01, 2016 at 05:39:24PM +0000, Andre Przywara wrote:
>> >> Based on the Allwinner A64 user manual and on the previous sunxi
>> >> pinctrl drivers this introduces the pin multiplex assignments for
>> >> the ARMv8 Allwinner A64 SoC.
>> >> Port A is apparently used for the fixed function DRAM controller, so
>> >> the ports start at B here (the manual mentions "n from 1 to 7", so
>> >> not starting at 0).
>> >>
>> >> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
>> >> ---
>> >>  .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
>> >>  arch/arm64/Kconfig.platforms                       |   1 +
>> >>  drivers/pinctrl/sunxi/Kconfig                      |   4 +
>> >>  drivers/pinctrl/sunxi/Makefile                     |   1 +
>> >>  drivers/pinctrl/sunxi/pinctrl-a64.c                | 606 +++++++++++++++++++++
>> >>  5 files changed, 613 insertions(+)
>> >>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-a64.c
>> >>
>> >> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>> >> index 9213b27..9050002 100644
>> >> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>> >> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>> >> @@ -21,6 +21,7 @@ Required properties:
>> >>    "allwinner,sun9i-a80-r-pinctrl"
>> >>    "allwinner,sun8i-a83t-pinctrl"
>> >>    "allwinner,sun8i-h3-pinctrl"
>> >> +  "allwinner,a64-pinctrl"
>> >
>> > Hello,
>> >
>> > on all other Allwinner SoCs we use the SoC family as part of the
>> > compatible, as well as in the names of the Kconfig options. To
>> > keep things consistent, I would like to propose doing the same on
>> > Arm64, i.e. using allwinner,sun50i-a64-pinctrl instead of
>> > allwinner,a64-pinctrl.
>>
>> Yes, I have been told this already. However I don't like this idea so
>> much, for the following reasons:
>> a) It is mostly redundant. The actual SoC (marketing) name is unique,
>> there is no sun6i-a20 or sun7i-a23.
>
> At the same time, the family name is mostly valid too.
>
> We do share some DTSI across some SoCs already by their family name
> (sun5i.dtsi for the A10s/A13/R8, sun8i-a23-a33.dtsi for the A23 and
> A33, etc.)
>
>> b) It is not even helpful. If I got Maxime correctly, then the newer
>> sunxi generation numbers depend on the ARM _cores_ used in the SoC,
>> which is frankly the least interesting part from a Linux support
>> perspective. I would see some sense if it would reflect the generation
>> of IP blocks used, but so it is even more confusing to see that
>> sun7i-a20 and sun8i-a23 are related, but sun8i-h3 is a completely
>> different beast. The Allwinner marketing name tells you that, but the
>> sunxi one does not.
>
> The opposite can be said too.
>
> The A31 is quite different from the A33, while the A83 is much closer
> to the H3 than it is to the A80. Their marketing scheme is messy. In
> all aspects. We have a scheme that worked, I'd really like to stick
> with it.
>
>> c) It is very confusing for people not dealing with it everyday. Just
>> because I own a BananaPi I know that the A20 is sun7i, but I am totally
>> lost when it comes to all the other names. And even now it took me about
>> a minute to find the appropriate Wiki page which explains part of that
>> story.
>> d) Most importantly ;-): It kills TAB completion, unless you know the
>> sunxi number, which is mostly not true as pointed out in c)
>
> Both of these are true, but are about the DT filenames, and not the
> compatibles. I'd agree with you on this one now that we have
> per-vendor subfolders in boot/dts, but it was not the case before, and
> I'm pretty sure that to anyone that is not aware of the Allwinner SoCs
> names, having an A<number>.dtsi in arch/arm/boot/dts, it would be
> about a Cortex-A<number>, and definitely not an SoC from some random
> vendor.
>
> So, droping it in the filenames, why not. But I'd really like to keep
> the same compatible scheme.

If we do end up dropping it from the filenames, can you (André) update
MAINTAINERS to add "arch/arm64/boot/dts/sunxi/" to the sunxi entry?

Thanks.
ChenYu

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Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC

[Andre Przywara]

Hi,

On 02/02/16 10:00, Maxime Ripard wrote:
> Hi Andre,
> 
> On Mon, Feb 01, 2016 at 10:49:16PM +0000, André Przywara wrote:
>> On 01/02/16 18:27, Karsten Merker wrote:
>>
>> Hi Karsten,
>>
>> thank you very much for your feedback!
>>
>>> On Mon, Feb 01, 2016 at 05:39:24PM +0000, Andre Przywara wrote:
>>>> Based on the Allwinner A64 user manual and on the previous sunxi
>>>> pinctrl drivers this introduces the pin multiplex assignments for
>>>> the ARMv8 Allwinner A64 SoC.
>>>> Port A is apparently used for the fixed function DRAM controller, so
>>>> the ports start at B here (the manual mentions "n from 1 to 7", so
>>>> not starting at 0).
>>>>
>>>> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
>>>> ---
>>>>  .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
>>>>  arch/arm64/Kconfig.platforms                       |   1 +
>>>>  drivers/pinctrl/sunxi/Kconfig                      |   4 +
>>>>  drivers/pinctrl/sunxi/Makefile                     |   1 +
>>>>  drivers/pinctrl/sunxi/pinctrl-a64.c                | 606 +++++++++++++++++++++
>>>>  5 files changed, 613 insertions(+)
>>>>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-a64.c
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>>>> index 9213b27..9050002 100644
>>>> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>>>> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>>>> @@ -21,6 +21,7 @@ Required properties:
>>>>    "allwinner,sun9i-a80-r-pinctrl"
>>>>    "allwinner,sun8i-a83t-pinctrl"
>>>>    "allwinner,sun8i-h3-pinctrl"
>>>> +  "allwinner,a64-pinctrl"
>>>
>>> Hello,
>>>
>>> on all other Allwinner SoCs we use the SoC family as part of the
>>> compatible, as well as in the names of the Kconfig options. To
>>> keep things consistent, I would like to propose doing the same on
>>> Arm64, i.e. using allwinner,sun50i-a64-pinctrl instead of
>>> allwinner,a64-pinctrl.
>>
>> Yes, I have been told this already. However I don't like this idea so
>> much, for the following reasons:
>> a) It is mostly redundant. The actual SoC (marketing) name is unique,
>> there is no sun6i-a20 or sun7i-a23.
> 
> At the same time, the family name is mostly valid too.
> 
> We do share some DTSI across some SoCs already by their family name
> (sun5i.dtsi for the A10s/A13/R8, sun8i-a23-a33.dtsi for the A23 and
> A33, etc.)
> 
>> b) It is not even helpful. If I got Maxime correctly, then the newer
>> sunxi generation numbers depend on the ARM _cores_ used in the SoC,
>> which is frankly the least interesting part from a Linux support
>> perspective. I would see some sense if it would reflect the generation
>> of IP blocks used, but so it is even more confusing to see that
>> sun7i-a20 and sun8i-a23 are related, but sun8i-h3 is a completely
>> different beast. The Allwinner marketing name tells you that, but the
>> sunxi one does not.
> 
> The opposite can be said too.
> 
> The A31 is quite different from the A33, while the A83 is much closer
> to the H3 than it is to the A80. Their marketing scheme is messy. In
> all aspects. We have a scheme that worked, I'd really like to stick
> with it.

But also H3 and A64 are closely related, still having a totally
different sunxi name.
I guess we could give examples and counter-examples for hours, and just
making it possible to have two contradicting rationales lets me think
this whole naming scheme is inconsistent ;-)
I see that it may have fulfilled a purpose in the past (sun3i-sun7i,
maybe sun8i), but I am not very happy with proliferating this into the
(arm64) future.
Allwinner A<something> is a perfectly google-able and well understood
naming, also unique. So why add some mysterious sun{4,5,6,7,8,9,50}i to it?
So I will amend identifiers/filenames where the name was just A64,
without any Allwinner reference (like in the pinctrl driver). I am in
for using sunxi as a shorthand for Allwinner, since this is a) shorter,
b) is already all over the kernel and c) doesn't give direct credit to a
company that apparently doesn't care ;-)

>> c) It is very confusing for people not dealing with it everyday. Just
>> because I own a BananaPi I know that the A20 is sun7i, but I am totally
>> lost when it comes to all the other names. And even now it took me about
>> a minute to find the appropriate Wiki page which explains part of that
>> story.
>> d) Most importantly ;-): It kills TAB completion, unless you know the
>> sunxi number, which is mostly not true as pointed out in c)
> 
> Both of these are true, but are about the DT filenames, and not the
> compatibles. I'd agree with you on this one now that we have
> per-vendor subfolders in boot/dts, but it was not the case before, and
> I'm pretty sure that to anyone that is not aware of the Allwinner SoCs
> names, having an A<number>.dtsi in arch/arm/boot/dts, it would be
> about a Cortex-A<number>, and definitely not an SoC from some random
> vendor.

I completely agree on that, but this is in
arch/arm64/boot/dts/allwinner, so it's pretty unique. Other vendors in
there seem to think the same. I also see that just an "a" as a prefix is
pretty short, so should we go with "aw" instead?
But actually I would just leave it as it is.

> So, droping it in the filenames, why not. But I'd really like to keep
> the same compatible scheme.

And I still don't get this: in the DT compatible scheme we always have a
vendor prefix, so allwinner,a64 is surely not a mysterious ARM Ltd. core
or a new Apple SoC. Instead it is the A64 from Allwinner, full stop. So
why should we add an arbitrary and confusing sun50i naming to it (when
it actually should be more like "sun8i-a64").

Cheers,
Andre.
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Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 941 bytes --]

Hi Andre,

On Tue, Feb 02, 2016 at 04:53:58PM +0000, Andre Przywara wrote:
> > So, droping it in the filenames, why not. But I'd really like to keep
> > the same compatible scheme.
> 
> And I still don't get this: in the DT compatible scheme we always have a
> vendor prefix, so allwinner,a64 is surely not a mysterious ARM Ltd. core
> or a new Apple SoC. Instead it is the A64 from Allwinner, full stop. So
> why should we add an arbitrary and confusing sun50i naming to it (when
> it actually should be more like "sun8i-a64").

I don't decide on their marketing names. And I know you want to start
anew with the arm64 SoCs, but the truth is, you don't. Most of the
compatibles in the DTSI are from earlier SoCs, and we have to keep
that legacy and remain consistent with it. With all the good and bad
things a legacy imply.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC

[Rob Herring]

On Thu, Feb 04, 2016 at 05:51:51PM +0100, Maxime Ripard wrote:
> Hi Andre,
> 
> On Tue, Feb 02, 2016 at 04:53:58PM +0000, Andre Przywara wrote:
> > > So, droping it in the filenames, why not. But I'd really like to keep
> > > the same compatible scheme.
> > 
> > And I still don't get this: in the DT compatible scheme we always have a
> > vendor prefix, so allwinner,a64 is surely not a mysterious ARM Ltd. core
> > or a new Apple SoC. Instead it is the A64 from Allwinner, full stop. So
> > why should we add an arbitrary and confusing sun50i naming to it (when
> > it actually should be more like "sun8i-a64").
> 
> I don't decide on their marketing names. And I know you want to start
> anew with the arm64 SoCs, but the truth is, you don't. Most of the
> compatibles in the DTSI are from earlier SoCs, and we have to keep
> that legacy and remain consistent with it. With all the good and bad
> things a legacy imply.

I have to agree. Unless there is some agreement to move to another 
naming scheme, then just follow the same pattern. If sunXi is just a 
made up name outside of Allwinner to provide some logical grouping of 
SoCs, then yes, that probably should not have been done.

Rob

Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC

[Andre Przywara]

Hi,

On 08/02/16 15:54, Rob Herring wrote:
> On Thu, Feb 04, 2016 at 05:51:51PM +0100, Maxime Ripard wrote:
>> Hi Andre,
>>
>> On Tue, Feb 02, 2016 at 04:53:58PM +0000, Andre Przywara wrote:
>>>> So, droping it in the filenames, why not. But I'd really like to keep
>>>> the same compatible scheme.
>>>
>>> And I still don't get this: in the DT compatible scheme we always have a
>>> vendor prefix, so allwinner,a64 is surely not a mysterious ARM Ltd. core
>>> or a new Apple SoC. Instead it is the A64 from Allwinner, full stop. So
>>> why should we add an arbitrary and confusing sun50i naming to it (when
>>> it actually should be more like "sun8i-a64").
>>
>> I don't decide on their marketing names. And I know you want to start
>> anew with the arm64 SoCs, but the truth is, you don't. Most of the
>> compatibles in the DTSI are from earlier SoCs, and we have to keep
>> that legacy and remain consistent with it. With all the good and bad
>> things a legacy imply.
> 
> I have to agree. Unless there is some agreement to move to another 
> naming scheme, then just follow the same pattern. If sunXi is just a 
> made up name outside of Allwinner to provide some logical grouping of 
> SoCs, then yes, that probably should not have been done.

So I still don't like it, but will not waste my time or energy on that
front.

Maxime, do you want "allwinner,sun50i-a64" or would
"allwinner,sunxi-a64" be OK as well?

Cheers,
Andre.
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Re: [PATCH 05/11] drivers: pinctrl: add driver for Allwinner A64 SoC

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1695 bytes --]

On Mon, Feb 08, 2016 at 03:58:18PM +0000, Andre Przywara wrote:
> Hi,
> 
> On 08/02/16 15:54, Rob Herring wrote:
> > On Thu, Feb 04, 2016 at 05:51:51PM +0100, Maxime Ripard wrote:
> >> Hi Andre,
> >>
> >> On Tue, Feb 02, 2016 at 04:53:58PM +0000, Andre Przywara wrote:
> >>>> So, droping it in the filenames, why not. But I'd really like to keep
> >>>> the same compatible scheme.
> >>>
> >>> And I still don't get this: in the DT compatible scheme we always have a
> >>> vendor prefix, so allwinner,a64 is surely not a mysterious ARM Ltd. core
> >>> or a new Apple SoC. Instead it is the A64 from Allwinner, full stop. So
> >>> why should we add an arbitrary and confusing sun50i naming to it (when
> >>> it actually should be more like "sun8i-a64").
> >>
> >> I don't decide on their marketing names. And I know you want to start
> >> anew with the arm64 SoCs, but the truth is, you don't. Most of the
> >> compatibles in the DTSI are from earlier SoCs, and we have to keep
> >> that legacy and remain consistent with it. With all the good and bad
> >> things a legacy imply.
> > 
> > I have to agree. Unless there is some agreement to move to another 
> > naming scheme, then just follow the same pattern. If sunXi is just a 
> > made up name outside of Allwinner to provide some logical grouping of 
> > SoCs, then yes, that probably should not have been done.
> 
> So I still don't like it, but will not waste my time or energy on that
> front.
> 
> Maxime, do you want "allwinner,sun50i-a64" or would
> "allwinner,sunxi-a64" be OK as well?

The former will be fine.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 07/11] clk: sunxi: add generic allwinner,sunxi name

[Andre Przywara]

The only difference between the different compatible matches at the
end of clk-sunxi.c are the critical clocks. Two SoCs get away so far
without any, so there is no reason to enumerate those SoCs in here
explicitly, though we have to keep them in for compatibility reasons.

Rename the init function to highlight this generic feature and add a
new, generic DT compatible string which can be used as a fallback value
in the future should a particular SoC don't need any special treatment.

Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
---
 Documentation/devicetree/bindings/arm/sunxi.txt |  4 ++++
 drivers/clk/sunxi/clk-sunxi.c                   | 14 ++++++--------
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
index 7e79fcc..980e065 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,3 +14,7 @@ using one of the following compatible strings:
   allwinner,sun8i-a83t
   allwinner,sun8i-h3
   allwinner,sun9i-a80
+
+For Allwinner SoCs without any specific needs the generic fallback value of:
+  allwinner,sunxi
+can be used.
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index e460a6b..efcce85 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -1052,14 +1052,12 @@ CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
 CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
 CLK_OF_DECLARE(sun8i_h3_clk_init, "allwinner,sun8i-h3", sun6i_init_clocks);
 
-static void __init sun8i_a83t_init_clocks(struct device_node *node)
+static void __init sunxi_generic_init_clocks(struct device_node *node)
 {
 	sunxi_init_clocks(NULL, 0);
 }
-CLK_OF_DECLARE(sun8i_a83t_clk_init, "allwinner,sun8i-a83t", sun8i_a83t_init_clocks);
-
-static void __init sun9i_init_clocks(struct device_node *node)
-{
-	sunxi_init_clocks(NULL, 0);
-}
-CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80", sun9i_init_clocks);
+CLK_OF_DECLARE(sun8i_a83t_clk_init, "allwinner,sun8i-a83t",
+	       sunxi_generic_init_clocks);
+CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80",
+	       sunxi_generic_init_clocks);
+CLK_OF_DECLARE(sunxi_clk_init, "allwinner,sunxi", sunxi_generic_init_clocks);
-- 
2.6.4

Re: [PATCH 07/11] clk: sunxi: add generic allwinner,sunxi name

[Rob Herring]

On Mon, Feb 01, 2016 at 05:39:26PM +0000, Andre Przywara wrote:
> The only difference between the different compatible matches at the
> end of clk-sunxi.c are the critical clocks. Two SoCs get away so far
> without any, so there is no reason to enumerate those SoCs in here
> explicitly, though we have to keep them in for compatibility reasons.
> 
> Rename the init function to highlight this generic feature and add a
> new, generic DT compatible string which can be used as a fallback value
> in the future should a particular SoC don't need any special treatment.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  Documentation/devicetree/bindings/arm/sunxi.txt |  4 ++++
>  drivers/clk/sunxi/clk-sunxi.c                   | 14 ++++++--------
>  2 files changed, 10 insertions(+), 8 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
> index 7e79fcc..980e065 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> @@ -14,3 +14,7 @@ using one of the following compatible strings:
>    allwinner,sun8i-a83t
>    allwinner,sun8i-h3
>    allwinner,sun9i-a80
> +
> +For Allwinner SoCs without any specific needs the generic fallback value of:
> +  allwinner,sunxi
> +can be used.

Perhaps "fallback" implies this, but be more specific that it can be 
used in addition to a specific string.

> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index e460a6b..efcce85 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -1052,14 +1052,12 @@ CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
>  CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
>  CLK_OF_DECLARE(sun8i_h3_clk_init, "allwinner,sun8i-h3", sun6i_init_clocks);
>  
> -static void __init sun8i_a83t_init_clocks(struct device_node *node)
> +static void __init sunxi_generic_init_clocks(struct device_node *node)
>  {
>  	sunxi_init_clocks(NULL, 0);
>  }
> -CLK_OF_DECLARE(sun8i_a83t_clk_init, "allwinner,sun8i-a83t", sun8i_a83t_init_clocks);
> -
> -static void __init sun9i_init_clocks(struct device_node *node)
> -{
> -	sunxi_init_clocks(NULL, 0);
> -}
> -CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80", sun9i_init_clocks);
> +CLK_OF_DECLARE(sun8i_a83t_clk_init, "allwinner,sun8i-a83t",
> +	       sunxi_generic_init_clocks);
> +CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80",
> +	       sunxi_generic_init_clocks);
> +CLK_OF_DECLARE(sunxi_clk_init, "allwinner,sunxi", sunxi_generic_init_clocks);
> -- 
> 2.6.4
> 

Re: [PATCH 07/11] clk: sunxi: add generic allwinner,sunxi name

[Andre Przywara]

Hi,

On 08/02/16 15:57, Rob Herring wrote:
> On Mon, Feb 01, 2016 at 05:39:26PM +0000, Andre Przywara wrote:
>> The only difference between the different compatible matches at the
>> end of clk-sunxi.c are the critical clocks. Two SoCs get away so far
>> without any, so there is no reason to enumerate those SoCs in here
>> explicitly, though we have to keep them in for compatibility reasons.
>>
>> Rename the init function to highlight this generic feature and add a
>> new, generic DT compatible string which can be used as a fallback value
>> in the future should a particular SoC don't need any special treatment.
>>
>> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
>> ---
>>  Documentation/devicetree/bindings/arm/sunxi.txt |  4 ++++
>>  drivers/clk/sunxi/clk-sunxi.c                   | 14 ++++++--------
>>  2 files changed, 10 insertions(+), 8 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
>> index 7e79fcc..980e065 100644
>> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
>> @@ -14,3 +14,7 @@ using one of the following compatible strings:
>>    allwinner,sun8i-a83t
>>    allwinner,sun8i-h3
>>    allwinner,sun9i-a80
>> +
>> +For Allwinner SoCs without any specific needs the generic fallback value of:
>> +  allwinner,sunxi
>> +can be used.
> 
> Perhaps "fallback" implies this, but be more specific that it can be 
> used in addition to a specific string.

Yeah, good point.

But Maxime's latest rework [1] made this patch here actually obsolete,
so we don't match on a root compatible string anymore to register the
sunxi clock drivers. Instead each clock is registered and matched on
it's own compatible string. Much nicer now, IMHO.

Thanks for having a look!
Andre.

[1]
https://git.kernel.org/cgit/linux/kernel/git/mripard/linux.git/commit/?h=sunxi/for-next&id=78e3fb4c745114b16a12458036d48aa96ea5b36d

>> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
>> index e460a6b..efcce85 100644
>> --- a/drivers/clk/sunxi/clk-sunxi.c
>> +++ b/drivers/clk/sunxi/clk-sunxi.c
>> @@ -1052,14 +1052,12 @@ CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
>>  CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
>>  CLK_OF_DECLARE(sun8i_h3_clk_init, "allwinner,sun8i-h3", sun6i_init_clocks);
>>  
>> -static void __init sun8i_a83t_init_clocks(struct device_node *node)
>> +static void __init sunxi_generic_init_clocks(struct device_node *node)
>>  {
>>  	sunxi_init_clocks(NULL, 0);
>>  }
>> -CLK_OF_DECLARE(sun8i_a83t_clk_init, "allwinner,sun8i-a83t", sun8i_a83t_init_clocks);
>> -
>> -static void __init sun9i_init_clocks(struct device_node *node)
>> -{
>> -	sunxi_init_clocks(NULL, 0);
>> -}
>> -CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80", sun9i_init_clocks);
>> +CLK_OF_DECLARE(sun8i_a83t_clk_init, "allwinner,sun8i-a83t",
>> +	       sunxi_generic_init_clocks);
>> +CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80",
>> +	       sunxi_generic_init_clocks);
>> +CLK_OF_DECLARE(sunxi_clk_init, "allwinner,sunxi", sunxi_generic_init_clocks);
>> -- 
>> 2.6.4
>>
> 
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[PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi

[Andre Przywara]

The Allwinner A64 SoC is low-cost SoC with 4 ARM Cortex-A53 cores
and the typical tablet / TV box peripherals.
The Soc is based on the (32-bit) Allwinner H3 chip, sharing most of
the peripherals and the memory map.
Although the cores are proper 64-bit ones, the whole SoC is actually
limited to 4GB (including all the supported DRAM), so we use 32-bit
address and size cells. This has the nice feature of us being able to
reuse the DT for 32-bit kernels as well.
This .dtsi lists the hardware that we support so far.

Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
---
 Documentation/devicetree/bindings/arm/sunxi.txt   |   1 +
 Documentation/devicetree/bindings/clock/sunxi.txt |   1 +
 arch/arm64/boot/dts/allwinner/a64.dtsi            | 583 ++++++++++++++++++++++
 3 files changed, 585 insertions(+)
 create mode 100644 arch/arm64/boot/dts/allwinner/a64.dtsi

diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
index 980e065..4a83853 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,6 +14,7 @@ using one of the following compatible strings:
   allwinner,sun8i-a83t
   allwinner,sun8i-h3
   allwinner,sun9i-a80
+  allwinner,a64
 
 For Allwinner SoCs without any specific needs the generic fallback value of:
   allwinner,sunxi
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index e59f57b..44b0c6c 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -77,6 +77,7 @@ Required properties:
 	"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
 	"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
 	"allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
+	"allwinner,a64-bus-gates-clk" - for the A64 multi-parent bus gates clock
 
 Required properties for all clocks:
 - reg : shall be the control register address for the clock.
diff --git a/arch/arm64/boot/dts/allwinner/a64.dtsi b/arch/arm64/boot/dts/allwinner/a64.dtsi
new file mode 100644
index 0000000..8dce10f
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/a64.dtsi
@@ -0,0 +1,583 @@
+/*
+ * Copyright (C) 2016 ARM Ltd.
+ * based on the Allwinner H3 dtsi:
+ *    Copyright (C) 2015 Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+	compatible = "allwinner,a64", "allwinner,sunxi";
+	interrupt-parent = <&gic>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0>;
+			enable-method = "psci";
+		};
+
+		cpu@1 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <1>;
+			enable-method = "psci";
+		};
+
+		cpu@2 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <2>;
+			enable-method = "psci";
+		};
+
+		cpu@3 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <3>;
+			enable-method = "psci";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2", "arm,psci";
+		method = "smc";
+		cpu_suspend = <0xc4000001>;
+		cpu_off = <0x84000002>;
+		cpu_on = <0xc4000003>;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x40000000 0>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 14
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 11
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 10
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		osc24M: osc24M_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "osc24M";
+		};
+
+		osc32k: osc32k_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			clock-output-names = "osc32k";
+		};
+
+		pll1: clk@01c20000 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun8i-a23-pll1-clk";
+			reg = <0x01c20000 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll1";
+		};
+
+		pll6: clk@01c20028 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun6i-a31-pll6-clk";
+			reg = <0x01c20028 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll6", "pll6x2";
+		};
+
+		pll6d2: pll6d2_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clock-div = <2>;
+			clock-mult = <1>;
+			clocks = <&pll6 0>;
+			clock-output-names = "pll6d2";
+		};
+
+		/* dummy clock until pll6 can be reused */
+		pll8: pll8_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <1>;
+			clock-output-names = "pll8";
+		};
+
+		cpu: cpu_clk@01c20050 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-cpu-clk";
+			reg = <0x01c20050 0x4>;
+			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
+			clock-output-names = "cpu";
+			critical-clocks = <0>;
+		};
+
+		axi: axi_clk@01c20050 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-axi-clk";
+			reg = <0x01c20050 0x4>;
+			clocks = <&cpu>;
+			clock-output-names = "axi";
+		};
+
+		ahb1: ahb1_clk@01c20054 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun6i-a31-ahb1-clk";
+			reg = <0x01c20054 0x4>;
+			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
+			clock-output-names = "ahb1";
+		};
+
+		ahb2: ahb2_clk@01c2005c {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun8i-h3-ahb2-clk";
+			reg = <0x01c2005c 0x4>;
+			clocks = <&ahb1>, <&pll6d2>;
+			clock-output-names = "ahb2";
+		};
+
+		apb1: apb1_clk@01c20054 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-apb0-clk";
+			reg = <0x01c20054 0x4>;
+			clocks = <&ahb1>;
+			clock-output-names = "apb1";
+		};
+
+		apb2: apb2_clk@01c20058 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-apb1-clk";
+			reg = <0x01c20058 0x4>;
+			clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
+			clock-output-names = "apb2";
+		};
+
+		bus_gates: clk@01c20060 {
+			#clock-cells = <1>;
+			compatible = "allwinner,a64-bus-gates-clk",
+				     "allwinner,sunxi-multi-bus-gates-clk";
+			reg = <0x01c20060 0x14>;
+			ahb1_parent {
+				clocks = <&ahb1>;
+				clock-indices = <1>, <5>,
+						<6>, <8>,
+						<9>, <10>,
+						<13>, <14>,
+						<18>, <19>,
+						<20>, <21>,
+						<23>, <24>,
+						<25>, <28>,
+						<32>, <35>,
+						<36>, <37>,
+						<40>, <43>,
+						<44>, <52>,
+						<53>, <54>,
+						<135>;
+				clock-output-names = "bus_mipidsi", "bus_ce",
+						"bus_dma", "bus_mmc0",
+						"bus_mmc1", "bus_mmc2",
+						"bus_nand", "bus_sdram",
+						"bus_ts", "bus_hstimer",
+						"bus_spi0", "bus_spi1",
+						"bus_otg", "bus_otg_ehci0",
+						"bus_ehci0", "bus_otg_ohci0",
+						"bus_ve", "bus_lcd0",
+						"bus_lcd1", "bus_deint",
+						"bus_csi", "bus_hdmi",
+						"bus_de", "bus_gpu",
+						"bus_msgbox", "bus_spinlock",
+						"bus_dbg";
+			};
+			ahb2_parent {
+				clocks = <&ahb2>;
+				clock-indices = <17>, <29>;
+				clock-output-names = "bus_gmac", "bus_ohci0";
+			};
+			apb1_parent {
+				clocks = <&apb1>;
+				clock-indices = <64>, <65>,
+						<69>, <72>,
+						<76>, <77>,
+						<78>;
+				clock-output-names = "bus_codec", "bus_spdif",
+						"bus_pio", "bus_ths",
+						"bus_i2s0", "bus_i2s1",
+						"bus_i2s2";
+			};
+			abp2_parent {
+				clocks = <&apb2>;
+				clock-indices = <96>, <97>,
+						<98>, <101>,
+						<112>, <113>,
+						<114>, <115>,
+						<116>;
+				clock-output-names = "bus_i2c0", "bus_i2c1",
+						"bus_i2c2", "bus_scr",
+						"bus_uart0", "bus_uart1",
+						"bus_uart2", "bus_uart3",
+						"bus_uart4";
+			};
+		};
+
+		mmc0_clk: clk@01c20088 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-mmc-clk";
+			reg = <0x01c20088 0x4>;
+			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
+			clock-output-names = "mmc0",
+					     "mmc0_output",
+					     "mmc0_sample";
+		};
+
+		mmc1_clk: clk@01c2008c {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-mmc-clk";
+			reg = <0x01c2008c 0x4>;
+			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
+			clock-output-names = "mmc1",
+					     "mmc1_output",
+					     "mmc1_sample";
+		};
+
+		mmc2_clk: clk@01c20090 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-mmc-clk";
+			reg = <0x01c20090 0x4>;
+			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
+			clock-output-names = "mmc2",
+					     "mmc2_output",
+					     "mmc2_sample";
+		};
+	};
+
+	regulators {
+		reg_vcc3v3: vcc3v3 {
+			compatible = "regulator-fixed";
+			regulator-name = "vcc3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		mmc0: mmc@01c0f000 {
+			compatible = "allwinner,sun5i-a13-mmc";
+			reg = <0x01c0f000 0x1000>;
+			clocks = <&bus_gates 8>,
+				 <&mmc0_clk 0>,
+				 <&mmc0_clk 1>,
+				 <&mmc0_clk 2>;
+			clock-names = "ahb",
+				      "mmc",
+				      "output",
+				      "sample";
+			resets = <&ahb_rst 8>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc1: mmc@01c10000 {
+			compatible = "allwinner,sun5i-a13-mmc";
+			reg = <0x01c10000 0x1000>;
+			clocks = <&bus_gates 9>,
+				 <&mmc1_clk 0>,
+				 <&mmc1_clk 1>,
+				 <&mmc1_clk 2>;
+			clock-names = "ahb",
+				      "mmc",
+				      "output",
+				      "sample";
+			resets = <&ahb_rst 9>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc2: mmc@01c11000 {
+			compatible = "allwinner,sun5i-a13-mmc";
+			reg = <0x01c11000 0x1000>;
+			clocks = <&bus_gates 10>,
+				 <&mmc2_clk 0>,
+				 <&mmc2_clk 1>,
+				 <&mmc2_clk 2>;
+			clock-names = "ahb",
+				      "mmc",
+				      "output",
+				      "sample";
+			resets = <&ahb_rst 10>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		pio: pinctrl@01c20800 {
+			compatible = "allwinner,a64-pinctrl";
+			reg = <0x01c20800 0x400>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&bus_gates 69>;
+			gpio-controller;
+			#gpio-cells = <3>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			uart0_pins_a: uart0@0 {
+				allwinner,pins = "PB8", "PB9";
+				allwinner,function = "uart0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart0_pins_b: uart0@1 {
+				allwinner,pins = "PF2", "PF3";
+				allwinner,function = "uart0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart1_pins: uart1@0 {
+				allwinner,pins = "PG6", "PG7", "PG8", "PG9";
+				allwinner,function = "uart1";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart2_pins: uart2@0 {
+				allwinner,pins = "PB0", "PB1", "PB2", "PB3";
+				allwinner,function = "uart2";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart3_pins_a: uart3@0 {
+				allwinner,pins = "PD0", "PD1";
+				allwinner,function = "uart3";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart3_pins_b: uart3@1 {
+				allwinner,pins = "PH4", "PH5", "PH6", "PH7";
+				allwinner,function = "uart3";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart4_pins: uart4@0 {
+				allwinner,pins = "PD2", "PD3", "PD4", "PD5";
+				allwinner,function = "uart4";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			mmc0_pins: mmc0@0 {
+				allwinner,pins = "PF0", "PF1", "PF2", "PF3",
+						 "PF4", "PF5";
+				allwinner,function = "mmc0";
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			mmc0_default_cd_pin: mmc0_cd_pin@0 {
+				allwinner,pins = "PF6";
+				allwinner,function = "gpio_in";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+			};
+
+			mmc1_pins: mmc1@0 {
+				allwinner,pins = "PG0", "PG1", "PG2", "PG3",
+						 "PG4", "PG5";
+				allwinner,function = "mmc1";
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			mmc2_pins: mmc2@0 {
+				allwinner,pins = "PC1", "PC5", "PC6", "PC8",
+						 "PC9", "PC10";
+				allwinner,function = "mmc2";
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+		};
+
+		ahb_rst: reset@01c202c0 {
+			#reset-cells = <1>;
+			compatible = "allwinner,sun6i-a31-ahb1-reset";
+			reg = <0x01c202c0 0xc>;
+		};
+
+		apb1_rst: reset@01c202d0 {
+			#reset-cells = <1>;
+			compatible = "allwinner,sun6i-a31-clock-reset";
+			reg = <0x01c202d0 0x4>;
+		};
+
+		apb2_rst: reset@01c202d8 {
+			#reset-cells = <1>;
+			compatible = "allwinner,sun6i-a31-clock-reset";
+			reg = <0x01c202d8 0x4>;
+		};
+
+		uart0: serial@01c28000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28000 0x400>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&bus_gates 112>;
+			resets = <&apb2_rst 16>;
+			reset-names = "apb2";
+			status = "disabled";
+		};
+
+		uart1: serial@01c28400 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28400 0x400>;
+			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&bus_gates 113>;
+			resets = <&apb2_rst 17>;
+			reset-names = "apb2";
+			status = "disabled";
+		};
+
+		uart2: serial@01c28800 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28800 0x400>;
+			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&bus_gates 114>;
+			resets = <&apb2_rst 18>;
+			reset-names = "apb2";
+			status = "disabled";
+		};
+
+		uart3: serial@01c28c00 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28c00 0x400>;
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&bus_gates 115>;
+			resets = <&apb2_rst 19>;
+			reset-names = "apb2";
+			status = "disabled";
+		};
+
+		uart4: serial@01c29000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c29000 0x400>;
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&bus_gates 116>;
+			resets = <&apb2_rst 20>;
+			reset-names = "apb2";
+			status = "disabled";
+		};
+
+		rtc: rtc@01f00000 {
+			compatible = "allwinner,sun6i-a31-rtc";
+			reg = <0x01f00000 0x54>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+
+	gic: interrupt-controller@{
+		compatible = "arm,gic-400";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+
+		reg = <0x01C81000 0x1000>,
+		      <0x01C82000 0x2000>,
+		      <0x01C84000 0x2000>,
+		      <0x01C86000 0x2000>;
+		interrupts = <GIC_PPI 9
+		      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+};
-- 
2.6.4

Re: [linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi

[Karsten Merker]

Hello,

a few tiny spelling nitpicks in case you should do a V2:

On Mon, Feb 01, 2016 at 05:39:29PM +0000, Andre Przywara wrote:

> The Allwinner A64 SoC is low-cost SoC with 4 ARM Cortex-A53 cores

s/is low-cost SoC/is a low-cost SoC/
                         
> and the typical tablet / TV box peripherals.
> The Soc is based on the (32-bit) Allwinner H3 chip, sharing most of

s/Soc/SoC/

> the peripherals and the memory map.
> Although the cores are proper 64-bit ones, the whole SoC is actually
> limited to 4GB (including all the supported DRAM), so we use 32-bit
> address and size cells. This has the nice feature of us being able to
> reuse the DT for 32-bit kernels as well.
> This .dtsi lists the hardware that we support so far.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  Documentation/devicetree/bindings/arm/sunxi.txt   |   1 +
>  Documentation/devicetree/bindings/clock/sunxi.txt |   1 +
>  arch/arm64/boot/dts/allwinner/a64.dtsi            | 583 ++++++++++++++++++++++
>  3 files changed, 585 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/allwinner/a64.dtsi
> 
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
> index 980e065..4a83853 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> @@ -14,6 +14,7 @@ using one of the following compatible strings:
>    allwinner,sun8i-a83t
>    allwinner,sun8i-h3
>    allwinner,sun9i-a80
> +  allwinner,a64

Please see my followup to patch No. 5 in this series.
s/allwinner,a64/allwinner,sun50i-a64/ ?

>  
>  For Allwinner SoCs without any specific needs the generic fallback value of:
>    allwinner,sunxi
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index e59f57b..44b0c6c 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -77,6 +77,7 @@ Required properties:
>  	"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
>  	"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
>  	"allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
> +	"allwinner,a64-bus-gates-clk" - for the A64 multi-parent bus gates clock

see above

>  
>  Required properties for all clocks:
>  - reg : shall be the control register address for the clock.
> diff --git a/arch/arm64/boot/dts/allwinner/a64.dtsi b/arch/arm64/boot/dts/allwinner/a64.dtsi

see above - the dts and dtsi names for the other Allwinner SoCs contain
the SoC family. 

> new file mode 100644
> index 0000000..8dce10f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/a64.dtsi
> @@ -0,0 +1,583 @@
> +/*
> + * Copyright (C) 2016 ARM Ltd.
> + * based on the Allwinner H3 dtsi:
> + *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
> +
> +/ {
> +	compatible = "allwinner,a64", "allwinner,sunxi";

see above

> +	interrupt-parent = <&gic>;
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +		serial4 = &uart4;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <0>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu@1 {
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <1>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu@2 {
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <2>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu@3 {
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <3>;
> +			enable-method = "psci";
> +		};
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-0.2", "arm,psci";
> +		method = "smc";
> +		cpu_suspend = <0xc4000001>;
> +		cpu_off = <0x84000002>;
> +		cpu_on = <0xc4000003>;
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x40000000 0>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13
> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> +			     <GIC_PPI 14
> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> +			     <GIC_PPI 11
> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> +			     <GIC_PPI 10
> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +	};
> +
> +	clocks {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		osc24M: osc24M_clk {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <24000000>;
> +			clock-output-names = "osc24M";
> +		};
> +
> +		osc32k: osc32k_clk {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <32768>;
> +			clock-output-names = "osc32k";
> +		};
> +
> +		pll1: clk@01c20000 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun8i-a23-pll1-clk";
> +			reg = <0x01c20000 0x4>;
> +			clocks = <&osc24M>;
> +			clock-output-names = "pll1";
> +		};
> +
> +		pll6: clk@01c20028 {
> +			#clock-cells = <1>;
> +			compatible = "allwinner,sun6i-a31-pll6-clk";
> +			reg = <0x01c20028 0x4>;
> +			clocks = <&osc24M>;
> +			clock-output-names = "pll6", "pll6x2";
> +		};
> +
> +		pll6d2: pll6d2_clk {
> +			#clock-cells = <0>;
> +			compatible = "fixed-factor-clock";
> +			clock-div = <2>;
> +			clock-mult = <1>;
> +			clocks = <&pll6 0>;
> +			clock-output-names = "pll6d2";
> +		};
> +
> +		/* dummy clock until pll6 can be reused */
> +		pll8: pll8_clk {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <1>;
> +			clock-output-names = "pll8";
> +		};
> +
> +		cpu: cpu_clk@01c20050 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-cpu-clk";
> +			reg = <0x01c20050 0x4>;
> +			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
> +			clock-output-names = "cpu";
> +			critical-clocks = <0>;
> +		};
> +
> +		axi: axi_clk@01c20050 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-axi-clk";
> +			reg = <0x01c20050 0x4>;
> +			clocks = <&cpu>;
> +			clock-output-names = "axi";
> +		};
> +
> +		ahb1: ahb1_clk@01c20054 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun6i-a31-ahb1-clk";
> +			reg = <0x01c20054 0x4>;
> +			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
> +			clock-output-names = "ahb1";
> +		};
> +
> +		ahb2: ahb2_clk@01c2005c {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun8i-h3-ahb2-clk";
> +			reg = <0x01c2005c 0x4>;
> +			clocks = <&ahb1>, <&pll6d2>;
> +			clock-output-names = "ahb2";
> +		};
> +
> +		apb1: apb1_clk@01c20054 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-apb0-clk";
> +			reg = <0x01c20054 0x4>;
> +			clocks = <&ahb1>;
> +			clock-output-names = "apb1";
> +		};
> +
> +		apb2: apb2_clk@01c20058 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-apb1-clk";
> +			reg = <0x01c20058 0x4>;
> +			clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
> +			clock-output-names = "apb2";
> +		};
> +
> +		bus_gates: clk@01c20060 {
> +			#clock-cells = <1>;
> +			compatible = "allwinner,a64-bus-gates-clk",

see above

> +				     "allwinner,sunxi-multi-bus-gates-clk";
> +			reg = <0x01c20060 0x14>;
> +			ahb1_parent {
> +				clocks = <&ahb1>;
> +				clock-indices = <1>, <5>,
> +						<6>, <8>,
> +						<9>, <10>,
> +						<13>, <14>,
> +						<18>, <19>,
> +						<20>, <21>,
> +						<23>, <24>,
> +						<25>, <28>,
> +						<32>, <35>,
> +						<36>, <37>,
> +						<40>, <43>,
> +						<44>, <52>,
> +						<53>, <54>,
> +						<135>;
> +				clock-output-names = "bus_mipidsi", "bus_ce",
> +						"bus_dma", "bus_mmc0",
> +						"bus_mmc1", "bus_mmc2",
> +						"bus_nand", "bus_sdram",
> +						"bus_ts", "bus_hstimer",
> +						"bus_spi0", "bus_spi1",
> +						"bus_otg", "bus_otg_ehci0",
> +						"bus_ehci0", "bus_otg_ohci0",
> +						"bus_ve", "bus_lcd0",
> +						"bus_lcd1", "bus_deint",
> +						"bus_csi", "bus_hdmi",
> +						"bus_de", "bus_gpu",
> +						"bus_msgbox", "bus_spinlock",
> +						"bus_dbg";
> +			};
> +			ahb2_parent {
> +				clocks = <&ahb2>;
> +				clock-indices = <17>, <29>;
> +				clock-output-names = "bus_gmac", "bus_ohci0";
> +			};
> +			apb1_parent {
> +				clocks = <&apb1>;
> +				clock-indices = <64>, <65>,
> +						<69>, <72>,
> +						<76>, <77>,
> +						<78>;
> +				clock-output-names = "bus_codec", "bus_spdif",
> +						"bus_pio", "bus_ths",
> +						"bus_i2s0", "bus_i2s1",
> +						"bus_i2s2";
> +			};
> +			abp2_parent {
> +				clocks = <&apb2>;
> +				clock-indices = <96>, <97>,
> +						<98>, <101>,
> +						<112>, <113>,
> +						<114>, <115>,
> +						<116>;
> +				clock-output-names = "bus_i2c0", "bus_i2c1",
> +						"bus_i2c2", "bus_scr",
> +						"bus_uart0", "bus_uart1",
> +						"bus_uart2", "bus_uart3",
> +						"bus_uart4";
> +			};
> +		};
> +
> +		mmc0_clk: clk@01c20088 {
> +			#clock-cells = <1>;
> +			compatible = "allwinner,sun4i-a10-mmc-clk";
> +			reg = <0x01c20088 0x4>;
> +			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
> +			clock-output-names = "mmc0",
> +					     "mmc0_output",
> +					     "mmc0_sample";
> +		};
> +
> +		mmc1_clk: clk@01c2008c {
> +			#clock-cells = <1>;
> +			compatible = "allwinner,sun4i-a10-mmc-clk";
> +			reg = <0x01c2008c 0x4>;
> +			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
> +			clock-output-names = "mmc1",
> +					     "mmc1_output",
> +					     "mmc1_sample";
> +		};
> +
> +		mmc2_clk: clk@01c20090 {
> +			#clock-cells = <1>;
> +			compatible = "allwinner,sun4i-a10-mmc-clk";
> +			reg = <0x01c20090 0x4>;
> +			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
> +			clock-output-names = "mmc2",
> +					     "mmc2_output",
> +					     "mmc2_sample";
> +		};
> +	};
> +
> +	regulators {
> +		reg_vcc3v3: vcc3v3 {
> +			compatible = "regulator-fixed";
> +			regulator-name = "vcc3v3";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +		};
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		mmc0: mmc@01c0f000 {
> +			compatible = "allwinner,sun5i-a13-mmc";
> +			reg = <0x01c0f000 0x1000>;
> +			clocks = <&bus_gates 8>,
> +				 <&mmc0_clk 0>,
> +				 <&mmc0_clk 1>,
> +				 <&mmc0_clk 2>;
> +			clock-names = "ahb",
> +				      "mmc",
> +				      "output",
> +				      "sample";
> +			resets = <&ahb_rst 8>;
> +			reset-names = "ahb";
> +			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		mmc1: mmc@01c10000 {
> +			compatible = "allwinner,sun5i-a13-mmc";
> +			reg = <0x01c10000 0x1000>;
> +			clocks = <&bus_gates 9>,
> +				 <&mmc1_clk 0>,
> +				 <&mmc1_clk 1>,
> +				 <&mmc1_clk 2>;
> +			clock-names = "ahb",
> +				      "mmc",
> +				      "output",
> +				      "sample";
> +			resets = <&ahb_rst 9>;
> +			reset-names = "ahb";
> +			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		mmc2: mmc@01c11000 {
> +			compatible = "allwinner,sun5i-a13-mmc";
> +			reg = <0x01c11000 0x1000>;
> +			clocks = <&bus_gates 10>,
> +				 <&mmc2_clk 0>,
> +				 <&mmc2_clk 1>,
> +				 <&mmc2_clk 2>;
> +			clock-names = "ahb",
> +				      "mmc",
> +				      "output",
> +				      "sample";
> +			resets = <&ahb_rst 10>;
> +			reset-names = "ahb";
> +			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		pio: pinctrl@01c20800 {
> +			compatible = "allwinner,a64-pinctrl";

see above

> +			reg = <0x01c20800 0x400>;
> +			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&bus_gates 69>;
> +			gpio-controller;
> +			#gpio-cells = <3>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +
> +			uart0_pins_a: uart0@0 {
> +				allwinner,pins = "PB8", "PB9";
> +				allwinner,function = "uart0";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			uart0_pins_b: uart0@1 {
> +				allwinner,pins = "PF2", "PF3";
> +				allwinner,function = "uart0";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			uart1_pins: uart1@0 {
> +				allwinner,pins = "PG6", "PG7", "PG8", "PG9";
> +				allwinner,function = "uart1";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			uart2_pins: uart2@0 {
> +				allwinner,pins = "PB0", "PB1", "PB2", "PB3";
> +				allwinner,function = "uart2";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			uart3_pins_a: uart3@0 {
> +				allwinner,pins = "PD0", "PD1";
> +				allwinner,function = "uart3";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			uart3_pins_b: uart3@1 {
> +				allwinner,pins = "PH4", "PH5", "PH6", "PH7";
> +				allwinner,function = "uart3";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			uart4_pins: uart4@0 {
> +				allwinner,pins = "PD2", "PD3", "PD4", "PD5";
> +				allwinner,function = "uart4";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			mmc0_pins: mmc0@0 {
> +				allwinner,pins = "PF0", "PF1", "PF2", "PF3",
> +						 "PF4", "PF5";
> +				allwinner,function = "mmc0";
> +				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			mmc0_default_cd_pin: mmc0_cd_pin@0 {
> +				allwinner,pins = "PF6";
> +				allwinner,function = "gpio_in";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
> +			};
> +
> +			mmc1_pins: mmc1@0 {
> +				allwinner,pins = "PG0", "PG1", "PG2", "PG3",
> +						 "PG4", "PG5";
> +				allwinner,function = "mmc1";
> +				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			mmc2_pins: mmc2@0 {
> +				allwinner,pins = "PC1", "PC5", "PC6", "PC8",
> +						 "PC9", "PC10";
> +				allwinner,function = "mmc2";
> +				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +		};
> +
> +		ahb_rst: reset@01c202c0 {
> +			#reset-cells = <1>;
> +			compatible = "allwinner,sun6i-a31-ahb1-reset";
> +			reg = <0x01c202c0 0xc>;
> +		};
> +
> +		apb1_rst: reset@01c202d0 {
> +			#reset-cells = <1>;
> +			compatible = "allwinner,sun6i-a31-clock-reset";
> +			reg = <0x01c202d0 0x4>;
> +		};
> +
> +		apb2_rst: reset@01c202d8 {
> +			#reset-cells = <1>;
> +			compatible = "allwinner,sun6i-a31-clock-reset";
> +			reg = <0x01c202d8 0x4>;
> +		};
> +
> +		uart0: serial@01c28000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c28000 0x400>;
> +			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&bus_gates 112>;
> +			resets = <&apb2_rst 16>;
> +			reset-names = "apb2";
> +			status = "disabled";
> +		};
> +
> +		uart1: serial@01c28400 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c28400 0x400>;
> +			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&bus_gates 113>;
> +			resets = <&apb2_rst 17>;
> +			reset-names = "apb2";
> +			status = "disabled";
> +		};
> +
> +		uart2: serial@01c28800 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c28800 0x400>;
> +			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&bus_gates 114>;
> +			resets = <&apb2_rst 18>;
> +			reset-names = "apb2";
> +			status = "disabled";
> +		};
> +
> +		uart3: serial@01c28c00 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c28c00 0x400>;
> +			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&bus_gates 115>;
> +			resets = <&apb2_rst 19>;
> +			reset-names = "apb2";
> +			status = "disabled";
> +		};
> +
> +		uart4: serial@01c29000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c29000 0x400>;
> +			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&bus_gates 116>;
> +			resets = <&apb2_rst 20>;
> +			reset-names = "apb2";
> +			status = "disabled";
> +		};
> +
> +		rtc: rtc@01f00000 {
> +			compatible = "allwinner,sun6i-a31-rtc";
> +			reg = <0x01f00000 0x54>;
> +			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +	};
> +
> +	gic: interrupt-controller@{
> +		compatible = "arm,gic-400";
> +		interrupt-controller;
> +		#interrupt-cells = <3>;
> +		#address-cells = <0>;
> +
> +		reg = <0x01C81000 0x1000>,
> +		      <0x01C82000 0x2000>,
> +		      <0x01C84000 0x2000>,
> +		      <0x01C86000 0x2000>;
> +		interrupts = <GIC_PPI 9
> +		      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +	};
> +};
> -- 
> 2.6.4

Regards,
Karsten
-- 
Gem. Par. 28 Abs. 4 Bundesdatenschutzgesetz widerspreche ich der Nutzung
sowie der Weitergabe meiner personenbezogenen Daten für Zwecke der
Werbung sowie der Markt- oder Meinungsforschung.

Re: [linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi

[André Przywara]

On 01/02/16 19:05, Karsten Merker wrote:
> Hello,
> 
> a few tiny spelling nitpicks in case you should do a V2:

Definitely! ;-)

> 
> On Mon, Feb 01, 2016 at 05:39:29PM +0000, Andre Przywara wrote:
> 
>> The Allwinner A64 SoC is low-cost SoC with 4 ARM Cortex-A53 cores
> 
> s/is low-cost SoC/is a low-cost SoC/
>                          
>> and the typical tablet / TV box peripherals.
>> The Soc is based on the (32-bit) Allwinner H3 chip, sharing most of
> 
> s/Soc/SoC/

Thanks for catching those!

>> the peripherals and the memory map.
>> Although the cores are proper 64-bit ones, the whole SoC is actually
>> limited to 4GB (including all the supported DRAM), so we use 32-bit
>> address and size cells. This has the nice feature of us being able to
>> reuse the DT for 32-bit kernels as well.
>> This .dtsi lists the hardware that we support so far.
>>
>> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
>> ---
>>  Documentation/devicetree/bindings/arm/sunxi.txt   |   1 +
>>  Documentation/devicetree/bindings/clock/sunxi.txt |   1 +
>>  arch/arm64/boot/dts/allwinner/a64.dtsi            | 583 ++++++++++++++++++++++
>>  3 files changed, 585 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/allwinner/a64.dtsi
>>
>> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
>> index 980e065..4a83853 100644
>> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
>> @@ -14,6 +14,7 @@ using one of the following compatible strings:
>>    allwinner,sun8i-a83t
>>    allwinner,sun8i-h3
>>    allwinner,sun9i-a80
>> +  allwinner,a64
> 
> Please see my followup to patch No. 5 in this series.
> s/allwinner,a64/allwinner,sun50i-a64/ ?

As explained in the first email, rather not, especially if it is about
DT namings.

>>  
>>  For Allwinner SoCs without any specific needs the generic fallback value of:
>>    allwinner,sunxi
>> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
>> index e59f57b..44b0c6c 100644
>> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>> @@ -77,6 +77,7 @@ Required properties:
>>  	"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
>>  	"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
>>  	"allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
>> +	"allwinner,a64-bus-gates-clk" - for the A64 multi-parent bus gates clock
> 
> see above
> 
>>  
>>  Required properties for all clocks:
>>  - reg : shall be the control register address for the clock.
>> diff --git a/arch/arm64/boot/dts/allwinner/a64.dtsi b/arch/arm64/boot/dts/allwinner/a64.dtsi
> 
> see above - the dts and dtsi names for the other Allwinner SoCs contain
> the SoC family. 

... mostly because the arm DTs are all in one directory, and just some
a<xx>.dtsi is then indeed not very specific. But arm64 fortunately has
per-vendor directories, so things are pretty well separated. If a64.dtsi
is deemed too short, I could call it allwinner_a64.dtsi or maybe
sunxi_a64.dtsi, but I'd rather avoid sun50i-a64.dtsi.
Also looking at the other arm64 DTs I see a lot of short names, just
using the (marketing) chip name as the stub.

Similar reasoning for the other occurrences below.

Cheers,
Andre.

>> new file mode 100644
>> index 0000000..8dce10f
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/allwinner/a64.dtsi
>> @@ -0,0 +1,583 @@
>> +/*
>> + * Copyright (C) 2016 ARM Ltd.
>> + * based on the Allwinner H3 dtsi:
>> + *    Copyright (C) 2015 Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This file is free software; you can redistribute it and/or
>> + *     modify it under the terms of the GNU General Public License as
>> + *     published by the Free Software Foundation; either version 2 of the
>> + *     License, or (at your option) any later version.
>> + *
>> + *     This file is distributed in the hope that it will be useful,
>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + *     GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + *     obtaining a copy of this software and associated documentation
>> + *     files (the "Software"), to deal in the Software without
>> + *     restriction, including without limitation the rights to use,
>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
>> + *     sell copies of the Software, and to permit persons to whom the
>> + *     Software is furnished to do so, subject to the following
>> + *     conditions:
>> + *
>> + *     The above copyright notice and this permission notice shall be
>> + *     included in all copies or substantial portions of the Software.
>> + *
>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + *     OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/pinctrl/sun4i-a10.h>
>> +
>> +/ {
>> +	compatible = "allwinner,a64", "allwinner,sunxi";
> 
> see above
> 
>> +	interrupt-parent = <&gic>;
>> +	#address-cells = <1>;
>> +	#size-cells = <1>;
>> +
>> +	aliases {
>> +		serial0 = &uart0;
>> +		serial1 = &uart1;
>> +		serial2 = &uart2;
>> +		serial3 = &uart3;
>> +		serial4 = &uart4;
>> +	};
>> +
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		cpu@0 {
>> +			compatible = "arm,cortex-a53", "arm,armv8";
>> +			device_type = "cpu";
>> +			reg = <0>;
>> +			enable-method = "psci";
>> +		};
>> +
>> +		cpu@1 {
>> +			compatible = "arm,cortex-a53", "arm,armv8";
>> +			device_type = "cpu";
>> +			reg = <1>;
>> +			enable-method = "psci";
>> +		};
>> +
>> +		cpu@2 {
>> +			compatible = "arm,cortex-a53", "arm,armv8";
>> +			device_type = "cpu";
>> +			reg = <2>;
>> +			enable-method = "psci";
>> +		};
>> +
>> +		cpu@3 {
>> +			compatible = "arm,cortex-a53", "arm,armv8";
>> +			device_type = "cpu";
>> +			reg = <3>;
>> +			enable-method = "psci";
>> +		};
>> +	};
>> +
>> +	psci {
>> +		compatible = "arm,psci-0.2", "arm,psci";
>> +		method = "smc";
>> +		cpu_suspend = <0xc4000001>;
>> +		cpu_off = <0x84000002>;
>> +		cpu_on = <0xc4000003>;
>> +	};
>> +
>> +	memory {
>> +		device_type = "memory";
>> +		reg = <0x40000000 0>;
>> +	};
>> +
>> +	timer {
>> +		compatible = "arm,armv8-timer";
>> +		interrupts = <GIC_PPI 13
>> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>> +			     <GIC_PPI 14
>> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>> +			     <GIC_PPI 11
>> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>> +			     <GIC_PPI 10
>> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> +	};
>> +
>> +	clocks {
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges;
>> +
>> +		osc24M: osc24M_clk {
>> +			#clock-cells = <0>;
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <24000000>;
>> +			clock-output-names = "osc24M";
>> +		};
>> +
>> +		osc32k: osc32k_clk {
>> +			#clock-cells = <0>;
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <32768>;
>> +			clock-output-names = "osc32k";
>> +		};
>> +
>> +		pll1: clk@01c20000 {
>> +			#clock-cells = <0>;
>> +			compatible = "allwinner,sun8i-a23-pll1-clk";
>> +			reg = <0x01c20000 0x4>;
>> +			clocks = <&osc24M>;
>> +			clock-output-names = "pll1";
>> +		};
>> +
>> +		pll6: clk@01c20028 {
>> +			#clock-cells = <1>;
>> +			compatible = "allwinner,sun6i-a31-pll6-clk";
>> +			reg = <0x01c20028 0x4>;
>> +			clocks = <&osc24M>;
>> +			clock-output-names = "pll6", "pll6x2";
>> +		};
>> +
>> +		pll6d2: pll6d2_clk {
>> +			#clock-cells = <0>;
>> +			compatible = "fixed-factor-clock";
>> +			clock-div = <2>;
>> +			clock-mult = <1>;
>> +			clocks = <&pll6 0>;
>> +			clock-output-names = "pll6d2";
>> +		};
>> +
>> +		/* dummy clock until pll6 can be reused */
>> +		pll8: pll8_clk {
>> +			#clock-cells = <0>;
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <1>;
>> +			clock-output-names = "pll8";
>> +		};
>> +
>> +		cpu: cpu_clk@01c20050 {
>> +			#clock-cells = <0>;
>> +			compatible = "allwinner,sun4i-a10-cpu-clk";
>> +			reg = <0x01c20050 0x4>;
>> +			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
>> +			clock-output-names = "cpu";
>> +			critical-clocks = <0>;
>> +		};
>> +
>> +		axi: axi_clk@01c20050 {
>> +			#clock-cells = <0>;
>> +			compatible = "allwinner,sun4i-a10-axi-clk";
>> +			reg = <0x01c20050 0x4>;
>> +			clocks = <&cpu>;
>> +			clock-output-names = "axi";
>> +		};
>> +
>> +		ahb1: ahb1_clk@01c20054 {
>> +			#clock-cells = <0>;
>> +			compatible = "allwinner,sun6i-a31-ahb1-clk";
>> +			reg = <0x01c20054 0x4>;
>> +			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
>> +			clock-output-names = "ahb1";
>> +		};
>> +
>> +		ahb2: ahb2_clk@01c2005c {
>> +			#clock-cells = <0>;
>> +			compatible = "allwinner,sun8i-h3-ahb2-clk";
>> +			reg = <0x01c2005c 0x4>;
>> +			clocks = <&ahb1>, <&pll6d2>;
>> +			clock-output-names = "ahb2";
>> +		};
>> +
>> +		apb1: apb1_clk@01c20054 {
>> +			#clock-cells = <0>;
>> +			compatible = "allwinner,sun4i-a10-apb0-clk";
>> +			reg = <0x01c20054 0x4>;
>> +			clocks = <&ahb1>;
>> +			clock-output-names = "apb1";
>> +		};
>> +
>> +		apb2: apb2_clk@01c20058 {
>> +			#clock-cells = <0>;
>> +			compatible = "allwinner,sun4i-a10-apb1-clk";
>> +			reg = <0x01c20058 0x4>;
>> +			clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
>> +			clock-output-names = "apb2";
>> +		};
>> +
>> +		bus_gates: clk@01c20060 {
>> +			#clock-cells = <1>;
>> +			compatible = "allwinner,a64-bus-gates-clk",
> 
> see above
> 
>> +				     "allwinner,sunxi-multi-bus-gates-clk";
>> +			reg = <0x01c20060 0x14>;
>> +			ahb1_parent {
>> +				clocks = <&ahb1>;
>> +				clock-indices = <1>, <5>,
>> +						<6>, <8>,
>> +						<9>, <10>,
>> +						<13>, <14>,
>> +						<18>, <19>,
>> +						<20>, <21>,
>> +						<23>, <24>,
>> +						<25>, <28>,
>> +						<32>, <35>,
>> +						<36>, <37>,
>> +						<40>, <43>,
>> +						<44>, <52>,
>> +						<53>, <54>,
>> +						<135>;
>> +				clock-output-names = "bus_mipidsi", "bus_ce",
>> +						"bus_dma", "bus_mmc0",
>> +						"bus_mmc1", "bus_mmc2",
>> +						"bus_nand", "bus_sdram",
>> +						"bus_ts", "bus_hstimer",
>> +						"bus_spi0", "bus_spi1",
>> +						"bus_otg", "bus_otg_ehci0",
>> +						"bus_ehci0", "bus_otg_ohci0",
>> +						"bus_ve", "bus_lcd0",
>> +						"bus_lcd1", "bus_deint",
>> +						"bus_csi", "bus_hdmi",
>> +						"bus_de", "bus_gpu",
>> +						"bus_msgbox", "bus_spinlock",
>> +						"bus_dbg";
>> +			};
>> +			ahb2_parent {
>> +				clocks = <&ahb2>;
>> +				clock-indices = <17>, <29>;
>> +				clock-output-names = "bus_gmac", "bus_ohci0";
>> +			};
>> +			apb1_parent {
>> +				clocks = <&apb1>;
>> +				clock-indices = <64>, <65>,
>> +						<69>, <72>,
>> +						<76>, <77>,
>> +						<78>;
>> +				clock-output-names = "bus_codec", "bus_spdif",
>> +						"bus_pio", "bus_ths",
>> +						"bus_i2s0", "bus_i2s1",
>> +						"bus_i2s2";
>> +			};
>> +			abp2_parent {
>> +				clocks = <&apb2>;
>> +				clock-indices = <96>, <97>,
>> +						<98>, <101>,
>> +						<112>, <113>,
>> +						<114>, <115>,
>> +						<116>;
>> +				clock-output-names = "bus_i2c0", "bus_i2c1",
>> +						"bus_i2c2", "bus_scr",
>> +						"bus_uart0", "bus_uart1",
>> +						"bus_uart2", "bus_uart3",
>> +						"bus_uart4";
>> +			};
>> +		};
>> +
>> +		mmc0_clk: clk@01c20088 {
>> +			#clock-cells = <1>;
>> +			compatible = "allwinner,sun4i-a10-mmc-clk";
>> +			reg = <0x01c20088 0x4>;
>> +			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>> +			clock-output-names = "mmc0",
>> +					     "mmc0_output",
>> +					     "mmc0_sample";
>> +		};
>> +
>> +		mmc1_clk: clk@01c2008c {
>> +			#clock-cells = <1>;
>> +			compatible = "allwinner,sun4i-a10-mmc-clk";
>> +			reg = <0x01c2008c 0x4>;
>> +			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>> +			clock-output-names = "mmc1",
>> +					     "mmc1_output",
>> +					     "mmc1_sample";
>> +		};
>> +
>> +		mmc2_clk: clk@01c20090 {
>> +			#clock-cells = <1>;
>> +			compatible = "allwinner,sun4i-a10-mmc-clk";
>> +			reg = <0x01c20090 0x4>;
>> +			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>> +			clock-output-names = "mmc2",
>> +					     "mmc2_output",
>> +					     "mmc2_sample";
>> +		};
>> +	};
>> +
>> +	regulators {
>> +		reg_vcc3v3: vcc3v3 {
>> +			compatible = "regulator-fixed";
>> +			regulator-name = "vcc3v3";
>> +			regulator-min-microvolt = <3300000>;
>> +			regulator-max-microvolt = <3300000>;
>> +		};
>> +	};
>> +
>> +	soc {
>> +		compatible = "simple-bus";
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges;
>> +
>> +		mmc0: mmc@01c0f000 {
>> +			compatible = "allwinner,sun5i-a13-mmc";
>> +			reg = <0x01c0f000 0x1000>;
>> +			clocks = <&bus_gates 8>,
>> +				 <&mmc0_clk 0>,
>> +				 <&mmc0_clk 1>,
>> +				 <&mmc0_clk 2>;
>> +			clock-names = "ahb",
>> +				      "mmc",
>> +				      "output",
>> +				      "sample";
>> +			resets = <&ahb_rst 8>;
>> +			reset-names = "ahb";
>> +			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		mmc1: mmc@01c10000 {
>> +			compatible = "allwinner,sun5i-a13-mmc";
>> +			reg = <0x01c10000 0x1000>;
>> +			clocks = <&bus_gates 9>,
>> +				 <&mmc1_clk 0>,
>> +				 <&mmc1_clk 1>,
>> +				 <&mmc1_clk 2>;
>> +			clock-names = "ahb",
>> +				      "mmc",
>> +				      "output",
>> +				      "sample";
>> +			resets = <&ahb_rst 9>;
>> +			reset-names = "ahb";
>> +			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		mmc2: mmc@01c11000 {
>> +			compatible = "allwinner,sun5i-a13-mmc";
>> +			reg = <0x01c11000 0x1000>;
>> +			clocks = <&bus_gates 10>,
>> +				 <&mmc2_clk 0>,
>> +				 <&mmc2_clk 1>,
>> +				 <&mmc2_clk 2>;
>> +			clock-names = "ahb",
>> +				      "mmc",
>> +				      "output",
>> +				      "sample";
>> +			resets = <&ahb_rst 10>;
>> +			reset-names = "ahb";
>> +			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		pio: pinctrl@01c20800 {
>> +			compatible = "allwinner,a64-pinctrl";
> 
> see above
> 
>> +			reg = <0x01c20800 0x400>;
>> +			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&bus_gates 69>;
>> +			gpio-controller;
>> +			#gpio-cells = <3>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +
>> +			uart0_pins_a: uart0@0 {
>> +				allwinner,pins = "PB8", "PB9";
>> +				allwinner,function = "uart0";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			uart0_pins_b: uart0@1 {
>> +				allwinner,pins = "PF2", "PF3";
>> +				allwinner,function = "uart0";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			uart1_pins: uart1@0 {
>> +				allwinner,pins = "PG6", "PG7", "PG8", "PG9";
>> +				allwinner,function = "uart1";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			uart2_pins: uart2@0 {
>> +				allwinner,pins = "PB0", "PB1", "PB2", "PB3";
>> +				allwinner,function = "uart2";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			uart3_pins_a: uart3@0 {
>> +				allwinner,pins = "PD0", "PD1";
>> +				allwinner,function = "uart3";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			uart3_pins_b: uart3@1 {
>> +				allwinner,pins = "PH4", "PH5", "PH6", "PH7";
>> +				allwinner,function = "uart3";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			uart4_pins: uart4@0 {
>> +				allwinner,pins = "PD2", "PD3", "PD4", "PD5";
>> +				allwinner,function = "uart4";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			mmc0_pins: mmc0@0 {
>> +				allwinner,pins = "PF0", "PF1", "PF2", "PF3",
>> +						 "PF4", "PF5";
>> +				allwinner,function = "mmc0";
>> +				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			mmc0_default_cd_pin: mmc0_cd_pin@0 {
>> +				allwinner,pins = "PF6";
>> +				allwinner,function = "gpio_in";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
>> +			};
>> +
>> +			mmc1_pins: mmc1@0 {
>> +				allwinner,pins = "PG0", "PG1", "PG2", "PG3",
>> +						 "PG4", "PG5";
>> +				allwinner,function = "mmc1";
>> +				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			mmc2_pins: mmc2@0 {
>> +				allwinner,pins = "PC1", "PC5", "PC6", "PC8",
>> +						 "PC9", "PC10";
>> +				allwinner,function = "mmc2";
>> +				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +		};
>> +
>> +		ahb_rst: reset@01c202c0 {
>> +			#reset-cells = <1>;
>> +			compatible = "allwinner,sun6i-a31-ahb1-reset";
>> +			reg = <0x01c202c0 0xc>;
>> +		};
>> +
>> +		apb1_rst: reset@01c202d0 {
>> +			#reset-cells = <1>;
>> +			compatible = "allwinner,sun6i-a31-clock-reset";
>> +			reg = <0x01c202d0 0x4>;
>> +		};
>> +
>> +		apb2_rst: reset@01c202d8 {
>> +			#reset-cells = <1>;
>> +			compatible = "allwinner,sun6i-a31-clock-reset";
>> +			reg = <0x01c202d8 0x4>;
>> +		};
>> +
>> +		uart0: serial@01c28000 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c28000 0x400>;
>> +			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&bus_gates 112>;
>> +			resets = <&apb2_rst 16>;
>> +			reset-names = "apb2";
>> +			status = "disabled";
>> +		};
>> +
>> +		uart1: serial@01c28400 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c28400 0x400>;
>> +			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&bus_gates 113>;
>> +			resets = <&apb2_rst 17>;
>> +			reset-names = "apb2";
>> +			status = "disabled";
>> +		};
>> +
>> +		uart2: serial@01c28800 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c28800 0x400>;
>> +			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&bus_gates 114>;
>> +			resets = <&apb2_rst 18>;
>> +			reset-names = "apb2";
>> +			status = "disabled";
>> +		};
>> +
>> +		uart3: serial@01c28c00 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c28c00 0x400>;
>> +			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&bus_gates 115>;
>> +			resets = <&apb2_rst 19>;
>> +			reset-names = "apb2";
>> +			status = "disabled";
>> +		};
>> +
>> +		uart4: serial@01c29000 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c29000 0x400>;
>> +			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&bus_gates 116>;
>> +			resets = <&apb2_rst 20>;
>> +			reset-names = "apb2";
>> +			status = "disabled";
>> +		};
>> +
>> +		rtc: rtc@01f00000 {
>> +			compatible = "allwinner,sun6i-a31-rtc";
>> +			reg = <0x01f00000 0x54>;
>> +			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
>> +		};
>> +	};
>> +
>> +	gic: interrupt-controller@{
>> +		compatible = "arm,gic-400";
>> +		interrupt-controller;
>> +		#interrupt-cells = <3>;
>> +		#address-cells = <0>;
>> +
>> +		reg = <0x01C81000 0x1000>,
>> +		      <0x01C82000 0x2000>,
>> +		      <0x01C84000 0x2000>,
>> +		      <0x01C86000 0x2000>;
>> +		interrupts = <GIC_PPI 9
>> +		      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> +	};
>> +};
>> -- 
>> 2.6.4
> 
> Regards,
> Karsten
> 

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Re: [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi

[Jens Kuske]

Hi,

On 01/02/16 18:39, Andre Przywara wrote:
> The Allwinner A64 SoC is low-cost SoC with 4 ARM Cortex-A53 cores
> and the typical tablet / TV box peripherals.
> The Soc is based on the (32-bit) Allwinner H3 chip, sharing most of
> the peripherals and the memory map.
> Although the cores are proper 64-bit ones, the whole SoC is actually
> limited to 4GB (including all the supported DRAM), so we use 32-bit
> address and size cells. This has the nice feature of us being able to
> reuse the DT for 32-bit kernels as well.
> This .dtsi lists the hardware that we support so far.
> 
> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/arm/sunxi.txt   |   1 +
>  Documentation/devicetree/bindings/clock/sunxi.txt |   1 +
>  arch/arm64/boot/dts/allwinner/a64.dtsi            | 583 ++++++++++++++++++++++
>  3 files changed, 585 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/allwinner/a64.dtsi
> 
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
> index 980e065..4a83853 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> @@ -14,6 +14,7 @@ using one of the following compatible strings:
>    allwinner,sun8i-a83t
>    allwinner,sun8i-h3
>    allwinner,sun9i-a80
> +  allwinner,a64
>  
>  For Allwinner SoCs without any specific needs the generic fallback value of:
>    allwinner,sunxi
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index e59f57b..44b0c6c 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -77,6 +77,7 @@ Required properties:
>  	"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
>  	"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
>  	"allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
> +	"allwinner,a64-bus-gates-clk" - for the A64 multi-parent bus gates clock
>  
>  Required properties for all clocks:
>  - reg : shall be the control register address for the clock.
> diff --git a/arch/arm64/boot/dts/allwinner/a64.dtsi b/arch/arm64/boot/dts/allwinner/a64.dtsi
> new file mode 100644
> index 0000000..8dce10f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/a64.dtsi
> @@ -0,0 +1,583 @@
> +/*
> + * Copyright (C) 2016 ARM Ltd.
> + * based on the Allwinner H3 dtsi:
> + *    Copyright (C) 2015 Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
> +
> +/ {
> +	compatible = "allwinner,a64", "allwinner,sunxi";
> +	interrupt-parent = <&gic>;
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +		serial4 = &uart4;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <0>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu@1 {
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <1>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu@2 {
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <2>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu@3 {
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <3>;
> +			enable-method = "psci";
> +		};
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-0.2", "arm,psci";
> +		method = "smc";
> +		cpu_suspend = <0xc4000001>;
> +		cpu_off = <0x84000002>;
> +		cpu_on = <0xc4000003>;
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x40000000 0>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13
> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> +			     <GIC_PPI 14
> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> +			     <GIC_PPI 11
> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> +			     <GIC_PPI 10
> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +	};
> +
> +	clocks {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		osc24M: osc24M_clk {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <24000000>;
> +			clock-output-names = "osc24M";
> +		};
> +
> +		osc32k: osc32k_clk {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <32768>;
> +			clock-output-names = "osc32k";
> +		};
> +
> +		pll1: clk@01c20000 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun8i-a23-pll1-clk";
> +			reg = <0x01c20000 0x4>;
> +			clocks = <&osc24M>;
> +			clock-output-names = "pll1";
> +		};
> +
> +		pll6: clk@01c20028 {
> +			#clock-cells = <1>;
> +			compatible = "allwinner,sun6i-a31-pll6-clk";
> +			reg = <0x01c20028 0x4>;
> +			clocks = <&osc24M>;
> +			clock-output-names = "pll6", "pll6x2";
> +		};
> +
> +		pll6d2: pll6d2_clk {
> +			#clock-cells = <0>;
> +			compatible = "fixed-factor-clock";
> +			clock-div = <2>;
> +			clock-mult = <1>;
> +			clocks = <&pll6 0>;
> +			clock-output-names = "pll6d2";
> +		};
> +
> +		/* dummy clock until pll6 can be reused */
> +		pll8: pll8_clk {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <1>;
> +			clock-output-names = "pll8";
> +		};
> +
> +		cpu: cpu_clk@01c20050 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-cpu-clk";
> +			reg = <0x01c20050 0x4>;
> +			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
> +			clock-output-names = "cpu";
> +			critical-clocks = <0>;
> +		};
> +
> +		axi: axi_clk@01c20050 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-axi-clk";
> +			reg = <0x01c20050 0x4>;
> +			clocks = <&cpu>;
> +			clock-output-names = "axi";
> +		};
> +
> +		ahb1: ahb1_clk@01c20054 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun6i-a31-ahb1-clk";
> +			reg = <0x01c20054 0x4>;
> +			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
> +			clock-output-names = "ahb1";
> +		};
> +
> +		ahb2: ahb2_clk@01c2005c {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun8i-h3-ahb2-clk";
> +			reg = <0x01c2005c 0x4>;
> +			clocks = <&ahb1>, <&pll6d2>;
> +			clock-output-names = "ahb2";
> +		};
> +
> +		apb1: apb1_clk@01c20054 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-apb0-clk";
> +			reg = <0x01c20054 0x4>;
> +			clocks = <&ahb1>;
> +			clock-output-names = "apb1";
> +		};
> +
> +		apb2: apb2_clk@01c20058 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-apb1-clk";
> +			reg = <0x01c20058 0x4>;
> +			clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
> +			clock-output-names = "apb2";
> +		};
> +
> +		bus_gates: clk@01c20060 {
> +			#clock-cells = <1>;
> +			compatible = "allwinner,a64-bus-gates-clk",
> +				     "allwinner,sunxi-multi-bus-gates-clk";
> +			reg = <0x01c20060 0x14>;
> +			ahb1_parent {
> +				clocks = <&ahb1>;
> +				clock-indices = <1>, <5>,
> +						<6>, <8>,
> +						<9>, <10>,
> +						<13>, <14>,
> +						<18>, <19>,
> +						<20>, <21>,
> +						<23>, <24>,
> +						<25>, <28>,
> +						<32>, <35>,
> +						<36>, <37>,
> +						<40>, <43>,
> +						<44>, <52>,
> +						<53>, <54>,
> +						<135>;
> +				clock-output-names = "bus_mipidsi", "bus_ce",
> +						"bus_dma", "bus_mmc0",
> +						"bus_mmc1", "bus_mmc2",
> +						"bus_nand", "bus_sdram",
> +						"bus_ts", "bus_hstimer",
> +						"bus_spi0", "bus_spi1",
> +						"bus_otg", "bus_otg_ehci0",
> +						"bus_ehci0", "bus_otg_ohci0",
> +						"bus_ve", "bus_lcd0",
> +						"bus_lcd1", "bus_deint",
> +						"bus_csi", "bus_hdmi",
> +						"bus_de", "bus_gpu",
> +						"bus_msgbox", "bus_spinlock",
> +						"bus_dbg";
> +			};
> +			ahb2_parent {
> +				clocks = <&ahb2>;
> +				clock-indices = <17>, <29>;
> +				clock-output-names = "bus_gmac", "bus_ohci0";
> +			};
> +			apb1_parent {
> +				clocks = <&apb1>;
> +				clock-indices = <64>, <65>,
> +						<69>, <72>,
> +						<76>, <77>,
> +						<78>;
> +				clock-output-names = "bus_codec", "bus_spdif",
> +						"bus_pio", "bus_ths",
> +						"bus_i2s0", "bus_i2s1",
> +						"bus_i2s2";
> +			};
> +			abp2_parent {
> +				clocks = <&apb2>;
> +				clock-indices = <96>, <97>,
> +						<98>, <101>,
> +						<112>, <113>,
> +						<114>, <115>,
> +						<116>;
> +				clock-output-names = "bus_i2c0", "bus_i2c1",
> +						"bus_i2c2", "bus_scr",
> +						"bus_uart0", "bus_uart1",
> +						"bus_uart2", "bus_uart3",
> +						"bus_uart4";
> +			};
> +		};
> +
> +		mmc0_clk: clk@01c20088 {
> +			#clock-cells = <1>;
> +			compatible = "allwinner,sun4i-a10-mmc-clk";

The A64 MMC clocks don't seem to be fully compatible to A10. The output
and sample phase control has been moved to the MMC module itself.
The dividers are the same, but the additional special "outputs" are gone.

> +			reg = <0x01c20088 0x4>;
> +			clocks = <&osc24M>, <&pll6 0>, <&pll8>;

Parents are PLL6(2x) and PLL8(2x) according to manual.

> +			clock-output-names = "mmc0",
> +					     "mmc0_output",
> +					     "mmc0_sample";
> +		};
> +
> +		mmc1_clk: clk@01c2008c {
> +			#clock-cells = <1>;
> +			compatible = "allwinner,sun4i-a10-mmc-clk";
> +			reg = <0x01c2008c 0x4>;
> +			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
> +			clock-output-names = "mmc1",
> +					     "mmc1_output",
> +					     "mmc1_sample";
> +		};
> +
> +		mmc2_clk: clk@01c20090 {
> +			#clock-cells = <1>;
> +			compatible = "allwinner,sun4i-a10-mmc-clk";
> +			reg = <0x01c20090 0x4>;
> +			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
> +			clock-output-names = "mmc2",
> +					     "mmc2_output",
> +					     "mmc2_sample";
> +		};
> +	};
> +
> +	regulators {
> +		reg_vcc3v3: vcc3v3 {
> +			compatible = "regulator-fixed";
> +			regulator-name = "vcc3v3";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +		};
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		mmc0: mmc@01c0f000 {
> +			compatible = "allwinner,sun5i-a13-mmc";
> +			reg = <0x01c0f000 0x1000>;
> +			clocks = <&bus_gates 8>,
> +				 <&mmc0_clk 0>,

Consequently, the MMC driver now has to control the output/sample phase
with registers 0x140-0x148 instead of
> +				 <&mmc0_clk 1>,
> +				 <&mmc0_clk 2>;

And there seems to be some new clock divider somewhere which I haven't
found in the manual yet. The clock measured at the CLK pin is always
half the expected rate (even with 24MHz as MMC clock parent, so no
PLL6*2 problem).

> +			clock-names = "ahb",
> +				      "mmc",
> +				      "output",
> +				      "sample";
> +			resets = <&ahb_rst 8>;
> +			reset-names = "ahb";
> +			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		mmc1: mmc@01c10000 {
> +			compatible = "allwinner,sun5i-a13-mmc";
> +			reg = <0x01c10000 0x1000>;
> +			clocks = <&bus_gates 9>,
> +				 <&mmc1_clk 0>,
> +				 <&mmc1_clk 1>,
> +				 <&mmc1_clk 2>;
> +			clock-names = "ahb",
> +				      "mmc",
> +				      "output",
> +				      "sample";
> +			resets = <&ahb_rst 9>;
> +			reset-names = "ahb";
> +			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		mmc2: mmc@01c11000 {
> +			compatible = "allwinner,sun5i-a13-mmc";
> +			reg = <0x01c11000 0x1000>;
> +			clocks = <&bus_gates 10>,
> +				 <&mmc2_clk 0>,
> +				 <&mmc2_clk 1>,
> +				 <&mmc2_clk 2>;
> +			clock-names = "ahb",
> +				      "mmc",
> +				      "output",
> +				      "sample";
> +			resets = <&ahb_rst 10>;
> +			reset-names = "ahb";
> +			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		pio: pinctrl@01c20800 {
> +			compatible = "allwinner,a64-pinctrl";
> +			reg = <0x01c20800 0x400>;
> +			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&bus_gates 69>;
> +			gpio-controller;
> +			#gpio-cells = <3>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +
> +			uart0_pins_a: uart0@0 {
> +				allwinner,pins = "PB8", "PB9";
> +				allwinner,function = "uart0";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			uart0_pins_b: uart0@1 {
> +				allwinner,pins = "PF2", "PF3";
> +				allwinner,function = "uart0";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			uart1_pins: uart1@0 {
> +				allwinner,pins = "PG6", "PG7", "PG8", "PG9";
> +				allwinner,function = "uart1";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			uart2_pins: uart2@0 {
> +				allwinner,pins = "PB0", "PB1", "PB2", "PB3";
> +				allwinner,function = "uart2";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			uart3_pins_a: uart3@0 {
> +				allwinner,pins = "PD0", "PD1";
> +				allwinner,function = "uart3";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			uart3_pins_b: uart3@1 {
> +				allwinner,pins = "PH4", "PH5", "PH6", "PH7";
> +				allwinner,function = "uart3";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			uart4_pins: uart4@0 {
> +				allwinner,pins = "PD2", "PD3", "PD4", "PD5";
> +				allwinner,function = "uart4";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			mmc0_pins: mmc0@0 {
> +				allwinner,pins = "PF0", "PF1", "PF2", "PF3",
> +						 "PF4", "PF5";
> +				allwinner,function = "mmc0";
> +				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			mmc0_default_cd_pin: mmc0_cd_pin@0 {
> +				allwinner,pins = "PF6";
> +				allwinner,function = "gpio_in";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
> +			};
> +
> +			mmc1_pins: mmc1@0 {
> +				allwinner,pins = "PG0", "PG1", "PG2", "PG3",
> +						 "PG4", "PG5";
> +				allwinner,function = "mmc1";
> +				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			mmc2_pins: mmc2@0 {
> +				allwinner,pins = "PC1", "PC5", "PC6", "PC8",
> +						 "PC9", "PC10";
> +				allwinner,function = "mmc2";
> +				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +		};
> +
> +		ahb_rst: reset@01c202c0 {
> +			#reset-cells = <1>;
> +			compatible = "allwinner,sun6i-a31-ahb1-reset";
> +			reg = <0x01c202c0 0xc>;
> +		};
> +
> +		apb1_rst: reset@01c202d0 {
> +			#reset-cells = <1>;
> +			compatible = "allwinner,sun6i-a31-clock-reset";
> +			reg = <0x01c202d0 0x4>;
> +		};
> +
> +		apb2_rst: reset@01c202d8 {
> +			#reset-cells = <1>;
> +			compatible = "allwinner,sun6i-a31-clock-reset";
> +			reg = <0x01c202d8 0x4>;
> +		};
> +
> +		uart0: serial@01c28000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c28000 0x400>;
> +			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&bus_gates 112>;
> +			resets = <&apb2_rst 16>;
> +			reset-names = "apb2";

Do we need reset-names here (and below)?

> +			status = "disabled";
> +		};
> +
> +		uart1: serial@01c28400 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c28400 0x400>;
> +			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&bus_gates 113>;
> +			resets = <&apb2_rst 17>;
> +			reset-names = "apb2";
> +			status = "disabled";
> +		};
> +
> +		uart2: serial@01c28800 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c28800 0x400>;
> +			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&bus_gates 114>;
> +			resets = <&apb2_rst 18>;
> +			reset-names = "apb2";
> +			status = "disabled";
> +		};
> +
> +		uart3: serial@01c28c00 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c28c00 0x400>;
> +			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&bus_gates 115>;
> +			resets = <&apb2_rst 19>;
> +			reset-names = "apb2";
> +			status = "disabled";
> +		};
> +
> +		uart4: serial@01c29000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c29000 0x400>;
> +			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&bus_gates 116>;
> +			resets = <&apb2_rst 20>;
> +			reset-names = "apb2";
> +			status = "disabled";
> +		};
> +
> +		rtc: rtc@01f00000 {
> +			compatible = "allwinner,sun6i-a31-rtc";
> +			reg = <0x01f00000 0x54>;
> +			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +	};
> +
> +	gic: interrupt-controller@{
> +		compatible = "arm,gic-400";
> +		interrupt-controller;
> +		#interrupt-cells = <3>;
> +		#address-cells = <0>;
> +
> +		reg = <0x01C81000 0x1000>,
> +		      <0x01C82000 0x2000>,
> +		      <0x01C84000 0x2000>,
> +		      <0x01C86000 0x2000>;

Maybe lowercase hex here too.

> +		interrupts = <GIC_PPI 9
> +		      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +	};
> +};
> 

Regards,
Jens

Re: [linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi

[Andre Przywara]

Hi Jens,

thanks for having such an elaborate look!

On 02/02/16 16:24, Jens Kuske wrote:
> Hi,
> 
> On 01/02/16 18:39, Andre Przywara wrote:
>> The Allwinner A64 SoC is low-cost SoC with 4 ARM Cortex-A53 cores
>> and the typical tablet / TV box peripherals.
>> The Soc is based on the (32-bit) Allwinner H3 chip, sharing most of
>> the peripherals and the memory map.
>> Although the cores are proper 64-bit ones, the whole SoC is actually
>> limited to 4GB (including all the supported DRAM), so we use 32-bit
>> address and size cells. This has the nice feature of us being able to
>> reuse the DT for 32-bit kernels as well.
>> This .dtsi lists the hardware that we support so far.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>> ---
>>  Documentation/devicetree/bindings/arm/sunxi.txt   |   1 +
>>  Documentation/devicetree/bindings/clock/sunxi.txt |   1 +
>>  arch/arm64/boot/dts/allwinner/a64.dtsi            | 583 ++++++++++++++++++++++
>>  3 files changed, 585 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/allwinner/a64.dtsi
>>
>> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
>> index 980e065..4a83853 100644
>> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
>> @@ -14,6 +14,7 @@ using one of the following compatible strings:
>>    allwinner,sun8i-a83t
>>    allwinner,sun8i-h3
>>    allwinner,sun9i-a80
>> +  allwinner,a64
>>  
>>  For Allwinner SoCs without any specific needs the generic fallback value of:
>>    allwinner,sunxi
>> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
>> index e59f57b..44b0c6c 100644
>> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>> @@ -77,6 +77,7 @@ Required properties:
>>  	"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
>>  	"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
>>  	"allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
>> +	"allwinner,a64-bus-gates-clk" - for the A64 multi-parent bus gates clock
>>  
>>  Required properties for all clocks:
>>  - reg : shall be the control register address for the clock.
>> diff --git a/arch/arm64/boot/dts/allwinner/a64.dtsi b/arch/arm64/boot/dts/allwinner/a64.dtsi
>> new file mode 100644
>> index 0000000..8dce10f
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/allwinner/a64.dtsi
>> @@ -0,0 +1,583 @@
>> +/*
>> + * Copyright (C) 2016 ARM Ltd.
>> + * based on the Allwinner H3 dtsi:
>> + *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This file is free software; you can redistribute it and/or
>> + *     modify it under the terms of the GNU General Public License as
>> + *     published by the Free Software Foundation; either version 2 of the
>> + *     License, or (at your option) any later version.
>> + *
>> + *     This file is distributed in the hope that it will be useful,
>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + *     GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + *     obtaining a copy of this software and associated documentation
>> + *     files (the "Software"), to deal in the Software without
>> + *     restriction, including without limitation the rights to use,
>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
>> + *     sell copies of the Software, and to permit persons to whom the
>> + *     Software is furnished to do so, subject to the following
>> + *     conditions:
>> + *
>> + *     The above copyright notice and this permission notice shall be
>> + *     included in all copies or substantial portions of the Software.
>> + *
>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + *     OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/pinctrl/sun4i-a10.h>
>> +
>> +/ {
>> +	compatible = "allwinner,a64", "allwinner,sunxi";
>> +	interrupt-parent = <&gic>;
>> +	#address-cells = <1>;
>> +	#size-cells = <1>;
>> +
>> +	aliases {
>> +		serial0 = &uart0;
>> +		serial1 = &uart1;
>> +		serial2 = &uart2;
>> +		serial3 = &uart3;
>> +		serial4 = &uart4;
>> +	};
>> +
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		cpu@0 {
>> +			compatible = "arm,cortex-a53", "arm,armv8";
>> +			device_type = "cpu";
>> +			reg = <0>;
>> +			enable-method = "psci";
>> +		};
>> +
>> +		cpu@1 {
>> +			compatible = "arm,cortex-a53", "arm,armv8";
>> +			device_type = "cpu";
>> +			reg = <1>;
>> +			enable-method = "psci";
>> +		};
>> +
>> +		cpu@2 {
>> +			compatible = "arm,cortex-a53", "arm,armv8";
>> +			device_type = "cpu";
>> +			reg = <2>;
>> +			enable-method = "psci";
>> +		};
>> +
>> +		cpu@3 {
>> +			compatible = "arm,cortex-a53", "arm,armv8";
>> +			device_type = "cpu";
>> +			reg = <3>;
>> +			enable-method = "psci";
>> +		};
>> +	};
>> +
>> +	psci {
>> +		compatible = "arm,psci-0.2", "arm,psci";
>> +		method = "smc";
>> +		cpu_suspend = <0xc4000001>;
>> +		cpu_off = <0x84000002>;
>> +		cpu_on = <0xc4000003>;
>> +	};
>> +
>> +	memory {
>> +		device_type = "memory";
>> +		reg = <0x40000000 0>;
>> +	};
>> +
>> +	timer {
>> +		compatible = "arm,armv8-timer";
>> +		interrupts = <GIC_PPI 13
>> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>> +			     <GIC_PPI 14
>> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>> +			     <GIC_PPI 11
>> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>> +			     <GIC_PPI 10
>> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> +	};
>> +
>> +	clocks {
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges;
>> +
>> +		osc24M: osc24M_clk {
>> +			#clock-cells = <0>;
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <24000000>;
>> +			clock-output-names = "osc24M";
>> +		};
>> +
>> +		osc32k: osc32k_clk {
>> +			#clock-cells = <0>;
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <32768>;
>> +			clock-output-names = "osc32k";
>> +		};
>> +
>> +		pll1: clk@01c20000 {
>> +			#clock-cells = <0>;
>> +			compatible = "allwinner,sun8i-a23-pll1-clk";
>> +			reg = <0x01c20000 0x4>;
>> +			clocks = <&osc24M>;
>> +			clock-output-names = "pll1";
>> +		};
>> +
>> +		pll6: clk@01c20028 {
>> +			#clock-cells = <1>;
>> +			compatible = "allwinner,sun6i-a31-pll6-clk";
>> +			reg = <0x01c20028 0x4>;
>> +			clocks = <&osc24M>;
>> +			clock-output-names = "pll6", "pll6x2";
>> +		};
>> +
>> +		pll6d2: pll6d2_clk {
>> +			#clock-cells = <0>;
>> +			compatible = "fixed-factor-clock";
>> +			clock-div = <2>;
>> +			clock-mult = <1>;
>> +			clocks = <&pll6 0>;
>> +			clock-output-names = "pll6d2";
>> +		};
>> +
>> +		/* dummy clock until pll6 can be reused */
>> +		pll8: pll8_clk {
>> +			#clock-cells = <0>;
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <1>;
>> +			clock-output-names = "pll8";
>> +		};

Since I have you (as the original author ;-) in the loop: What was again
the reason for this dummy clock? Can't it be modelled with the existing
clock drivers in Linux?

>> +
>> +		cpu: cpu_clk@01c20050 {
>> +			#clock-cells = <0>;
>> +			compatible = "allwinner,sun4i-a10-cpu-clk";
>> +			reg = <0x01c20050 0x4>;
>> +			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
>> +			clock-output-names = "cpu";
>> +			critical-clocks = <0>;
>> +		};
>> +
>> +		axi: axi_clk@01c20050 {
>> +			#clock-cells = <0>;
>> +			compatible = "allwinner,sun4i-a10-axi-clk";
>> +			reg = <0x01c20050 0x4>;
>> +			clocks = <&cpu>;
>> +			clock-output-names = "axi";
>> +		};
>> +
>> +		ahb1: ahb1_clk@01c20054 {
>> +			#clock-cells = <0>;
>> +			compatible = "allwinner,sun6i-a31-ahb1-clk";
>> +			reg = <0x01c20054 0x4>;
>> +			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
>> +			clock-output-names = "ahb1";
>> +		};
>> +
>> +		ahb2: ahb2_clk@01c2005c {
>> +			#clock-cells = <0>;
>> +			compatible = "allwinner,sun8i-h3-ahb2-clk";
>> +			reg = <0x01c2005c 0x4>;
>> +			clocks = <&ahb1>, <&pll6d2>;
>> +			clock-output-names = "ahb2";
>> +		};
>> +
>> +		apb1: apb1_clk@01c20054 {
>> +			#clock-cells = <0>;
>> +			compatible = "allwinner,sun4i-a10-apb0-clk";
>> +			reg = <0x01c20054 0x4>;
>> +			clocks = <&ahb1>;
>> +			clock-output-names = "apb1";
>> +		};
>> +
>> +		apb2: apb2_clk@01c20058 {
>> +			#clock-cells = <0>;
>> +			compatible = "allwinner,sun4i-a10-apb1-clk";
>> +			reg = <0x01c20058 0x4>;
>> +			clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
>> +			clock-output-names = "apb2";
>> +		};
>> +
>> +		bus_gates: clk@01c20060 {
>> +			#clock-cells = <1>;
>> +			compatible = "allwinner,a64-bus-gates-clk",
>> +				     "allwinner,sunxi-multi-bus-gates-clk";
>> +			reg = <0x01c20060 0x14>;
>> +			ahb1_parent {
>> +				clocks = <&ahb1>;
>> +				clock-indices = <1>, <5>,
>> +						<6>, <8>,
>> +						<9>, <10>,
>> +						<13>, <14>,
>> +						<18>, <19>,
>> +						<20>, <21>,
>> +						<23>, <24>,
>> +						<25>, <28>,
>> +						<32>, <35>,
>> +						<36>, <37>,
>> +						<40>, <43>,
>> +						<44>, <52>,
>> +						<53>, <54>,
>> +						<135>;
>> +				clock-output-names = "bus_mipidsi", "bus_ce",
>> +						"bus_dma", "bus_mmc0",
>> +						"bus_mmc1", "bus_mmc2",
>> +						"bus_nand", "bus_sdram",
>> +						"bus_ts", "bus_hstimer",
>> +						"bus_spi0", "bus_spi1",
>> +						"bus_otg", "bus_otg_ehci0",
>> +						"bus_ehci0", "bus_otg_ohci0",
>> +						"bus_ve", "bus_lcd0",
>> +						"bus_lcd1", "bus_deint",
>> +						"bus_csi", "bus_hdmi",
>> +						"bus_de", "bus_gpu",
>> +						"bus_msgbox", "bus_spinlock",
>> +						"bus_dbg";
>> +			};
>> +			ahb2_parent {
>> +				clocks = <&ahb2>;
>> +				clock-indices = <17>, <29>;
>> +				clock-output-names = "bus_gmac", "bus_ohci0";
>> +			};
>> +			apb1_parent {
>> +				clocks = <&apb1>;
>> +				clock-indices = <64>, <65>,
>> +						<69>, <72>,
>> +						<76>, <77>,
>> +						<78>;
>> +				clock-output-names = "bus_codec", "bus_spdif",
>> +						"bus_pio", "bus_ths",
>> +						"bus_i2s0", "bus_i2s1",
>> +						"bus_i2s2";
>> +			};
>> +			abp2_parent {
>> +				clocks = <&apb2>;
>> +				clock-indices = <96>, <97>,
>> +						<98>, <101>,
>> +						<112>, <113>,
>> +						<114>, <115>,
>> +						<116>;
>> +				clock-output-names = "bus_i2c0", "bus_i2c1",
>> +						"bus_i2c2", "bus_scr",
>> +						"bus_uart0", "bus_uart1",
>> +						"bus_uart2", "bus_uart3",
>> +						"bus_uart4";
>> +			};
>> +		};
>> +
>> +		mmc0_clk: clk@01c20088 {
>> +			#clock-cells = <1>;
>> +			compatible = "allwinner,sun4i-a10-mmc-clk";
> 
> The A64 MMC clocks don't seem to be fully compatible to A10. The output
> and sample phase control has been moved to the MMC module itself.
> The dividers are the same, but the additional special "outputs" are gone.

So from comparing the H3 and the A64 datasheet I see that this is one of
the rare deviations of the A64 from the H3?

>> +			reg = <0x01c20088 0x4>;
>> +			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
> 
> Parents are PLL6(2x) and PLL8(2x) according to manual.

Indeed, thanks for pointing this out! So do we need a proper pll8 clock?

> 
>> +			clock-output-names = "mmc0",
>> +					     "mmc0_output",
>> +					     "mmc0_sample";
>> +		};
>> +
>> +		mmc1_clk: clk@01c2008c {
>> +			#clock-cells = <1>;
>> +			compatible = "allwinner,sun4i-a10-mmc-clk";
>> +			reg = <0x01c2008c 0x4>;
>> +			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>> +			clock-output-names = "mmc1",
>> +					     "mmc1_output",
>> +					     "mmc1_sample";
>> +		};
>> +
>> +		mmc2_clk: clk@01c20090 {
>> +			#clock-cells = <1>;
>> +			compatible = "allwinner,sun4i-a10-mmc-clk";
>> +			reg = <0x01c20090 0x4>;
>> +			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>> +			clock-output-names = "mmc2",
>> +					     "mmc2_output",
>> +					     "mmc2_sample";
>> +		};
>> +	};
>> +
>> +	regulators {
>> +		reg_vcc3v3: vcc3v3 {
>> +			compatible = "regulator-fixed";
>> +			regulator-name = "vcc3v3";
>> +			regulator-min-microvolt = <3300000>;
>> +			regulator-max-microvolt = <3300000>;
>> +		};
>> +	};
>> +
>> +	soc {
>> +		compatible = "simple-bus";
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges;
>> +
>> +		mmc0: mmc@01c0f000 {
>> +			compatible = "allwinner,sun5i-a13-mmc";
>> +			reg = <0x01c0f000 0x1000>;
>> +			clocks = <&bus_gates 8>,
>> +				 <&mmc0_clk 0>,
> 
> Consequently, the MMC driver now has to control the output/sample phase
> with registers 0x140-0x148 instead of
>> +				 <&mmc0_clk 1>,
>> +				 <&mmc0_clk 2>;

OK, good point. I was just briefly browsing over the register
descriptions and missed that.
So it looks like I need to change the driver. Interestingly it seems to
work anyways ...

> And there seems to be some new clock divider somewhere which I haven't
> found in the manual yet. The clock measured at the CLK pin is always
> half the expected rate (even with 24MHz as MMC clock parent, so no
> PLL6*2 problem).

Mmh, I heard about that mysterious clock doubling / halving already. Was
that actually causing any issues?

> 
>> +			clock-names = "ahb",
>> +				      "mmc",
>> +				      "output",
>> +				      "sample";
>> +			resets = <&ahb_rst 8>;
>> +			reset-names = "ahb";
>> +			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		mmc1: mmc@01c10000 {
>> +			compatible = "allwinner,sun5i-a13-mmc";
>> +			reg = <0x01c10000 0x1000>;
>> +			clocks = <&bus_gates 9>,
>> +				 <&mmc1_clk 0>,
>> +				 <&mmc1_clk 1>,
>> +				 <&mmc1_clk 2>;
>> +			clock-names = "ahb",
>> +				      "mmc",
>> +				      "output",
>> +				      "sample";
>> +			resets = <&ahb_rst 9>;
>> +			reset-names = "ahb";
>> +			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		mmc2: mmc@01c11000 {
>> +			compatible = "allwinner,sun5i-a13-mmc";
>> +			reg = <0x01c11000 0x1000>;
>> +			clocks = <&bus_gates 10>,
>> +				 <&mmc2_clk 0>,
>> +				 <&mmc2_clk 1>,
>> +				 <&mmc2_clk 2>;
>> +			clock-names = "ahb",
>> +				      "mmc",
>> +				      "output",
>> +				      "sample";
>> +			resets = <&ahb_rst 10>;
>> +			reset-names = "ahb";
>> +			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		pio: pinctrl@01c20800 {
>> +			compatible = "allwinner,a64-pinctrl";
>> +			reg = <0x01c20800 0x400>;
>> +			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&bus_gates 69>;
>> +			gpio-controller;
>> +			#gpio-cells = <3>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +
>> +			uart0_pins_a: uart0@0 {
>> +				allwinner,pins = "PB8", "PB9";
>> +				allwinner,function = "uart0";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			uart0_pins_b: uart0@1 {
>> +				allwinner,pins = "PF2", "PF3";
>> +				allwinner,function = "uart0";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			uart1_pins: uart1@0 {
>> +				allwinner,pins = "PG6", "PG7", "PG8", "PG9";
>> +				allwinner,function = "uart1";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			uart2_pins: uart2@0 {
>> +				allwinner,pins = "PB0", "PB1", "PB2", "PB3";
>> +				allwinner,function = "uart2";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			uart3_pins_a: uart3@0 {
>> +				allwinner,pins = "PD0", "PD1";
>> +				allwinner,function = "uart3";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			uart3_pins_b: uart3@1 {
>> +				allwinner,pins = "PH4", "PH5", "PH6", "PH7";
>> +				allwinner,function = "uart3";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			uart4_pins: uart4@0 {
>> +				allwinner,pins = "PD2", "PD3", "PD4", "PD5";
>> +				allwinner,function = "uart4";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			mmc0_pins: mmc0@0 {
>> +				allwinner,pins = "PF0", "PF1", "PF2", "PF3",
>> +						 "PF4", "PF5";
>> +				allwinner,function = "mmc0";
>> +				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			mmc0_default_cd_pin: mmc0_cd_pin@0 {
>> +				allwinner,pins = "PF6";
>> +				allwinner,function = "gpio_in";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
>> +			};
>> +
>> +			mmc1_pins: mmc1@0 {
>> +				allwinner,pins = "PG0", "PG1", "PG2", "PG3",
>> +						 "PG4", "PG5";
>> +				allwinner,function = "mmc1";
>> +				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			mmc2_pins: mmc2@0 {
>> +				allwinner,pins = "PC1", "PC5", "PC6", "PC8",
>> +						 "PC9", "PC10";
>> +				allwinner,function = "mmc2";
>> +				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +		};
>> +
>> +		ahb_rst: reset@01c202c0 {
>> +			#reset-cells = <1>;
>> +			compatible = "allwinner,sun6i-a31-ahb1-reset";
>> +			reg = <0x01c202c0 0xc>;
>> +		};
>> +
>> +		apb1_rst: reset@01c202d0 {
>> +			#reset-cells = <1>;
>> +			compatible = "allwinner,sun6i-a31-clock-reset";
>> +			reg = <0x01c202d0 0x4>;
>> +		};
>> +
>> +		apb2_rst: reset@01c202d8 {
>> +			#reset-cells = <1>;
>> +			compatible = "allwinner,sun6i-a31-clock-reset";
>> +			reg = <0x01c202d8 0x4>;
>> +		};
>> +
>> +		uart0: serial@01c28000 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c28000 0x400>;
>> +			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&bus_gates 112>;
>> +			resets = <&apb2_rst 16>;
>> +			reset-names = "apb2";
> 
> Do we need reset-names here (and below)?

Probably not, in fact I was wondering about that already. Actually I
just copied them from some other DT ;-)

>> +			status = "disabled";
>> +		};
>> +
>> +		uart1: serial@01c28400 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c28400 0x400>;
>> +			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&bus_gates 113>;
>> +			resets = <&apb2_rst 17>;
>> +			reset-names = "apb2";
>> +			status = "disabled";
>> +		};
>> +
>> +		uart2: serial@01c28800 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c28800 0x400>;
>> +			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&bus_gates 114>;
>> +			resets = <&apb2_rst 18>;
>> +			reset-names = "apb2";
>> +			status = "disabled";
>> +		};
>> +
>> +		uart3: serial@01c28c00 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c28c00 0x400>;
>> +			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&bus_gates 115>;
>> +			resets = <&apb2_rst 19>;
>> +			reset-names = "apb2";
>> +			status = "disabled";
>> +		};
>> +
>> +		uart4: serial@01c29000 {
>> +			compatible = "snps,dw-apb-uart";
>> +			reg = <0x01c29000 0x400>;
>> +			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
>> +			reg-shift = <2>;
>> +			reg-io-width = <4>;
>> +			clocks = <&bus_gates 116>;
>> +			resets = <&apb2_rst 20>;
>> +			reset-names = "apb2";
>> +			status = "disabled";
>> +		};
>> +
>> +		rtc: rtc@01f00000 {
>> +			compatible = "allwinner,sun6i-a31-rtc";
>> +			reg = <0x01f00000 0x54>;
>> +			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
>> +		};
>> +	};
>> +
>> +	gic: interrupt-controller@{
>> +		compatible = "arm,gic-400";
>> +		interrupt-controller;
>> +		#interrupt-cells = <3>;
>> +		#address-cells = <0>;
>> +
>> +		reg = <0x01C81000 0x1000>,
>> +		      <0x01C82000 0x2000>,
>> +		      <0x01C84000 0x2000>,
>> +		      <0x01C86000 0x2000>;
> 
> Maybe lowercase hex here too.

Yes.


Thanks for actually going through this!

Cheers,
Andre.

>> +		interrupts = <GIC_PPI 9
>> +		      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> +	};
>> +};
>>
> 
> Regards,
> Jens
> 

Re: [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi

[Jens Kuske]

Hi,

On 02/02/16 17:46, Andre Przywara wrote:
> Hi Jens,
> 
> thanks for having such an elaborate look!
> 
> On 02/02/16 16:24, Jens Kuske wrote:
>> Hi,
>>
>> On 01/02/16 18:39, Andre Przywara wrote:
[..]
>>> +
>>> +		/* dummy clock until pll6 can be reused */
>>> +		pll8: pll8_clk {
>>> +			#clock-cells = <0>;
>>> +			compatible = "fixed-clock";
>>> +			clock-frequency = <1>;
>>> +			clock-output-names = "pll8";
>>> +		};
> 
> Since I have you (as the original author ;-) in the loop: What was again
> the reason for this dummy clock? Can't it be modelled with the existing
> clock drivers in Linux?

PLL6 driver had the output name "pll6" hardcoded, so we couldn't reuse
it for "pll8". Maxime has reworked the pll6 code in the meantime, now
pll8 can use compatible = "allwinner,sun6i-a31-pll6-clk" too:
http://www.spinics.net/lists/linux-clk/msg06242.html

>
>>> +
>>> +		cpu: cpu_clk@01c20050 {
>>> +			#clock-cells = <0>;
>>> +			compatible = "allwinner,sun4i-a10-cpu-clk";
>>> +			reg = <0x01c20050 0x4>;
>>> +			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
>>> +			clock-output-names = "cpu";
>>> +			critical-clocks = <0>;
>>> +		};
>>> +
>>> +		axi: axi_clk@01c20050 {
>>> +			#clock-cells = <0>;
>>> +			compatible = "allwinner,sun4i-a10-axi-clk";
>>> +			reg = <0x01c20050 0x4>;
>>> +			clocks = <&cpu>;
>>> +			clock-output-names = "axi";
>>> +		};
>>> +
>>> +		ahb1: ahb1_clk@01c20054 {
>>> +			#clock-cells = <0>;
>>> +			compatible = "allwinner,sun6i-a31-ahb1-clk";
>>> +			reg = <0x01c20054 0x4>;
>>> +			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
>>> +			clock-output-names = "ahb1";
>>> +		};
>>> +
>>> +		ahb2: ahb2_clk@01c2005c {
>>> +			#clock-cells = <0>;
>>> +			compatible = "allwinner,sun8i-h3-ahb2-clk";
>>> +			reg = <0x01c2005c 0x4>;
>>> +			clocks = <&ahb1>, <&pll6d2>;
>>> +			clock-output-names = "ahb2";
>>> +		};
>>> +
>>> +		apb1: apb1_clk@01c20054 {
>>> +			#clock-cells = <0>;
>>> +			compatible = "allwinner,sun4i-a10-apb0-clk";
>>> +			reg = <0x01c20054 0x4>;
>>> +			clocks = <&ahb1>;
>>> +			clock-output-names = "apb1";
>>> +		};
>>> +
>>> +		apb2: apb2_clk@01c20058 {
>>> +			#clock-cells = <0>;
>>> +			compatible = "allwinner,sun4i-a10-apb1-clk";
>>> +			reg = <0x01c20058 0x4>;
>>> +			clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
>>> +			clock-output-names = "apb2";
>>> +		};
>>> +
>>> +		bus_gates: clk@01c20060 {
>>> +			#clock-cells = <1>;
>>> +			compatible = "allwinner,a64-bus-gates-clk",
>>> +				     "allwinner,sunxi-multi-bus-gates-clk";
>>> +			reg = <0x01c20060 0x14>;
>>> +			ahb1_parent {
>>> +				clocks = <&ahb1>;
>>> +				clock-indices = <1>, <5>,
>>> +						<6>, <8>,
>>> +						<9>, <10>,
>>> +						<13>, <14>,
>>> +						<18>, <19>,
>>> +						<20>, <21>,
>>> +						<23>, <24>,
>>> +						<25>, <28>,
>>> +						<32>, <35>,
>>> +						<36>, <37>,
>>> +						<40>, <43>,
>>> +						<44>, <52>,
>>> +						<53>, <54>,
>>> +						<135>;
>>> +				clock-output-names = "bus_mipidsi", "bus_ce",
>>> +						"bus_dma", "bus_mmc0",
>>> +						"bus_mmc1", "bus_mmc2",
>>> +						"bus_nand", "bus_sdram",
>>> +						"bus_ts", "bus_hstimer",
>>> +						"bus_spi0", "bus_spi1",
>>> +						"bus_otg", "bus_otg_ehci0",
>>> +						"bus_ehci0", "bus_otg_ohci0",
>>> +						"bus_ve", "bus_lcd0",
>>> +						"bus_lcd1", "bus_deint",
>>> +						"bus_csi", "bus_hdmi",
>>> +						"bus_de", "bus_gpu",
>>> +						"bus_msgbox", "bus_spinlock",
>>> +						"bus_dbg";
>>> +			};
>>> +			ahb2_parent {
>>> +				clocks = <&ahb2>;
>>> +				clock-indices = <17>, <29>;
>>> +				clock-output-names = "bus_gmac", "bus_ohci0";
>>> +			};
>>> +			apb1_parent {
>>> +				clocks = <&apb1>;
>>> +				clock-indices = <64>, <65>,
>>> +						<69>, <72>,
>>> +						<76>, <77>,
>>> +						<78>;
>>> +				clock-output-names = "bus_codec", "bus_spdif",
>>> +						"bus_pio", "bus_ths",
>>> +						"bus_i2s0", "bus_i2s1",
>>> +						"bus_i2s2";
>>> +			};
>>> +			abp2_parent {
>>> +				clocks = <&apb2>;
>>> +				clock-indices = <96>, <97>,
>>> +						<98>, <101>,
>>> +						<112>, <113>,
>>> +						<114>, <115>,
>>> +						<116>;
>>> +				clock-output-names = "bus_i2c0", "bus_i2c1",
>>> +						"bus_i2c2", "bus_scr",
>>> +						"bus_uart0", "bus_uart1",
>>> +						"bus_uart2", "bus_uart3",
>>> +						"bus_uart4";
>>> +			};
>>> +		};
>>> +
>>> +		mmc0_clk: clk@01c20088 {
>>> +			#clock-cells = <1>;
>>> +			compatible = "allwinner,sun4i-a10-mmc-clk";
>>
>> The A64 MMC clocks don't seem to be fully compatible to A10. The output
>> and sample phase control has been moved to the MMC module itself.
>> The dividers are the same, but the additional special "outputs" are gone.
> 
> So from comparing the H3 and the A64 datasheet I see that this is one of
> the rare deviations of the A64 from the H3?

Yeah, looks like this is new in A64, probably because it supports even
higher card speeds now.

> 
>>> +			reg = <0x01c20088 0x4>;
>>> +			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>>
>> Parents are PLL6(2x) and PLL8(2x) according to manual.
> 
> Indeed, thanks for pointing this out! So do we need a proper pll8 clock?

The dummy would still work, but it is easy to add a real pll8 now with
Maximes work.

> 
>>
>>> +			clock-output-names = "mmc0",
>>> +					     "mmc0_output",
>>> +					     "mmc0_sample";
>>> +		};
>>> +
>>> +		mmc1_clk: clk@01c2008c {
>>> +			#clock-cells = <1>;
>>> +			compatible = "allwinner,sun4i-a10-mmc-clk";
>>> +			reg = <0x01c2008c 0x4>;
>>> +			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>>> +			clock-output-names = "mmc1",
>>> +					     "mmc1_output",
>>> +					     "mmc1_sample";
>>> +		};
>>> +
>>> +		mmc2_clk: clk@01c20090 {
>>> +			#clock-cells = <1>;
>>> +			compatible = "allwinner,sun4i-a10-mmc-clk";
>>> +			reg = <0x01c20090 0x4>;
>>> +			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>>> +			clock-output-names = "mmc2",
>>> +					     "mmc2_output",
>>> +					     "mmc2_sample";
>>> +		};
>>> +	};
>>> +
>>> +	regulators {
>>> +		reg_vcc3v3: vcc3v3 {
>>> +			compatible = "regulator-fixed";
>>> +			regulator-name = "vcc3v3";
>>> +			regulator-min-microvolt = <3300000>;
>>> +			regulator-max-microvolt = <3300000>;
>>> +		};
>>> +	};
>>> +
>>> +	soc {
>>> +		compatible = "simple-bus";
>>> +		#address-cells = <1>;
>>> +		#size-cells = <1>;
>>> +		ranges;
>>> +
>>> +		mmc0: mmc@01c0f000 {
>>> +			compatible = "allwinner,sun5i-a13-mmc";
>>> +			reg = <0x01c0f000 0x1000>;
>>> +			clocks = <&bus_gates 8>,
>>> +				 <&mmc0_clk 0>,
>>
>> Consequently, the MMC driver now has to control the output/sample phase
>> with registers 0x140-0x148 instead of
>>> +				 <&mmc0_clk 1>,
>>> +				 <&mmc0_clk 2>;
> 
> OK, good point. I was just briefly browsing over the register
> descriptions and missed that.
> So it looks like I need to change the driver. Interestingly it seems to
> work anyways ...

I don't know, maybe it has sane defaults or is only relevant at higher
clock speeds. Or Allwinners u-boot already set it.

> 
>> And there seems to be some new clock divider somewhere which I haven't
>> found in the manual yet. The clock measured at the CLK pin is always
>> half the expected rate (even with 24MHz as MMC clock parent, so no
>> PLL6*2 problem).
> 
> Mmh, I heard about that mysterious clock doubling / halving already. Was
> that actually causing any issues?

Since it uses PLL6 * 2 now and seems to divide that by 2 somewhere
nothing has changed in the end. One could argue that pll6 * 2 is wrong,
but by testing with osc24MHz parent (in u-boot) it can be seen that the
clockrate is only half of what is expected.

Disclaimer: I don't know much about mmc, so maybe I've missed something
obvious. I only did some frequency measurements on H3 vs A64 hardware
when Siarhei asked about that in irc and now I wonder about the results.

Jens

Re: [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi

[Chen-Yu Tsai]

On Wed, Feb 3, 2016 at 12:46 AM, Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org> wrote:
> Hi Jens,
>
> thanks for having such an elaborate look!
>
> On 02/02/16 16:24, Jens Kuske wrote:
>> Hi,
>>
>> On 01/02/16 18:39, Andre Przywara wrote:
>>> The Allwinner A64 SoC is low-cost SoC with 4 ARM Cortex-A53 cores
>>> and the typical tablet / TV box peripherals.
>>> The Soc is based on the (32-bit) Allwinner H3 chip, sharing most of
>>> the peripherals and the memory map.
>>> Although the cores are proper 64-bit ones, the whole SoC is actually
>>> limited to 4GB (including all the supported DRAM), so we use 32-bit
>>> address and size cells. This has the nice feature of us being able to
>>> reuse the DT for 32-bit kernels as well.
>>> This .dtsi lists the hardware that we support so far.
>>>
>>> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
>>> ---
>>>  Documentation/devicetree/bindings/arm/sunxi.txt   |   1 +
>>>  Documentation/devicetree/bindings/clock/sunxi.txt |   1 +
>>>  arch/arm64/boot/dts/allwinner/a64.dtsi            | 583 ++++++++++++++++++++++
>>>  3 files changed, 585 insertions(+)
>>>  create mode 100644 arch/arm64/boot/dts/allwinner/a64.dtsi
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
>>> index 980e065..4a83853 100644
>>> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
>>> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
>>> @@ -14,6 +14,7 @@ using one of the following compatible strings:
>>>    allwinner,sun8i-a83t
>>>    allwinner,sun8i-h3
>>>    allwinner,sun9i-a80
>>> +  allwinner,a64
>>>
>>>  For Allwinner SoCs without any specific needs the generic fallback value of:
>>>    allwinner,sunxi
>>> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
>>> index e59f57b..44b0c6c 100644
>>> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>>> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>>> @@ -77,6 +77,7 @@ Required properties:
>>>      "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
>>>      "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
>>>      "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
>>> +    "allwinner,a64-bus-gates-clk" - for the A64 multi-parent bus gates clock
>>>
>>>  Required properties for all clocks:
>>>  - reg : shall be the control register address for the clock.
>>> diff --git a/arch/arm64/boot/dts/allwinner/a64.dtsi b/arch/arm64/boot/dts/allwinner/a64.dtsi
>>> new file mode 100644
>>> index 0000000..8dce10f
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/allwinner/a64.dtsi
>>> @@ -0,0 +1,583 @@
>>> +/*
>>> + * Copyright (C) 2016 ARM Ltd.
>>> + * based on the Allwinner H3 dtsi:
>>> + *    Copyright (C) 2015 Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>>> + *
>>> + * This file is dual-licensed: you can use it either under the terms
>>> + * of the GPL or the X11 license, at your option. Note that this dual
>>> + * licensing only applies to this file, and not this project as a
>>> + * whole.
>>> + *
>>> + *  a) This file is free software; you can redistribute it and/or
>>> + *     modify it under the terms of the GNU General Public License as
>>> + *     published by the Free Software Foundation; either version 2 of the
>>> + *     License, or (at your option) any later version.
>>> + *
>>> + *     This file is distributed in the hope that it will be useful,
>>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>> + *     GNU General Public License for more details.
>>> + *
>>> + * Or, alternatively,
>>> + *
>>> + *  b) Permission is hereby granted, free of charge, to any person
>>> + *     obtaining a copy of this software and associated documentation
>>> + *     files (the "Software"), to deal in the Software without
>>> + *     restriction, including without limitation the rights to use,
>>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
>>> + *     sell copies of the Software, and to permit persons to whom the
>>> + *     Software is furnished to do so, subject to the following
>>> + *     conditions:
>>> + *
>>> + *     The above copyright notice and this permission notice shall be
>>> + *     included in all copies or substantial portions of the Software.
>>> + *
>>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>> + *     OTHER DEALINGS IN THE SOFTWARE.
>>> + */
>>> +
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +#include <dt-bindings/pinctrl/sun4i-a10.h>
>>> +
>>> +/ {
>>> +    compatible = "allwinner,a64", "allwinner,sunxi";
>>> +    interrupt-parent = <&gic>;
>>> +    #address-cells = <1>;
>>> +    #size-cells = <1>;
>>> +
>>> +    aliases {
>>> +            serial0 = &uart0;
>>> +            serial1 = &uart1;
>>> +            serial2 = &uart2;
>>> +            serial3 = &uart3;
>>> +            serial4 = &uart4;
>>> +    };
>>> +
>>> +    cpus {
>>> +            #address-cells = <1>;
>>> +            #size-cells = <0>;
>>> +
>>> +            cpu@0 {
>>> +                    compatible = "arm,cortex-a53", "arm,armv8";
>>> +                    device_type = "cpu";
>>> +                    reg = <0>;
>>> +                    enable-method = "psci";
>>> +            };
>>> +
>>> +            cpu@1 {
>>> +                    compatible = "arm,cortex-a53", "arm,armv8";
>>> +                    device_type = "cpu";
>>> +                    reg = <1>;
>>> +                    enable-method = "psci";
>>> +            };
>>> +
>>> +            cpu@2 {
>>> +                    compatible = "arm,cortex-a53", "arm,armv8";
>>> +                    device_type = "cpu";
>>> +                    reg = <2>;
>>> +                    enable-method = "psci";
>>> +            };
>>> +
>>> +            cpu@3 {
>>> +                    compatible = "arm,cortex-a53", "arm,armv8";
>>> +                    device_type = "cpu";
>>> +                    reg = <3>;
>>> +                    enable-method = "psci";
>>> +            };
>>> +    };
>>> +
>>> +    psci {
>>> +            compatible = "arm,psci-0.2", "arm,psci";
>>> +            method = "smc";
>>> +            cpu_suspend = <0xc4000001>;
>>> +            cpu_off = <0x84000002>;
>>> +            cpu_on = <0xc4000003>;
>>> +    };
>>> +
>>> +    memory {
>>> +            device_type = "memory";
>>> +            reg = <0x40000000 0>;
>>> +    };
>>> +
>>> +    timer {
>>> +            compatible = "arm,armv8-timer";
>>> +            interrupts = <GIC_PPI 13
>>> +                    (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>>> +                         <GIC_PPI 14
>>> +                    (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>>> +                         <GIC_PPI 11
>>> +                    (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>>> +                         <GIC_PPI 10
>>> +                    (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>>> +    };
>>> +
>>> +    clocks {
>>> +            #address-cells = <1>;
>>> +            #size-cells = <1>;
>>> +            ranges;
>>> +
>>> +            osc24M: osc24M_clk {
>>> +                    #clock-cells = <0>;
>>> +                    compatible = "fixed-clock";
>>> +                    clock-frequency = <24000000>;
>>> +                    clock-output-names = "osc24M";
>>> +            };
>>> +
>>> +            osc32k: osc32k_clk {
>>> +                    #clock-cells = <0>;
>>> +                    compatible = "fixed-clock";
>>> +                    clock-frequency = <32768>;
>>> +                    clock-output-names = "osc32k";
>>> +            };
>>> +
>>> +            pll1: clk@01c20000 {
>>> +                    #clock-cells = <0>;
>>> +                    compatible = "allwinner,sun8i-a23-pll1-clk";
>>> +                    reg = <0x01c20000 0x4>;
>>> +                    clocks = <&osc24M>;
>>> +                    clock-output-names = "pll1";
>>> +            };
>>> +
>>> +            pll6: clk@01c20028 {
>>> +                    #clock-cells = <1>;
>>> +                    compatible = "allwinner,sun6i-a31-pll6-clk";
>>> +                    reg = <0x01c20028 0x4>;
>>> +                    clocks = <&osc24M>;
>>> +                    clock-output-names = "pll6", "pll6x2";
>>> +            };
>>> +
>>> +            pll6d2: pll6d2_clk {
>>> +                    #clock-cells = <0>;
>>> +                    compatible = "fixed-factor-clock";
>>> +                    clock-div = <2>;
>>> +                    clock-mult = <1>;
>>> +                    clocks = <&pll6 0>;
>>> +                    clock-output-names = "pll6d2";
>>> +            };
>>> +
>>> +            /* dummy clock until pll6 can be reused */
>>> +            pll8: pll8_clk {
>>> +                    #clock-cells = <0>;
>>> +                    compatible = "fixed-clock";
>>> +                    clock-frequency = <1>;
>>> +                    clock-output-names = "pll8";
>>> +            };
>
> Since I have you (as the original author ;-) in the loop: What was again
> the reason for this dummy clock? Can't it be modelled with the existing
> clock drivers in Linux?

The driver for "allwinner,sun6i-a31-pll6-clk" has it's name hard coded,
which means it's not reusable for other clocks. The placeholder is there
to provide a proper representation of the clock tree. It works because
nothing is clocked from pll8 by default.

>>> +
>>> +            cpu: cpu_clk@01c20050 {
>>> +                    #clock-cells = <0>;
>>> +                    compatible = "allwinner,sun4i-a10-cpu-clk";
>>> +                    reg = <0x01c20050 0x4>;
>>> +                    clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
>>> +                    clock-output-names = "cpu";
>>> +                    critical-clocks = <0>;
>>> +            };
>>> +
>>> +            axi: axi_clk@01c20050 {
>>> +                    #clock-cells = <0>;
>>> +                    compatible = "allwinner,sun4i-a10-axi-clk";
>>> +                    reg = <0x01c20050 0x4>;
>>> +                    clocks = <&cpu>;
>>> +                    clock-output-names = "axi";
>>> +            };
>>> +
>>> +            ahb1: ahb1_clk@01c20054 {
>>> +                    #clock-cells = <0>;
>>> +                    compatible = "allwinner,sun6i-a31-ahb1-clk";
>>> +                    reg = <0x01c20054 0x4>;
>>> +                    clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
>>> +                    clock-output-names = "ahb1";
>>> +            };
>>> +
>>> +            ahb2: ahb2_clk@01c2005c {
>>> +                    #clock-cells = <0>;
>>> +                    compatible = "allwinner,sun8i-h3-ahb2-clk";
>>> +                    reg = <0x01c2005c 0x4>;
>>> +                    clocks = <&ahb1>, <&pll6d2>;
>>> +                    clock-output-names = "ahb2";
>>> +            };
>>> +
>>> +            apb1: apb1_clk@01c20054 {
>>> +                    #clock-cells = <0>;
>>> +                    compatible = "allwinner,sun4i-a10-apb0-clk";
>>> +                    reg = <0x01c20054 0x4>;
>>> +                    clocks = <&ahb1>;
>>> +                    clock-output-names = "apb1";
>>> +            };
>>> +
>>> +            apb2: apb2_clk@01c20058 {
>>> +                    #clock-cells = <0>;
>>> +                    compatible = "allwinner,sun4i-a10-apb1-clk";
>>> +                    reg = <0x01c20058 0x4>;
>>> +                    clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
>>> +                    clock-output-names = "apb2";
>>> +            };
>>> +
>>> +            bus_gates: clk@01c20060 {
>>> +                    #clock-cells = <1>;
>>> +                    compatible = "allwinner,a64-bus-gates-clk",
>>> +                                 "allwinner,sunxi-multi-bus-gates-clk";
>>> +                    reg = <0x01c20060 0x14>;
>>> +                    ahb1_parent {
>>> +                            clocks = <&ahb1>;
>>> +                            clock-indices = <1>, <5>,
>>> +                                            <6>, <8>,
>>> +                                            <9>, <10>,
>>> +                                            <13>, <14>,
>>> +                                            <18>, <19>,
>>> +                                            <20>, <21>,
>>> +                                            <23>, <24>,
>>> +                                            <25>, <28>,
>>> +                                            <32>, <35>,
>>> +                                            <36>, <37>,
>>> +                                            <40>, <43>,
>>> +                                            <44>, <52>,
>>> +                                            <53>, <54>,
>>> +                                            <135>;
>>> +                            clock-output-names = "bus_mipidsi", "bus_ce",
>>> +                                            "bus_dma", "bus_mmc0",
>>> +                                            "bus_mmc1", "bus_mmc2",
>>> +                                            "bus_nand", "bus_sdram",
>>> +                                            "bus_ts", "bus_hstimer",
>>> +                                            "bus_spi0", "bus_spi1",
>>> +                                            "bus_otg", "bus_otg_ehci0",
>>> +                                            "bus_ehci0", "bus_otg_ohci0",
>>> +                                            "bus_ve", "bus_lcd0",
>>> +                                            "bus_lcd1", "bus_deint",
>>> +                                            "bus_csi", "bus_hdmi",
>>> +                                            "bus_de", "bus_gpu",
>>> +                                            "bus_msgbox", "bus_spinlock",
>>> +                                            "bus_dbg";
>>> +                    };
>>> +                    ahb2_parent {
>>> +                            clocks = <&ahb2>;
>>> +                            clock-indices = <17>, <29>;
>>> +                            clock-output-names = "bus_gmac", "bus_ohci0";
>>> +                    };
>>> +                    apb1_parent {
>>> +                            clocks = <&apb1>;
>>> +                            clock-indices = <64>, <65>,
>>> +                                            <69>, <72>,
>>> +                                            <76>, <77>,
>>> +                                            <78>;
>>> +                            clock-output-names = "bus_codec", "bus_spdif",
>>> +                                            "bus_pio", "bus_ths",
>>> +                                            "bus_i2s0", "bus_i2s1",
>>> +                                            "bus_i2s2";
>>> +                    };
>>> +                    abp2_parent {
>>> +                            clocks = <&apb2>;
>>> +                            clock-indices = <96>, <97>,
>>> +                                            <98>, <101>,
>>> +                                            <112>, <113>,
>>> +                                            <114>, <115>,
>>> +                                            <116>;
>>> +                            clock-output-names = "bus_i2c0", "bus_i2c1",
>>> +                                            "bus_i2c2", "bus_scr",
>>> +                                            "bus_uart0", "bus_uart1",
>>> +                                            "bus_uart2", "bus_uart3",
>>> +                                            "bus_uart4";
>>> +                    };
>>> +            };
>>> +
>>> +            mmc0_clk: clk@01c20088 {
>>> +                    #clock-cells = <1>;
>>> +                    compatible = "allwinner,sun4i-a10-mmc-clk";
>>
>> The A64 MMC clocks don't seem to be fully compatible to A10. The output
>> and sample phase control has been moved to the MMC module itself.
>> The dividers are the same, but the additional special "outputs" are gone.
>
> So from comparing the H3 and the A64 datasheet I see that this is one of
> the rare deviations of the A64 from the H3?

Without the extra phase delay clocks, this is now just a mod0 clock.

>>> +                    reg = <0x01c20088 0x4>;
>>> +                    clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>>
>> Parents are PLL6(2x) and PLL8(2x) according to manual.
>
> Indeed, thanks for pointing this out! So do we need a proper pll8 clock?

You could add a pll8x2 fixed-factor-clk for now, until Maxime's clk series
is worked out.

>
>>
>>> +                    clock-output-names = "mmc0",
>>> +                                         "mmc0_output",
>>> +                                         "mmc0_sample";
>>> +            };
>>> +
>>> +            mmc1_clk: clk@01c2008c {
>>> +                    #clock-cells = <1>;
>>> +                    compatible = "allwinner,sun4i-a10-mmc-clk";
>>> +                    reg = <0x01c2008c 0x4>;
>>> +                    clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>>> +                    clock-output-names = "mmc1",
>>> +                                         "mmc1_output",
>>> +                                         "mmc1_sample";
>>> +            };
>>> +
>>> +            mmc2_clk: clk@01c20090 {
>>> +                    #clock-cells = <1>;
>>> +                    compatible = "allwinner,sun4i-a10-mmc-clk";
>>> +                    reg = <0x01c20090 0x4>;
>>> +                    clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>>> +                    clock-output-names = "mmc2",
>>> +                                         "mmc2_output",
>>> +                                         "mmc2_sample";
>>> +            };
>>> +    };
>>> +
>>> +    regulators {
>>> +            reg_vcc3v3: vcc3v3 {
>>> +                    compatible = "regulator-fixed";
>>> +                    regulator-name = "vcc3v3";
>>> +                    regulator-min-microvolt = <3300000>;
>>> +                    regulator-max-microvolt = <3300000>;
>>> +            };

Why is this in the .dtsi?

>>> +    };
>>> +
>>> +    soc {
>>> +            compatible = "simple-bus";
>>> +            #address-cells = <1>;
>>> +            #size-cells = <1>;
>>> +            ranges;
>>> +
>>> +            mmc0: mmc@01c0f000 {
>>> +                    compatible = "allwinner,sun5i-a13-mmc";
>>> +                    reg = <0x01c0f000 0x1000>;
>>> +                    clocks = <&bus_gates 8>,
>>> +                             <&mmc0_clk 0>,
>>
>> Consequently, the MMC driver now has to control the output/sample phase
>> with registers 0x140-0x148 instead of
>>> +                             <&mmc0_clk 1>,
>>> +                             <&mmc0_clk 2>;
>
> OK, good point. I was just briefly browsing over the register
> descriptions and missed that.
> So it looks like I need to change the driver. Interestingly it seems to
> work anyways ...

The default delay values probably are good enough. Or they included routing
tolerances in the design notes. :)

You should still check Allwinner's kernel for new delay values though.

>> And there seems to be some new clock divider somewhere which I haven't
>> found in the manual yet. The clock measured at the CLK pin is always
>> half the expected rate (even with 24MHz as MMC clock parent, so no
>> PLL6*2 problem).
>
> Mmh, I heard about that mysterious clock doubling / halving already. Was
> that actually causing any issues?

On the A83T there was this "new timing mode" feature in the mmc clocks and
controller, which halved the card clock. I don't see any mention of it on
A64 though.

>>
>>> +                    clock-names = "ahb",
>>> +                                  "mmc",
>>> +                                  "output",
>>> +                                  "sample";
>>> +                    resets = <&ahb_rst 8>;
>>> +                    reset-names = "ahb";
>>> +                    interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
>>> +                    status = "disabled";
>>> +                    #address-cells = <1>;
>>> +                    #size-cells = <0>;
>>> +            };
>>> +
>>> +            mmc1: mmc@01c10000 {
>>> +                    compatible = "allwinner,sun5i-a13-mmc";
>>> +                    reg = <0x01c10000 0x1000>;
>>> +                    clocks = <&bus_gates 9>,
>>> +                             <&mmc1_clk 0>,
>>> +                             <&mmc1_clk 1>,
>>> +                             <&mmc1_clk 2>;
>>> +                    clock-names = "ahb",
>>> +                                  "mmc",
>>> +                                  "output",
>>> +                                  "sample";
>>> +                    resets = <&ahb_rst 9>;
>>> +                    reset-names = "ahb";
>>> +                    interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
>>> +                    status = "disabled";
>>> +                    #address-cells = <1>;
>>> +                    #size-cells = <0>;
>>> +            };
>>> +
>>> +            mmc2: mmc@01c11000 {
>>> +                    compatible = "allwinner,sun5i-a13-mmc";
>>> +                    reg = <0x01c11000 0x1000>;
>>> +                    clocks = <&bus_gates 10>,
>>> +                             <&mmc2_clk 0>,
>>> +                             <&mmc2_clk 1>,
>>> +                             <&mmc2_clk 2>;
>>> +                    clock-names = "ahb",
>>> +                                  "mmc",
>>> +                                  "output",
>>> +                                  "sample";
>>> +                    resets = <&ahb_rst 10>;
>>> +                    reset-names = "ahb";
>>> +                    interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>>> +                    status = "disabled";
>>> +                    #address-cells = <1>;
>>> +                    #size-cells = <0>;
>>> +            };
>>> +
>>> +            pio: pinctrl@01c20800 {
>>> +                    compatible = "allwinner,a64-pinctrl";
>>> +                    reg = <0x01c20800 0x400>;
>>> +                    interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>>> +                                 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>>> +                                 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
>>> +                    clocks = <&bus_gates 69>;
>>> +                    gpio-controller;
>>> +                    #gpio-cells = <3>;
>>> +                    interrupt-controller;
>>> +                    #interrupt-cells = <2>;
>>> +
>>> +                    uart0_pins_a: uart0@0 {
>>> +                            allwinner,pins = "PB8", "PB9";
>>> +                            allwinner,function = "uart0";
>>> +                            allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> +                            allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> +                    };
>>> +
>>> +                    uart0_pins_b: uart0@1 {
>>> +                            allwinner,pins = "PF2", "PF3";
>>> +                            allwinner,function = "uart0";
>>> +                            allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> +                            allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> +                    };
>>> +
>>> +                    uart1_pins: uart1@0 {
>>> +                            allwinner,pins = "PG6", "PG7", "PG8", "PG9";
>>> +                            allwinner,function = "uart1";
>>> +                            allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> +                            allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> +                    };
>>> +
>>> +                    uart2_pins: uart2@0 {
>>> +                            allwinner,pins = "PB0", "PB1", "PB2", "PB3";
>>> +                            allwinner,function = "uart2";
>>> +                            allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> +                            allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> +                    };
>>> +
>>> +                    uart3_pins_a: uart3@0 {
>>> +                            allwinner,pins = "PD0", "PD1";
>>> +                            allwinner,function = "uart3";
>>> +                            allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> +                            allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> +                    };
>>> +
>>> +                    uart3_pins_b: uart3@1 {
>>> +                            allwinner,pins = "PH4", "PH5", "PH6", "PH7";
>>> +                            allwinner,function = "uart3";
>>> +                            allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> +                            allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> +                    };
>>> +
>>> +                    uart4_pins: uart4@0 {
>>> +                            allwinner,pins = "PD2", "PD3", "PD4", "PD5";
>>> +                            allwinner,function = "uart4";
>>> +                            allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> +                            allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> +                    };

We normally don't add these until someone uses them.
And one could choose to use 2 pins instead of 4. :|

>>> +
>>> +                    mmc0_pins: mmc0@0 {
>>> +                            allwinner,pins = "PF0", "PF1", "PF2", "PF3",
>>> +                                             "PF4", "PF5";
>>> +                            allwinner,function = "mmc0";
>>> +                            allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>>> +                            allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> +                    };
>>> +
>>> +                    mmc0_default_cd_pin: mmc0_cd_pin@0 {
>>> +                            allwinner,pins = "PF6";
>>> +                            allwinner,function = "gpio_in";
>>> +                            allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> +                            allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
>>> +                    };
>>> +
>>> +                    mmc1_pins: mmc1@0 {
>>> +                            allwinner,pins = "PG0", "PG1", "PG2", "PG3",
>>> +                                             "PG4", "PG5";
>>> +                            allwinner,function = "mmc1";
>>> +                            allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>>> +                            allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> +                    };
>>> +
>>> +                    mmc2_pins: mmc2@0 {
>>> +                            allwinner,pins = "PC1", "PC5", "PC6", "PC8",
>>> +                                             "PC9", "PC10";
>>> +                            allwinner,function = "mmc2";
>>> +                            allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>>> +                            allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> +                    };
>>> +            };
>>> +
>>> +            ahb_rst: reset@01c202c0 {
>>> +                    #reset-cells = <1>;
>>> +                    compatible = "allwinner,sun6i-a31-ahb1-reset";
>>> +                    reg = <0x01c202c0 0xc>;
>>> +            };
>>> +
>>> +            apb1_rst: reset@01c202d0 {
>>> +                    #reset-cells = <1>;
>>> +                    compatible = "allwinner,sun6i-a31-clock-reset";
>>> +                    reg = <0x01c202d0 0x4>;
>>> +            };
>>> +
>>> +            apb2_rst: reset@01c202d8 {
>>> +                    #reset-cells = <1>;
>>> +                    compatible = "allwinner,sun6i-a31-clock-reset";
>>> +                    reg = <0x01c202d8 0x4>;
>>> +            };
>>> +
>>> +            uart0: serial@01c28000 {
>>> +                    compatible = "snps,dw-apb-uart";
>>> +                    reg = <0x01c28000 0x400>;
>>> +                    interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>>> +                    reg-shift = <2>;
>>> +                    reg-io-width = <4>;
>>> +                    clocks = <&bus_gates 112>;
>>> +                    resets = <&apb2_rst 16>;
>>> +                    reset-names = "apb2";
>>
>> Do we need reset-names here (and below)?
>
> Probably not, in fact I was wondering about that already. Actually I
> just copied them from some other DT ;-)

Nope. Not needed.


Regards
ChenYu

>>> +                    status = "disabled";
>>> +            };
>>> +
>>> +            uart1: serial@01c28400 {
>>> +                    compatible = "snps,dw-apb-uart";
>>> +                    reg = <0x01c28400 0x400>;
>>> +                    interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
>>> +                    reg-shift = <2>;
>>> +                    reg-io-width = <4>;
>>> +                    clocks = <&bus_gates 113>;
>>> +                    resets = <&apb2_rst 17>;
>>> +                    reset-names = "apb2";
>>> +                    status = "disabled";
>>> +            };
>>> +
>>> +            uart2: serial@01c28800 {
>>> +                    compatible = "snps,dw-apb-uart";
>>> +                    reg = <0x01c28800 0x400>;
>>> +                    interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
>>> +                    reg-shift = <2>;
>>> +                    reg-io-width = <4>;
>>> +                    clocks = <&bus_gates 114>;
>>> +                    resets = <&apb2_rst 18>;
>>> +                    reset-names = "apb2";
>>> +                    status = "disabled";
>>> +            };
>>> +
>>> +            uart3: serial@01c28c00 {
>>> +                    compatible = "snps,dw-apb-uart";
>>> +                    reg = <0x01c28c00 0x400>;
>>> +                    interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
>>> +                    reg-shift = <2>;
>>> +                    reg-io-width = <4>;
>>> +                    clocks = <&bus_gates 115>;
>>> +                    resets = <&apb2_rst 19>;
>>> +                    reset-names = "apb2";
>>> +                    status = "disabled";
>>> +            };
>>> +
>>> +            uart4: serial@01c29000 {
>>> +                    compatible = "snps,dw-apb-uart";
>>> +                    reg = <0x01c29000 0x400>;
>>> +                    interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
>>> +                    reg-shift = <2>;
>>> +                    reg-io-width = <4>;
>>> +                    clocks = <&bus_gates 116>;
>>> +                    resets = <&apb2_rst 20>;
>>> +                    reset-names = "apb2";
>>> +                    status = "disabled";
>>> +            };
>>> +
>>> +            rtc: rtc@01f00000 {
>>> +                    compatible = "allwinner,sun6i-a31-rtc";
>>> +                    reg = <0x01f00000 0x54>;
>>> +                    interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
>>> +                                 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
>>> +            };
>>> +    };
>>> +
>>> +    gic: interrupt-controller@{
>>> +            compatible = "arm,gic-400";
>>> +            interrupt-controller;
>>> +            #interrupt-cells = <3>;
>>> +            #address-cells = <0>;
>>> +
>>> +            reg = <0x01C81000 0x1000>,
>>> +                  <0x01C82000 0x2000>,
>>> +                  <0x01C84000 0x2000>,
>>> +                  <0x01C86000 0x2000>;
>>
>> Maybe lowercase hex here too.
>
> Yes.
>
>
> Thanks for actually going through this!
>
> Cheers,
> Andre.
>
>>> +            interrupts = <GIC_PPI 9
>>> +                  (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>>> +    };
>>> +};
>>>
>>
>> Regards,
>> Jens
>>
>
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Re: [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 16955 bytes --]

Hi Andre,

On Mon, Feb 01, 2016 at 05:39:29PM +0000, Andre Przywara wrote:
> The Allwinner A64 SoC is low-cost SoC with 4 ARM Cortex-A53 cores
> and the typical tablet / TV box peripherals.
> The Soc is based on the (32-bit) Allwinner H3 chip, sharing most of
> the peripherals and the memory map.
> Although the cores are proper 64-bit ones, the whole SoC is actually
> limited to 4GB (including all the supported DRAM), so we use 32-bit
> address and size cells. This has the nice feature of us being able to
> reuse the DT for 32-bit kernels as well.
> This .dtsi lists the hardware that we support so far.
> 
> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/arm/sunxi.txt   |   1 +
>  Documentation/devicetree/bindings/clock/sunxi.txt |   1 +
>  arch/arm64/boot/dts/allwinner/a64.dtsi            | 583 ++++++++++++++++++++++
>  3 files changed, 585 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/allwinner/a64.dtsi
> 
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
> index 980e065..4a83853 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> @@ -14,6 +14,7 @@ using one of the following compatible strings:
>    allwinner,sun8i-a83t
>    allwinner,sun8i-h3
>    allwinner,sun9i-a80
> +  allwinner,a64
>  
>  For Allwinner SoCs without any specific needs the generic fallback value of:
>    allwinner,sunxi
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index e59f57b..44b0c6c 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -77,6 +77,7 @@ Required properties:
>  	"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
>  	"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
>  	"allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
> +	"allwinner,a64-bus-gates-clk" - for the A64 multi-parent bus gates clock
>  
>  Required properties for all clocks:
>  - reg : shall be the control register address for the clock.
> diff --git a/arch/arm64/boot/dts/allwinner/a64.dtsi b/arch/arm64/boot/dts/allwinner/a64.dtsi
> new file mode 100644
> index 0000000..8dce10f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/a64.dtsi
> @@ -0,0 +1,583 @@
> +/*
> + * Copyright (C) 2016 ARM Ltd.
> + * based on the Allwinner H3 dtsi:
> + *    Copyright (C) 2015 Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
> +
> +/ {
> +	compatible = "allwinner,a64", "allwinner,sunxi";
> +	interrupt-parent = <&gic>;
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +		serial4 = &uart4;
> +	};

The aliases are usually per-board, as it will vary depending on what
the board enables.

> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <0>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu@1 {
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <1>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu@2 {
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <2>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu@3 {
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <3>;
> +			enable-method = "psci";
> +		};
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-0.2", "arm,psci";
> +		method = "smc";
> +		cpu_suspend = <0xc4000001>;
> +		cpu_off = <0x84000002>;
> +		cpu_on = <0xc4000003>;
> +	};

I thought that the function IDs were not needed anymore with PSCI 0.2?


> +	memory {
> +		device_type = "memory";
> +		reg = <0x40000000 0>;
> +	};

I'm guessing u-boot fixes that, can we just remove it entirely?

> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13
> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> +			     <GIC_PPI 14
> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> +			     <GIC_PPI 11
> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> +			     <GIC_PPI 10
> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +	};
> +
> +	clocks {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		osc24M: osc24M_clk {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <24000000>;
> +			clock-output-names = "osc24M";
> +		};
> +
> +		osc32k: osc32k_clk {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <32768>;
> +			clock-output-names = "osc32k";
> +		};
> +
> +		pll1: clk@01c20000 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun8i-a23-pll1-clk";
> +			reg = <0x01c20000 0x4>;
> +			clocks = <&osc24M>;
> +			clock-output-names = "pll1";
> +		};
> +
> +		pll6: clk@01c20028 {
> +			#clock-cells = <1>;
> +			compatible = "allwinner,sun6i-a31-pll6-clk";
> +			reg = <0x01c20028 0x4>;
> +			clocks = <&osc24M>;
> +			clock-output-names = "pll6", "pll6x2";

The output names have changed, and it doesn't take an argument
anymore.

> +		};
> +
> +		pll6d2: pll6d2_clk {
> +			#clock-cells = <0>;
> +			compatible = "fixed-factor-clock";
> +			clock-div = <2>;
> +			clock-mult = <1>;
> +			clocks = <&pll6 0>;
> +			clock-output-names = "pll6d2";
> +		};
> +
> +		/* dummy clock until pll6 can be reused */
> +		pll8: pll8_clk {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <1>;
> +			clock-output-names = "pll8";
> +		};
> +
> +		cpu: cpu_clk@01c20050 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-cpu-clk";
> +			reg = <0x01c20050 0x4>;
> +			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
> +			clock-output-names = "cpu";
> +			critical-clocks = <0>;
> +		};
> +
> +		axi: axi_clk@01c20050 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-axi-clk";
> +			reg = <0x01c20050 0x4>;
> +			clocks = <&cpu>;
> +			clock-output-names = "axi";
> +		};
> +
> +		ahb1: ahb1_clk@01c20054 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun6i-a31-ahb1-clk";
> +			reg = <0x01c20054 0x4>;
> +			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
> +			clock-output-names = "ahb1";
> +		};
> +
> +		ahb2: ahb2_clk@01c2005c {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun8i-h3-ahb2-clk";
> +			reg = <0x01c2005c 0x4>;
> +			clocks = <&ahb1>, <&pll6d2>;
> +			clock-output-names = "ahb2";
> +		};
> +
> +		apb1: apb1_clk@01c20054 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-apb0-clk";
> +			reg = <0x01c20054 0x4>;
> +			clocks = <&ahb1>;
> +			clock-output-names = "apb1";
> +		};
> +
> +		apb2: apb2_clk@01c20058 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-apb1-clk";
> +			reg = <0x01c20058 0x4>;
> +			clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
> +			clock-output-names = "apb2";
> +		};
> +
> +		bus_gates: clk@01c20060 {
> +			#clock-cells = <1>;
> +			compatible = "allwinner,a64-bus-gates-clk",
> +				     "allwinner,sunxi-multi-bus-gates-clk";
> +			reg = <0x01c20060 0x14>;
> +			ahb1_parent {
> +				clocks = <&ahb1>;
> +				clock-indices = <1>, <5>,
> +						<6>, <8>,
> +						<9>, <10>,
> +						<13>, <14>,
> +						<18>, <19>,
> +						<20>, <21>,
> +						<23>, <24>,
> +						<25>, <28>,
> +						<32>, <35>,
> +						<36>, <37>,
> +						<40>, <43>,
> +						<44>, <52>,
> +						<53>, <54>,
> +						<135>;
> +				clock-output-names = "bus_mipidsi", "bus_ce",
> +						"bus_dma", "bus_mmc0",
> +						"bus_mmc1", "bus_mmc2",
> +						"bus_nand", "bus_sdram",
> +						"bus_ts", "bus_hstimer",
> +						"bus_spi0", "bus_spi1",
> +						"bus_otg", "bus_otg_ehci0",
> +						"bus_ehci0", "bus_otg_ohci0",
> +						"bus_ve", "bus_lcd0",
> +						"bus_lcd1", "bus_deint",
> +						"bus_csi", "bus_hdmi",
> +						"bus_de", "bus_gpu",
> +						"bus_msgbox", "bus_spinlock",
> +						"bus_dbg";
> +			};
> +			ahb2_parent {
> +				clocks = <&ahb2>;
> +				clock-indices = <17>, <29>;
> +				clock-output-names = "bus_gmac", "bus_ohci0";
> +			};
> +			apb1_parent {
> +				clocks = <&apb1>;
> +				clock-indices = <64>, <65>,
> +						<69>, <72>,
> +						<76>, <77>,
> +						<78>;
> +				clock-output-names = "bus_codec", "bus_spdif",
> +						"bus_pio", "bus_ths",
> +						"bus_i2s0", "bus_i2s1",
> +						"bus_i2s2";
> +			};
> +			abp2_parent {
> +				clocks = <&apb2>;
> +				clock-indices = <96>, <97>,
> +						<98>, <101>,
> +						<112>, <113>,
> +						<114>, <115>,
> +						<116>;
> +				clock-output-names = "bus_i2c0", "bus_i2c1",
> +						"bus_i2c2", "bus_scr",
> +						"bus_uart0", "bus_uart1",
> +						"bus_uart2", "bus_uart3",
> +						"bus_uart4";
> +			};
> +		};

As I've already told you I'm not really fond of this one, for two main
topics.

The first one is about the DT bindings itself which is quite exotic,
especially the fact that you define clocks using clocks, clock-indices
and clock-output-names in nodes that are not the one referred to by
consumer, which goes against both the clock bindings documentation and
the usage.

The second one is pretty much the same one than for the discussion we
had about pinctrl. There is SoCs where we simply don't have that
information, or at least are not really sure about what to put where
(namely, the A83t). In such a case, we would knowingly put invalid
information in the DT, which is already quite bad in itself. The worst
part is, when we will identify issues and fix them (hopefully), there
will be no way to fix the current DT users. And it just became a pain
to maintain in the long run.

On the opposite side, having something like the H3 bus gates driver
address all these concerns and is easily extensible, which is why we
ended up merging it.

So please use it.

> +		mmc0_clk: clk@01c20088 {
> +			#clock-cells = <1>;
> +			compatible = "allwinner,sun4i-a10-mmc-clk";
> +			reg = <0x01c20088 0x4>;
> +			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
> +			clock-output-names = "mmc0",
> +					     "mmc0_output",
> +					     "mmc0_sample";
> +		};
> +
> +		mmc1_clk: clk@01c2008c {
> +			#clock-cells = <1>;
> +			compatible = "allwinner,sun4i-a10-mmc-clk";
> +			reg = <0x01c2008c 0x4>;
> +			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
> +			clock-output-names = "mmc1",
> +					     "mmc1_output",
> +					     "mmc1_sample";
> +		};
> +
> +		mmc2_clk: clk@01c20090 {
> +			#clock-cells = <1>;
> +			compatible = "allwinner,sun4i-a10-mmc-clk";
> +			reg = <0x01c20090 0x4>;
> +			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
> +			clock-output-names = "mmc2",
> +					     "mmc2_output",
> +					     "mmc2_sample";
> +		};
> +	};
> +
> +	regulators {
> +		reg_vcc3v3: vcc3v3 {
> +			compatible = "regulator-fixed";
> +			regulator-name = "vcc3v3";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;
> +		};
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		mmc0: mmc@01c0f000 {
> +			compatible = "allwinner,sun5i-a13-mmc";
> +			reg = <0x01c0f000 0x1000>;
> +			clocks = <&bus_gates 8>,
> +				 <&mmc0_clk 0>,
> +				 <&mmc0_clk 1>,
> +				 <&mmc0_clk 2>;
> +			clock-names = "ahb",
> +				      "mmc",
> +				      "output",
> +				      "sample";
> +			resets = <&ahb_rst 8>;
> +			reset-names = "ahb";
> +			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		mmc1: mmc@01c10000 {
> +			compatible = "allwinner,sun5i-a13-mmc";
> +			reg = <0x01c10000 0x1000>;
> +			clocks = <&bus_gates 9>,
> +				 <&mmc1_clk 0>,
> +				 <&mmc1_clk 1>,
> +				 <&mmc1_clk 2>;
> +			clock-names = "ahb",
> +				      "mmc",
> +				      "output",
> +				      "sample";
> +			resets = <&ahb_rst 9>;
> +			reset-names = "ahb";
> +			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		mmc2: mmc@01c11000 {
> +			compatible = "allwinner,sun5i-a13-mmc";
> +			reg = <0x01c11000 0x1000>;
> +			clocks = <&bus_gates 10>,
> +				 <&mmc2_clk 0>,
> +				 <&mmc2_clk 1>,
> +				 <&mmc2_clk 2>;
> +			clock-names = "ahb",
> +				      "mmc",
> +				      "output",
> +				      "sample";
> +			resets = <&ahb_rst 10>;
> +			reset-names = "ahb";
> +			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		pio: pinctrl@01c20800 {
> +			compatible = "allwinner,a64-pinctrl";
> +			reg = <0x01c20800 0x400>;
> +			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&bus_gates 69>;
> +			gpio-controller;
> +			#gpio-cells = <3>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +
> +			uart0_pins_a: uart0@0 {
> +				allwinner,pins = "PB8", "PB9";
> +				allwinner,function = "uart0";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			uart0_pins_b: uart0@1 {
> +				allwinner,pins = "PF2", "PF3";
> +				allwinner,function = "uart0";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			uart1_pins: uart1@0 {
> +				allwinner,pins = "PG6", "PG7", "PG8", "PG9";
> +				allwinner,function = "uart1";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			uart2_pins: uart2@0 {
> +				allwinner,pins = "PB0", "PB1", "PB2", "PB3";
> +				allwinner,function = "uart2";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			uart3_pins_a: uart3@0 {
> +				allwinner,pins = "PD0", "PD1";
> +				allwinner,function = "uart3";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			uart3_pins_b: uart3@1 {
> +				allwinner,pins = "PH4", "PH5", "PH6", "PH7";
> +				allwinner,function = "uart3";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};

You have several options for all these controllers, which is why we
have the _a or _b suffices.

Usually, the uart pins we had were only using RX and TX, I guess you
could add a separate node for the RTS / CTS pins if some board want to
use them.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi

[Andre Przywara]

Hi,

On 05/02/16 08:50, Maxime Ripard wrote:
> Hi Andre,
> 
> On Mon, Feb 01, 2016 at 05:39:29PM +0000, Andre Przywara wrote:
>> The Allwinner A64 SoC is low-cost SoC with 4 ARM Cortex-A53 cores
>> and the typical tablet / TV box peripherals.
>> The Soc is based on the (32-bit) Allwinner H3 chip, sharing most of
>> the peripherals and the memory map.
>> Although the cores are proper 64-bit ones, the whole SoC is actually
>> limited to 4GB (including all the supported DRAM), so we use 32-bit
>> address and size cells. This has the nice feature of us being able to
>> reuse the DT for 32-bit kernels as well.
>> This .dtsi lists the hardware that we support so far.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>> ---
>>  Documentation/devicetree/bindings/arm/sunxi.txt   |   1 +
>>  Documentation/devicetree/bindings/clock/sunxi.txt |   1 +
>>  arch/arm64/boot/dts/allwinner/a64.dtsi            | 583 ++++++++++++++++++++++
>>  3 files changed, 585 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/allwinner/a64.dtsi
>>
>> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
>> index 980e065..4a83853 100644
>> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
>> @@ -14,6 +14,7 @@ using one of the following compatible strings:
>>    allwinner,sun8i-a83t
>>    allwinner,sun8i-h3
>>    allwinner,sun9i-a80
>> +  allwinner,a64
>>  
>>  For Allwinner SoCs without any specific needs the generic fallback value of:
>>    allwinner,sunxi
>> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
>> index e59f57b..44b0c6c 100644
>> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>> @@ -77,6 +77,7 @@ Required properties:
>>  	"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
>>  	"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
>>  	"allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
>> +	"allwinner,a64-bus-gates-clk" - for the A64 multi-parent bus gates clock
>>  
>>  Required properties for all clocks:
>>  - reg : shall be the control register address for the clock.
>> diff --git a/arch/arm64/boot/dts/allwinner/a64.dtsi b/arch/arm64/boot/dts/allwinner/a64.dtsi
>> new file mode 100644
>> index 0000000..8dce10f
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/allwinner/a64.dtsi
>> @@ -0,0 +1,583 @@
>> +/*
>> + * Copyright (C) 2016 ARM Ltd.
>> + * based on the Allwinner H3 dtsi:
>> + *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This file is free software; you can redistribute it and/or
>> + *     modify it under the terms of the GNU General Public License as
>> + *     published by the Free Software Foundation; either version 2 of the
>> + *     License, or (at your option) any later version.
>> + *
>> + *     This file is distributed in the hope that it will be useful,
>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + *     GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + *     obtaining a copy of this software and associated documentation
>> + *     files (the "Software"), to deal in the Software without
>> + *     restriction, including without limitation the rights to use,
>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
>> + *     sell copies of the Software, and to permit persons to whom the
>> + *     Software is furnished to do so, subject to the following
>> + *     conditions:
>> + *
>> + *     The above copyright notice and this permission notice shall be
>> + *     included in all copies or substantial portions of the Software.
>> + *
>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + *     OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/pinctrl/sun4i-a10.h>
>> +
>> +/ {
>> +	compatible = "allwinner,a64", "allwinner,sunxi";
>> +	interrupt-parent = <&gic>;
>> +	#address-cells = <1>;
>> +	#size-cells = <1>;
>> +
>> +	aliases {
>> +		serial0 = &uart0;
>> +		serial1 = &uart1;
>> +		serial2 = &uart2;
>> +		serial3 = &uart3;
>> +		serial4 = &uart4;
>> +	};
> 
> The aliases are usually per-board, as it will vary depending on what
> the board enables.

Sure.

> 
>> +
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		cpu@0 {
>> +			compatible = "arm,cortex-a53", "arm,armv8";
>> +			device_type = "cpu";
>> +			reg = <0>;
>> +			enable-method = "psci";
>> +		};
>> +
>> +		cpu@1 {
>> +			compatible = "arm,cortex-a53", "arm,armv8";
>> +			device_type = "cpu";
>> +			reg = <1>;
>> +			enable-method = "psci";
>> +		};
>> +
>> +		cpu@2 {
>> +			compatible = "arm,cortex-a53", "arm,armv8";
>> +			device_type = "cpu";
>> +			reg = <2>;
>> +			enable-method = "psci";
>> +		};
>> +
>> +		cpu@3 {
>> +			compatible = "arm,cortex-a53", "arm,armv8";
>> +			device_type = "cpu";
>> +			reg = <3>;
>> +			enable-method = "psci";
>> +		};
>> +	};
>> +
>> +	psci {
>> +		compatible = "arm,psci-0.2", "arm,psci";
>> +		method = "smc";
>> +		cpu_suspend = <0xc4000001>;
>> +		cpu_off = <0x84000002>;
>> +		cpu_on = <0xc4000003>;
>> +	};
> 
> I thought that the function IDs were not needed anymore with PSCI 0.2?

The idea here was to provide compatibility with older OSes not
supporting PSCI 0.2, those would match on the "arm,psci" compatible
string and require the numbers (see bindings/arm/psci.txt).

Thinking again I realise that we require PSCI 0.2 for having reset and
shutdown, so I will drop this and just provide the 0.2 compatible string.

>> +	memory {
>> +		device_type = "memory";
>> +		reg = <0x40000000 0>;
>> +	};
> 
> I'm guessing u-boot fixes that, can we just remove it entirely?

Don't know, can we? I found it nice to have it in here to give people at
the least the idea of where DRAM starts and also making it clear that a
bootloader is expected to patch this (and having a node already makes
patching easier).

>> +	timer {
>> +		compatible = "arm,armv8-timer";
>> +		interrupts = <GIC_PPI 13
>> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>> +			     <GIC_PPI 14
>> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>> +			     <GIC_PPI 11
>> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>> +			     <GIC_PPI 10
>> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> +	};
>> +
>> +	clocks {
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges;
>> +
>> +		osc24M: osc24M_clk {
>> +			#clock-cells = <0>;
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <24000000>;
>> +			clock-output-names = "osc24M";
>> +		};
>> +
>> +		osc32k: osc32k_clk {
>> +			#clock-cells = <0>;
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <32768>;
>> +			clock-output-names = "osc32k";
>> +		};
>> +
>> +		pll1: clk@01c20000 {
>> +			#clock-cells = <0>;
>> +			compatible = "allwinner,sun8i-a23-pll1-clk";
>> +			reg = <0x01c20000 0x4>;
>> +			clocks = <&osc24M>;
>> +			clock-output-names = "pll1";
>> +		};
>> +
>> +		pll6: clk@01c20028 {
>> +			#clock-cells = <1>;
>> +			compatible = "allwinner,sun6i-a31-pll6-clk";
>> +			reg = <0x01c20028 0x4>;
>> +			clocks = <&osc24M>;
>> +			clock-output-names = "pll6", "pll6x2";
> 
> The output names have changed, and it doesn't take an argument
> anymore.

Would be happy to adapt to this, but we should sort this approach out
(see the other mail).

>> +		};
>> +
>> +		pll6d2: pll6d2_clk {
>> +			#clock-cells = <0>;
>> +			compatible = "fixed-factor-clock";
>> +			clock-div = <2>;
>> +			clock-mult = <1>;
>> +			clocks = <&pll6 0>;
>> +			clock-output-names = "pll6d2";
>> +		};
>> +
>> +		/* dummy clock until pll6 can be reused */
>> +		pll8: pll8_clk {
>> +			#clock-cells = <0>;
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <1>;
>> +			clock-output-names = "pll8";
>> +		};
>> +
>> +		cpu: cpu_clk@01c20050 {
>> +			#clock-cells = <0>;
>> +			compatible = "allwinner,sun4i-a10-cpu-clk";
>> +			reg = <0x01c20050 0x4>;
>> +			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
>> +			clock-output-names = "cpu";
>> +			critical-clocks = <0>;
>> +		};
>> +
>> +		axi: axi_clk@01c20050 {
>> +			#clock-cells = <0>;
>> +			compatible = "allwinner,sun4i-a10-axi-clk";
>> +			reg = <0x01c20050 0x4>;
>> +			clocks = <&cpu>;
>> +			clock-output-names = "axi";
>> +		};
>> +
>> +		ahb1: ahb1_clk@01c20054 {
>> +			#clock-cells = <0>;
>> +			compatible = "allwinner,sun6i-a31-ahb1-clk";
>> +			reg = <0x01c20054 0x4>;
>> +			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
>> +			clock-output-names = "ahb1";
>> +		};
>> +
>> +		ahb2: ahb2_clk@01c2005c {
>> +			#clock-cells = <0>;
>> +			compatible = "allwinner,sun8i-h3-ahb2-clk";
>> +			reg = <0x01c2005c 0x4>;
>> +			clocks = <&ahb1>, <&pll6d2>;
>> +			clock-output-names = "ahb2";
>> +		};
>> +
>> +		apb1: apb1_clk@01c20054 {
>> +			#clock-cells = <0>;
>> +			compatible = "allwinner,sun4i-a10-apb0-clk";
>> +			reg = <0x01c20054 0x4>;
>> +			clocks = <&ahb1>;
>> +			clock-output-names = "apb1";
>> +		};
>> +
>> +		apb2: apb2_clk@01c20058 {
>> +			#clock-cells = <0>;
>> +			compatible = "allwinner,sun4i-a10-apb1-clk";
>> +			reg = <0x01c20058 0x4>;
>> +			clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
>> +			clock-output-names = "apb2";
>> +		};
>> +
>> +		bus_gates: clk@01c20060 {
>> +			#clock-cells = <1>;
>> +			compatible = "allwinner,a64-bus-gates-clk",
>> +				     "allwinner,sunxi-multi-bus-gates-clk";
>> +			reg = <0x01c20060 0x14>;
>> +			ahb1_parent {
>> +				clocks = <&ahb1>;
>> +				clock-indices = <1>, <5>,
>> +						<6>, <8>,
>> +						<9>, <10>,
>> +						<13>, <14>,
>> +						<18>, <19>,
>> +						<20>, <21>,
>> +						<23>, <24>,
>> +						<25>, <28>,
>> +						<32>, <35>,
>> +						<36>, <37>,
>> +						<40>, <43>,
>> +						<44>, <52>,
>> +						<53>, <54>,
>> +						<135>;
>> +				clock-output-names = "bus_mipidsi", "bus_ce",
>> +						"bus_dma", "bus_mmc0",
>> +						"bus_mmc1", "bus_mmc2",
>> +						"bus_nand", "bus_sdram",
>> +						"bus_ts", "bus_hstimer",
>> +						"bus_spi0", "bus_spi1",
>> +						"bus_otg", "bus_otg_ehci0",
>> +						"bus_ehci0", "bus_otg_ohci0",
>> +						"bus_ve", "bus_lcd0",
>> +						"bus_lcd1", "bus_deint",
>> +						"bus_csi", "bus_hdmi",
>> +						"bus_de", "bus_gpu",
>> +						"bus_msgbox", "bus_spinlock",
>> +						"bus_dbg";
>> +			};
>> +			ahb2_parent {
>> +				clocks = <&ahb2>;
>> +				clock-indices = <17>, <29>;
>> +				clock-output-names = "bus_gmac", "bus_ohci0";
>> +			};
>> +			apb1_parent {
>> +				clocks = <&apb1>;
>> +				clock-indices = <64>, <65>,
>> +						<69>, <72>,
>> +						<76>, <77>,
>> +						<78>;
>> +				clock-output-names = "bus_codec", "bus_spdif",
>> +						"bus_pio", "bus_ths",
>> +						"bus_i2s0", "bus_i2s1",
>> +						"bus_i2s2";
>> +			};
>> +			abp2_parent {
>> +				clocks = <&apb2>;
>> +				clock-indices = <96>, <97>,
>> +						<98>, <101>,
>> +						<112>, <113>,
>> +						<114>, <115>,
>> +						<116>;
>> +				clock-output-names = "bus_i2c0", "bus_i2c1",
>> +						"bus_i2c2", "bus_scr",
>> +						"bus_uart0", "bus_uart1",
>> +						"bus_uart2", "bus_uart3",
>> +						"bus_uart4";
>> +			};
>> +		};
> 
> As I've already told you I'm not really fond of this one, for two main
> topics.
> 
> The first one is about the DT bindings itself which is quite exotic,
> especially the fact that you define clocks using clocks, clock-indices
> and clock-output-names in nodes that are not the one referred to by
> consumer, which goes against both the clock bindings documentation and
> the usage.

You are right in one point: it is not documented. I just see that I
forgot to update the bindings doc and describe this behaviour there.

But I don't see an issue with abstracting the clock provider's internal
details by referring to the parent node and use the DT's natural tree
structure to properly represent these clock gates. I cannot read
anything in clock-bindings.txt that would prevent this.

Happy to hear from DT maintainers about it.

> The second one is pretty much the same one than for the discussion we
> had about pinctrl. There is SoCs where we simply don't have that
> information, or at least are not really sure about what to put where
> (namely, the A83t). In such a case, we would knowingly put invalid
> information in the DT, which is already quite bad in itself.

And in your case we would put knowingly invalid information into the kernel?
So what is wrong with just _not_ putting this information until we know
it? With my patch you would just enumerate the gates we know the parents
of so far. Once we learn about the other gates, we add them. If we don't
know the parent, we probably can't use it anyway, I guess.
So we do as we do with other new features: updated DTs provide new
functionality.

And also: this is about A64, not A83t.

> The worst
> part is, when we will identify issues and fix them (hopefully), there
> will be no way to fix the current DT users.

But if we have a broken DT out there where a feature never worked or had
bugs, we _can_ fix it. Interested users will upgrade their DT and are
able to use the new feature or run without bugs now. This mimics the
approach when we add features: users update. However if users are happy
with the current feature set or are not affected by the bug, they can
use the older DT.

Also from my point of view it is much harder to provide an updated
kernel to people, since every distribution would need to pick up the
changes and provide updates to their users.

> And it just became a pain to maintain in the long run.

How so?

> On the opposite side, having something like the H3 bus gates driver
> address all these concerns and is easily extensible, which is why we
> ended up merging it.

Speaking of this driver: I really dislike that it hardcodes Soc specific
information into the kernel. I consider this bad style. The clock gates
are a rather generic functionality (one bit per gate), and we provide
the SoC specific part (mapping names and bit numbers) already in the DT.
So with the parent relation in the code we hide some information from
the DT which clearly belongs there, also ending up with having something
in the kernel and something in the DT.
Also this requires to add support for each and every SoC explicitly in
the kernel.

Also please keep in mind that the DT is not just for Linux: why should
other OS developers hard code the same information over and over again
when we could have it once for everybody in the DT?

I think we should stop with supporting each and every SoC explicitly in
the kernel and go for more generic drivers, that use DTs to describe
each SoC.
That way we can eventually reach the point where we have (at least)
basic functionality for a new SoC in existing(!) kernels - like from a
LTS style distribution kernel.
New SoCs would just come with their DTs as part of their firmware, as
it's the case with many arm64 boards out there at the moment. As long as
they don't have fundamentally new IP blocks (for the basic
functionality), that could just work out of the box.

> So please use it.

I really rather would avoid doing this.

I would appreciate if other people could comment on this.

> 
>> +		mmc0_clk: clk@01c20088 {
>> +			#clock-cells = <1>;
>> +			compatible = "allwinner,sun4i-a10-mmc-clk";
>> +			reg = <0x01c20088 0x4>;
>> +			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>> +			clock-output-names = "mmc0",
>> +					     "mmc0_output",
>> +					     "mmc0_sample";
>> +		};
>> +
>> +		mmc1_clk: clk@01c2008c {
>> +			#clock-cells = <1>;
>> +			compatible = "allwinner,sun4i-a10-mmc-clk";
>> +			reg = <0x01c2008c 0x4>;
>> +			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>> +			clock-output-names = "mmc1",
>> +					     "mmc1_output",
>> +					     "mmc1_sample";
>> +		};
>> +
>> +		mmc2_clk: clk@01c20090 {
>> +			#clock-cells = <1>;
>> +			compatible = "allwinner,sun4i-a10-mmc-clk";
>> +			reg = <0x01c20090 0x4>;
>> +			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
>> +			clock-output-names = "mmc2",
>> +					     "mmc2_output",
>> +					     "mmc2_sample";
>> +		};
>> +	};
>> +
>> +	regulators {
>> +		reg_vcc3v3: vcc3v3 {
>> +			compatible = "regulator-fixed";
>> +			regulator-name = "vcc3v3";
>> +			regulator-min-microvolt = <3300000>;
>> +			regulator-max-microvolt = <3300000>;
>> +		};
>> +	};
>> +
>> +	soc {
>> +		compatible = "simple-bus";
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges;
>> +
>> +		mmc0: mmc@01c0f000 {
>> +			compatible = "allwinner,sun5i-a13-mmc";
>> +			reg = <0x01c0f000 0x1000>;
>> +			clocks = <&bus_gates 8>,
>> +				 <&mmc0_clk 0>,
>> +				 <&mmc0_clk 1>,
>> +				 <&mmc0_clk 2>;
>> +			clock-names = "ahb",
>> +				      "mmc",
>> +				      "output",
>> +				      "sample";
>> +			resets = <&ahb_rst 8>;
>> +			reset-names = "ahb";
>> +			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		mmc1: mmc@01c10000 {
>> +			compatible = "allwinner,sun5i-a13-mmc";
>> +			reg = <0x01c10000 0x1000>;
>> +			clocks = <&bus_gates 9>,
>> +				 <&mmc1_clk 0>,
>> +				 <&mmc1_clk 1>,
>> +				 <&mmc1_clk 2>;
>> +			clock-names = "ahb",
>> +				      "mmc",
>> +				      "output",
>> +				      "sample";
>> +			resets = <&ahb_rst 9>;
>> +			reset-names = "ahb";
>> +			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		mmc2: mmc@01c11000 {
>> +			compatible = "allwinner,sun5i-a13-mmc";
>> +			reg = <0x01c11000 0x1000>;
>> +			clocks = <&bus_gates 10>,
>> +				 <&mmc2_clk 0>,
>> +				 <&mmc2_clk 1>,
>> +				 <&mmc2_clk 2>;
>> +			clock-names = "ahb",
>> +				      "mmc",
>> +				      "output",
>> +				      "sample";
>> +			resets = <&ahb_rst 10>;
>> +			reset-names = "ahb";
>> +			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>> +			status = "disabled";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +
>> +		pio: pinctrl@01c20800 {
>> +			compatible = "allwinner,a64-pinctrl";
>> +			reg = <0x01c20800 0x400>;
>> +			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&bus_gates 69>;
>> +			gpio-controller;
>> +			#gpio-cells = <3>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +
>> +			uart0_pins_a: uart0@0 {
>> +				allwinner,pins = "PB8", "PB9";
>> +				allwinner,function = "uart0";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			uart0_pins_b: uart0@1 {
>> +				allwinner,pins = "PF2", "PF3";
>> +				allwinner,function = "uart0";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			uart1_pins: uart1@0 {
>> +				allwinner,pins = "PG6", "PG7", "PG8", "PG9";
>> +				allwinner,function = "uart1";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			uart2_pins: uart2@0 {
>> +				allwinner,pins = "PB0", "PB1", "PB2", "PB3";
>> +				allwinner,function = "uart2";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			uart3_pins_a: uart3@0 {
>> +				allwinner,pins = "PD0", "PD1";
>> +				allwinner,function = "uart3";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
>> +
>> +			uart3_pins_b: uart3@1 {
>> +				allwinner,pins = "PH4", "PH5", "PH6", "PH7";
>> +				allwinner,function = "uart3";
>> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +			};
> 
> You have several options for all these controllers, which is why we
> have the _a or _b suffices.
> 
> Usually, the uart pins we had were only using RX and TX, I guess you
> could add a separate node for the RTS / CTS pins if some board want to
> use them.

Makes sense. Do you want the RTS/CTS pins in a separate child node or
another variant (like uart3_pins_b_hwhs) with all four pins in addition
to the two-pin version?

Cheers,
Andre

Re: [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 15531 bytes --]

Hi,

Sorry for the late reply,

On Mon, Feb 08, 2016 at 09:42:35AM +0000, Andre Przywara wrote:
> >> +	memory {
> >> +		device_type = "memory";
> >> +		reg = <0x40000000 0>;
> >> +	};
> > 
> > I'm guessing u-boot fixes that, can we just remove it entirely?
> 
> Don't know, can we? I found it nice to have it in here to give people at
> the least the idea of where DRAM starts and also making it clear that a
> bootloader is expected to patch this (and having a node already makes
> patching easier).

Well, U-Boot seems to deal with it just fine. The only SoCs where we
do it are SoCs where had to use the Allwinner bootloader.

I guess I don't really care, but if it's to indicate where the RAM is
mapped, we'd be better off by putting the max memory size there
instead of 0, and a comment saying that the bootloader is supposed to
patch this node.

> >> +	timer {
> >> +		compatible = "arm,armv8-timer";
> >> +		interrupts = <GIC_PPI 13
> >> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> >> +			     <GIC_PPI 14
> >> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> >> +			     <GIC_PPI 11
> >> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> >> +			     <GIC_PPI 10
> >> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> >> +	};
> >> +
> >> +	clocks {
> >> +		#address-cells = <1>;
> >> +		#size-cells = <1>;
> >> +		ranges;
> >> +
> >> +		osc24M: osc24M_clk {
> >> +			#clock-cells = <0>;
> >> +			compatible = "fixed-clock";
> >> +			clock-frequency = <24000000>;
> >> +			clock-output-names = "osc24M";
> >> +		};
> >> +
> >> +		osc32k: osc32k_clk {
> >> +			#clock-cells = <0>;
> >> +			compatible = "fixed-clock";
> >> +			clock-frequency = <32768>;
> >> +			clock-output-names = "osc32k";
> >> +		};
> >> +
> >> +		pll1: clk@01c20000 {
> >> +			#clock-cells = <0>;
> >> +			compatible = "allwinner,sun8i-a23-pll1-clk";
> >> +			reg = <0x01c20000 0x4>;
> >> +			clocks = <&osc24M>;
> >> +			clock-output-names = "pll1";
> >> +		};
> >> +
> >> +		pll6: clk@01c20028 {
> >> +			#clock-cells = <1>;
> >> +			compatible = "allwinner,sun6i-a31-pll6-clk";
> >> +			reg = <0x01c20028 0x4>;
> >> +			clocks = <&osc24M>;
> >> +			clock-output-names = "pll6", "pll6x2";
> > 
> > The output names have changed, and it doesn't take an argument
> > anymore.
> 
> Would be happy to adapt to this, but we should sort this approach out
> (see the other mail).

Yeah.

> 
> >> +		};
> >> +
> >> +		pll6d2: pll6d2_clk {
> >> +			#clock-cells = <0>;
> >> +			compatible = "fixed-factor-clock";
> >> +			clock-div = <2>;
> >> +			clock-mult = <1>;
> >> +			clocks = <&pll6 0>;
> >> +			clock-output-names = "pll6d2";
> >> +		};
> >> +
> >> +		/* dummy clock until pll6 can be reused */
> >> +		pll8: pll8_clk {
> >> +			#clock-cells = <0>;
> >> +			compatible = "fixed-clock";
> >> +			clock-frequency = <1>;
> >> +			clock-output-names = "pll8";
> >> +		};
> >> +
> >> +		cpu: cpu_clk@01c20050 {
> >> +			#clock-cells = <0>;
> >> +			compatible = "allwinner,sun4i-a10-cpu-clk";
> >> +			reg = <0x01c20050 0x4>;
> >> +			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
> >> +			clock-output-names = "cpu";
> >> +			critical-clocks = <0>;
> >> +		};
> >> +
> >> +		axi: axi_clk@01c20050 {
> >> +			#clock-cells = <0>;
> >> +			compatible = "allwinner,sun4i-a10-axi-clk";
> >> +			reg = <0x01c20050 0x4>;
> >> +			clocks = <&cpu>;
> >> +			clock-output-names = "axi";
> >> +		};
> >> +
> >> +		ahb1: ahb1_clk@01c20054 {
> >> +			#clock-cells = <0>;
> >> +			compatible = "allwinner,sun6i-a31-ahb1-clk";
> >> +			reg = <0x01c20054 0x4>;
> >> +			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
> >> +			clock-output-names = "ahb1";
> >> +		};
> >> +
> >> +		ahb2: ahb2_clk@01c2005c {
> >> +			#clock-cells = <0>;
> >> +			compatible = "allwinner,sun8i-h3-ahb2-clk";
> >> +			reg = <0x01c2005c 0x4>;
> >> +			clocks = <&ahb1>, <&pll6d2>;
> >> +			clock-output-names = "ahb2";
> >> +		};
> >> +
> >> +		apb1: apb1_clk@01c20054 {
> >> +			#clock-cells = <0>;
> >> +			compatible = "allwinner,sun4i-a10-apb0-clk";
> >> +			reg = <0x01c20054 0x4>;
> >> +			clocks = <&ahb1>;
> >> +			clock-output-names = "apb1";
> >> +		};
> >> +
> >> +		apb2: apb2_clk@01c20058 {
> >> +			#clock-cells = <0>;
> >> +			compatible = "allwinner,sun4i-a10-apb1-clk";
> >> +			reg = <0x01c20058 0x4>;
> >> +			clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
> >> +			clock-output-names = "apb2";
> >> +		};
> >> +
> >> +		bus_gates: clk@01c20060 {
> >> +			#clock-cells = <1>;
> >> +			compatible = "allwinner,a64-bus-gates-clk",
> >> +				     "allwinner,sunxi-multi-bus-gates-clk";
> >> +			reg = <0x01c20060 0x14>;
> >> +			ahb1_parent {
> >> +				clocks = <&ahb1>;
> >> +				clock-indices = <1>, <5>,
> >> +						<6>, <8>,
> >> +						<9>, <10>,
> >> +						<13>, <14>,
> >> +						<18>, <19>,
> >> +						<20>, <21>,
> >> +						<23>, <24>,
> >> +						<25>, <28>,
> >> +						<32>, <35>,
> >> +						<36>, <37>,
> >> +						<40>, <43>,
> >> +						<44>, <52>,
> >> +						<53>, <54>,
> >> +						<135>;
> >> +				clock-output-names = "bus_mipidsi", "bus_ce",
> >> +						"bus_dma", "bus_mmc0",
> >> +						"bus_mmc1", "bus_mmc2",
> >> +						"bus_nand", "bus_sdram",
> >> +						"bus_ts", "bus_hstimer",
> >> +						"bus_spi0", "bus_spi1",
> >> +						"bus_otg", "bus_otg_ehci0",
> >> +						"bus_ehci0", "bus_otg_ohci0",
> >> +						"bus_ve", "bus_lcd0",
> >> +						"bus_lcd1", "bus_deint",
> >> +						"bus_csi", "bus_hdmi",
> >> +						"bus_de", "bus_gpu",
> >> +						"bus_msgbox", "bus_spinlock",
> >> +						"bus_dbg";
> >> +			};
> >> +			ahb2_parent {
> >> +				clocks = <&ahb2>;
> >> +				clock-indices = <17>, <29>;
> >> +				clock-output-names = "bus_gmac", "bus_ohci0";
> >> +			};
> >> +			apb1_parent {
> >> +				clocks = <&apb1>;
> >> +				clock-indices = <64>, <65>,
> >> +						<69>, <72>,
> >> +						<76>, <77>,
> >> +						<78>;
> >> +				clock-output-names = "bus_codec", "bus_spdif",
> >> +						"bus_pio", "bus_ths",
> >> +						"bus_i2s0", "bus_i2s1",
> >> +						"bus_i2s2";
> >> +			};
> >> +			abp2_parent {
> >> +				clocks = <&apb2>;
> >> +				clock-indices = <96>, <97>,
> >> +						<98>, <101>,
> >> +						<112>, <113>,
> >> +						<114>, <115>,
> >> +						<116>;
> >> +				clock-output-names = "bus_i2c0", "bus_i2c1",
> >> +						"bus_i2c2", "bus_scr",
> >> +						"bus_uart0", "bus_uart1",
> >> +						"bus_uart2", "bus_uart3",
> >> +						"bus_uart4";
> >> +			};
> >> +		};
> > 
> > As I've already told you I'm not really fond of this one, for two main
> > topics.
> > 
> > The first one is about the DT bindings itself which is quite exotic,
> > especially the fact that you define clocks using clocks, clock-indices
> > and clock-output-names in nodes that are not the one referred to by
> > consumer, which goes against both the clock bindings documentation and
> > the usage.
> 
> You are right in one point: it is not documented. I just see that I
> forgot to update the bindings doc and describe this behaviour there.
> 
> But I don't see an issue with abstracting the clock provider's internal
> details by referring to the parent node and use the DT's natural tree
> structure to properly represent these clock gates. I cannot read
> anything in clock-bindings.txt that would prevent this.
> 
> Happy to hear from DT maintainers about it.
> 
> > The second one is pretty much the same one than for the discussion we
> > had about pinctrl. There is SoCs where we simply don't have that
> > information, or at least are not really sure about what to put where
> > (namely, the A83t). In such a case, we would knowingly put invalid
> > information in the DT, which is already quite bad in itself.
> 
> And in your case we would put knowingly invalid information into the kernel?
> So what is wrong with just _not_ putting this information until we know
> it? With my patch you would just enumerate the gates we know the parents
> of so far.

And what happens when you simply don't have that information?

> Once we learn about the other gates, we add them. If we don't
> know the parent, we probably can't use it anyway, I guess.
> So we do as we do with other new features: updated DTs provide new
> functionality.

The issue is broader than that. It basically boils down to that: What
is your fixing strategy in case one of the clocks you put there
doesn't belong to the right parent?

> And also: this is about A64, not A83t.

If the driver is generic, it should not be just about the A64,
otherwise it's simply not generic.

> > The worst part is, when we will identify issues and fix them
> > (hopefully), there will be no way to fix the current DT users.
> 
> But if we have a broken DT out there where a feature never worked or had
> bugs, we _can_ fix it. Interested users will upgrade their DT and are
> able to use the new feature or run without bugs now. This mimics the
> approach when we add features: users update. However if users are happy
> with the current feature set or are not affected by the bug, they can
> use the older DT.

So basically, you just tell "if you want to be as bug free and
featureful as possible, always keep your DT as up to date as
possible". Isn't that the exact same situation than before that whole
DT ABI debate?

> Also from my point of view it is much harder to provide an updated
> kernel to people, since every distribution would need to pick up the
> changes and provide updates to their users.

Do you know a single linux distribution that doesn't update the kernel
to the latest stable kernel version?

> 
> > And it just became a pain to maintain in the long run.
> 
> How so?
> 
> > On the opposite side, having something like the H3 bus gates driver
> > address all these concerns and is easily extensible, which is why we
> > ended up merging it.
> 
> Speaking of this driver: I really dislike that it hardcodes Soc specific
> information into the kernel. I consider this bad style. The clock gates
> are a rather generic functionality (one bit per gate), and we provide
> the SoC specific part (mapping names and bit numbers) already in the DT.
> So with the parent relation in the code we hide some information from
> the DT which clearly belongs there, also ending up with having something
> in the kernel and something in the DT.

It's true to some extent, but it's also something that is not critical
in any way: a typo'd name or a missing index will not affect the
system in any way. A wrong parent relationship might completely crash
the system if the actual parent is not enabled and you try to access
the device.

> Also this requires to add support for each and every SoC explicitly in
> the kernel.

Which is something that you already have to do for any other drivers.

> Also please keep in mind that the DT is not just for Linux: why should
> other OS developers hard code the same information over and over again
> when we could have it once for everybody in the DT?

Since the "other OS developers" don't care about our bindings anyway and
make up their own, is that really something we should care about?

> I think we should stop with supporting each and every SoC explicitly in
> the kernel and go for more generic drivers, that use DTs to describe
> each SoC.
> That way we can eventually reach the point where we have (at least)
> basic functionality for a new SoC in existing(!) kernels - like from a
> LTS style distribution kernel.

It's an argument that has been used since basically the switch to the
device tree, and it never happened, because there's basically no such
thing as a generic driver.

Let's take the example of the A64: we had a driver that was common to
all the SoCs so far for the MMC and MMC clocks, which was working fine
for all of them, so I guess it would be elligible to your definition
of generic. Comes the A64, with its modified phase behaviour, and a
MMC clock factor. Is it really something you expect to support without
a single change to the MMC driver and clocks driver?

This also goes against the whole policy of the clock framework for the
past couple of years to put less information in the DT. Mike asked
repeatedly to switch to a single clock controller node, and have a
driver that is registering everything, instead of exposing each and
every clock in the DT.

It's something we never took the time to do because we knew that we
could switch to it at any point in time. If you want to really have a
stable DT for the A64, then please use that scheme so that we never
have to switch to it in the future and break the ABI.

> New SoCs would just come with their DTs as part of their firmware, as
> it's the case with many arm64 boards out there at the moment. As long as
> they don't have fundamentally new IP blocks (for the basic
> functionality), that could just work out of the box.

Who would provide that firmware? The vendor? Whose binding were never
ever reviewed?

> >> +		pio: pinctrl@01c20800 {
> >> +			compatible = "allwinner,a64-pinctrl";
> >> +			reg = <0x01c20800 0x400>;
> >> +			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> >> +				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> >> +				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> >> +			clocks = <&bus_gates 69>;
> >> +			gpio-controller;
> >> +			#gpio-cells = <3>;
> >> +			interrupt-controller;
> >> +			#interrupt-cells = <2>;
> >> +
> >> +			uart0_pins_a: uart0@0 {
> >> +				allwinner,pins = "PB8", "PB9";
> >> +				allwinner,function = "uart0";
> >> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> >> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> >> +			};
> >> +
> >> +			uart0_pins_b: uart0@1 {
> >> +				allwinner,pins = "PF2", "PF3";
> >> +				allwinner,function = "uart0";
> >> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> >> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> >> +			};
> >> +
> >> +			uart1_pins: uart1@0 {
> >> +				allwinner,pins = "PG6", "PG7", "PG8", "PG9";
> >> +				allwinner,function = "uart1";
> >> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> >> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> >> +			};
> >> +
> >> +			uart2_pins: uart2@0 {
> >> +				allwinner,pins = "PB0", "PB1", "PB2", "PB3";
> >> +				allwinner,function = "uart2";
> >> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> >> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> >> +			};
> >> +
> >> +			uart3_pins_a: uart3@0 {
> >> +				allwinner,pins = "PD0", "PD1";
> >> +				allwinner,function = "uart3";
> >> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> >> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> >> +			};
> >> +
> >> +			uart3_pins_b: uart3@1 {
> >> +				allwinner,pins = "PH4", "PH5", "PH6", "PH7";
> >> +				allwinner,function = "uart3";
> >> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> >> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> >> +			};
> > 
> > You have several options for all these controllers, which is why we
> > have the _a or _b suffices.
> > 
> > Usually, the uart pins we had were only using RX and TX, I guess you
> > could add a separate node for the RTS / CTS pins if some board want to
> > use them.
> 
> Makes sense. Do you want the RTS/CTS pins in a separate child node or
> another variant (like uart3_pins_b_hwhs) with all four pins in addition
> to the two-pin version?

I think we can have RTS/CTS alone in a separate node, just like we
already do for the SPI and its chip select, where each board can then
pick the combination it uses, without duplicating pins definitions.

Thanks (and sorry again for the slow answer),
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH 11/11] arm64: dts: add Pine64 support

[Andre Przywara]

The Pine64 is a cost-efficient development board based on the
Allwinner A64 SoC.
There are three models: the basic version with Fast Ethernet and
512 MB of DRAM (Pine64) and two Pine64+ versions, which both
feature Gigabit Ethernet and additional connectors for touchscreens
and a camera. Or as my son put it: "Those are smaller and these are
missing." ;-)
The two Pine64+ models just differ in the amount of DRAM
(1GB vs. 2GB). Since U-Boot will figure out the right size for us and
patches the DT accordingly we just need to provide one DT for the
Pine64+.

Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
---
 .../devicetree/bindings/vendor-prefixes.txt        |  1 +
 arch/arm64/boot/dts/Makefile                       |  1 +
 arch/arm64/boot/dts/allwinner/Makefile             |  5 ++
 arch/arm64/boot/dts/allwinner/pine64.dts           | 58 +++++++++++++++++
 arch/arm64/boot/dts/allwinner/pine64_common.dtsi   | 76 ++++++++++++++++++++++
 arch/arm64/boot/dts/allwinner/pine64_plus.dts      | 59 +++++++++++++++++
 6 files changed, 200 insertions(+)
 create mode 100644 arch/arm64/boot/dts/allwinner/Makefile
 create mode 100644 arch/arm64/boot/dts/allwinner/pine64.dts
 create mode 100644 arch/arm64/boot/dts/allwinner/pine64_common.dtsi
 create mode 100644 arch/arm64/boot/dts/allwinner/pine64_plus.dts

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 72e2c5a..0c22fa9 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -175,6 +175,7 @@ parade	Parade Technologies Inc.
 pericom	Pericom Technology Inc.
 phytec	PHYTEC Messtechnik GmbH
 picochip	Picochip Ltd
+pine64	Pine64
 plathome	Plat'Home Co., Ltd.
 plda	PLDA
 pixcir  PIXCIR MICROELECTRONICS Co., Ltd
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index f832b8a..3b7428a 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,4 @@
+dts-dirs += allwinner
 dts-dirs += altera
 dts-dirs += amd
 dts-dirs += apm
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
new file mode 100644
index 0000000..65f4e24
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_SUNXI) += pine64_plus.dtb pine64.dtb
+
+always		:= $(dtb-y)
+subdir-y	:= $(dts-dirs)
+clean-files	:= *.dtb
diff --git a/arch/arm64/boot/dts/allwinner/pine64.dts b/arch/arm64/boot/dts/allwinner/pine64.dts
new file mode 100644
index 0000000..ebea5dd
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/pine64.dts
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "pine64_common.dtsi"
+
+/ {
+	model = "Pine64";
+	compatible = "pine64,pine64", "allwinner,a64", "allwinner,sunxi";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		reg = <0x40000000 0x20000000>;
+	};
+};
diff --git a/arch/arm64/boot/dts/allwinner/pine64_common.dtsi b/arch/arm64/boot/dts/allwinner/pine64_common.dtsi
new file mode 100644
index 0000000..d968d76
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/pine64_common.dtsi
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "a64.dtsi"
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins>, <&mmc0_default_cd_pin>;
+	vmmc-supply = <&reg_vcc3v3>;
+	cd-gpios = <&pio 5 6 0>;
+	cd-inverted;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pins>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins_a>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart4_pins>;
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/allwinner/pine64_plus.dts b/arch/arm64/boot/dts/allwinner/pine64_plus.dts
new file mode 100644
index 0000000..344752e
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/pine64_plus.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "pine64_common.dtsi"
+
+/ {
+	model = "Pine64+";
+	compatible = "pine64,pine64_plus", "allwinner,a64", "allwinner,sunxi";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	/* There is a model with 2GB of DRAM, but U-Boot fixes this for us. */
+	memory {
+		reg = <0x40000000 0x40000000>;
+	};
+};
-- 
2.6.4

Re: [linux-sunxi] [PATCH 11/11] arm64: dts: add Pine64 support

[Karsten Merker]

On Mon, Feb 01, 2016 at 05:39:30PM +0000, Andre Przywara wrote:
> The Pine64 is a cost-efficient development board based on the
> Allwinner A64 SoC.
> There are three models: the basic version with Fast Ethernet and
> 512 MB of DRAM (Pine64) and two Pine64+ versions, which both
> feature Gigabit Ethernet and additional connectors for touchscreens
> and a camera. Or as my son put it: "Those are smaller and these are
> missing." ;-)
> The two Pine64+ models just differ in the amount of DRAM
> (1GB vs. 2GB). Since U-Boot will figure out the right size for us and
> patches the DT accordingly we just need to provide one DT for the
> Pine64+.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  .../devicetree/bindings/vendor-prefixes.txt        |  1 +
>  arch/arm64/boot/dts/Makefile                       |  1 +
>  arch/arm64/boot/dts/allwinner/Makefile             |  5 ++
>  arch/arm64/boot/dts/allwinner/pine64.dts           | 58 +++++++++++++++++
>  arch/arm64/boot/dts/allwinner/pine64_common.dtsi   | 76 ++++++++++++++++++++++
>  arch/arm64/boot/dts/allwinner/pine64_plus.dts      | 59 +++++++++++++++++
>  6 files changed, 200 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/allwinner/Makefile
>  create mode 100644 arch/arm64/boot/dts/allwinner/pine64.dts
>  create mode 100644 arch/arm64/boot/dts/allwinner/pine64_common.dtsi
>  create mode 100644 arch/arm64/boot/dts/allwinner/pine64_plus.dts
> 
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index 72e2c5a..0c22fa9 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -175,6 +175,7 @@ parade	Parade Technologies Inc.
>  pericom	Pericom Technology Inc.
>  phytec	PHYTEC Messtechnik GmbH
>  picochip	Picochip Ltd
> +pine64	Pine64
>  plathome	Plat'Home Co., Ltd.
>  plda	PLDA
>  pixcir  PIXCIR MICROELECTRONICS Co., Ltd
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index f832b8a..3b7428a 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -1,3 +1,4 @@
> +dts-dirs += allwinner
>  dts-dirs += altera
>  dts-dirs += amd
>  dts-dirs += apm
> diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
> new file mode 100644
> index 0000000..65f4e24
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/Makefile
> @@ -0,0 +1,5 @@
> +dtb-$(CONFIG_ARCH_SUNXI) += pine64_plus.dtb pine64.dtb
> +
> +always		:= $(dtb-y)
> +subdir-y	:= $(dts-dirs)
> +clean-files	:= *.dtb
> diff --git a/arch/arm64/boot/dts/allwinner/pine64.dts b/arch/arm64/boot/dts/allwinner/pine64.dts

Please see my followups to patch No. 5 and patch No. 10 in this series.
s/pine64.dts/sun50i-pine64.dts/ ?

> new file mode 100644
> index 0000000..ebea5dd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/pine64.dts
> @@ -0,0 +1,58 @@
> +/*
> + * Copyright (c) 2016 ARM Ltd.
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This library is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This library is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +
> +#include "pine64_common.dtsi"

see above

Also a minor spelling nitpick: the other *common* dts/dtsi files
use dashes instead of underscores, so with regard to naming
consistency I would like to propose doing it the same way here.

> +
> +/ {
> +	model = "Pine64";
> +	compatible = "pine64,pine64", "allwinner,a64", "allwinner,sunxi";

see above

> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory {
> +		reg = <0x40000000 0x20000000>;
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/allwinner/pine64_common.dtsi b/arch/arm64/boot/dts/allwinner/pine64_common.dtsi

see above

> new file mode 100644
> index 0000000..d968d76
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/pine64_common.dtsi
> @@ -0,0 +1,76 @@
> +/*
> + * Copyright (c) 2016 ARM Ltd.
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This library is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This library is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include "a64.dtsi"

see above

> +
> +&mmc0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mmc0_pins>, <&mmc0_default_cd_pin>;
> +	vmmc-supply = <&reg_vcc3v3>;
> +	cd-gpios = <&pio 5 6 0>;
> +	cd-inverted;
> +	status = "okay";
> +};
> +
> +&uart0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart0_pins_a>;
> +	status = "okay";
> +};
> +
> +&uart2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart2_pins>;
> +	status = "okay";
> +};
> +
> +&uart3 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart3_pins_a>;
> +	status = "okay";
> +};
> +
> +&uart4 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart4_pins>;
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/allwinner/pine64_plus.dts b/arch/arm64/boot/dts/allwinner/pine64_plus.dts
> new file mode 100644
> index 0000000..344752e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/pine64_plus.dts

see above

> @@ -0,0 +1,59 @@
> +/*
> + * Copyright (c) 2016 ARM Ltd.
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This library is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This library is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +
> +#include "pine64_common.dtsi"

see above

> +
> +/ {
> +	model = "Pine64+";
> +	compatible = "pine64,pine64_plus", "allwinner,a64", "allwinner,sunxi";

see above

> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	/* There is a model with 2GB of DRAM, but U-Boot fixes this for us. */
> +	memory {
> +		reg = <0x40000000 0x40000000>;
> +	};
> +};
> -- 
> 2.6.4

Regards,
Karsten
-- 
Gem. Par. 28 Abs. 4 Bundesdatenschutzgesetz widerspreche ich der Nutzung
sowie der Weitergabe meiner personenbezogenen Daten für Zwecke der
Werbung sowie der Markt- oder Meinungsforschung.

Re: [PATCH 11/11] arm64: dts: add Pine64 support

[André Przywara]

On 01/02/16 19:22, Karsten Merker wrote:

Hi,

> On Mon, Feb 01, 2016 at 05:39:30PM +0000, Andre Przywara wrote:
>> The Pine64 is a cost-efficient development board based on the
>> Allwinner A64 SoC.
>> There are three models: the basic version with Fast Ethernet and
>> 512 MB of DRAM (Pine64) and two Pine64+ versions, which both
>> feature Gigabit Ethernet and additional connectors for touchscreens
>> and a camera. Or as my son put it: "Those are smaller and these are
>> missing." ;-)
>> The two Pine64+ models just differ in the amount of DRAM
>> (1GB vs. 2GB). Since U-Boot will figure out the right size for us and
>> patches the DT accordingly we just need to provide one DT for the
>> Pine64+.
>>
>> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
>> ---
>>  .../devicetree/bindings/vendor-prefixes.txt        |  1 +
>>  arch/arm64/boot/dts/Makefile                       |  1 +
>>  arch/arm64/boot/dts/allwinner/Makefile             |  5 ++
>>  arch/arm64/boot/dts/allwinner/pine64.dts           | 58 +++++++++++++++++
>>  arch/arm64/boot/dts/allwinner/pine64_common.dtsi   | 76 ++++++++++++++++++++++
>>  arch/arm64/boot/dts/allwinner/pine64_plus.dts      | 59 +++++++++++++++++
>>  6 files changed, 200 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/allwinner/Makefile
>>  create mode 100644 arch/arm64/boot/dts/allwinner/pine64.dts
>>  create mode 100644 arch/arm64/boot/dts/allwinner/pine64_common.dtsi
>>  create mode 100644 arch/arm64/boot/dts/allwinner/pine64_plus.dts
>>
>> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
>> index 72e2c5a..0c22fa9 100644
>> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
>> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
>> @@ -175,6 +175,7 @@ parade	Parade Technologies Inc.
>>  pericom	Pericom Technology Inc.
>>  phytec	PHYTEC Messtechnik GmbH
>>  picochip	Picochip Ltd
>> +pine64	Pine64
>>  plathome	Plat'Home Co., Ltd.
>>  plda	PLDA
>>  pixcir  PIXCIR MICROELECTRONICS Co., Ltd
>> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
>> index f832b8a..3b7428a 100644
>> --- a/arch/arm64/boot/dts/Makefile
>> +++ b/arch/arm64/boot/dts/Makefile
>> @@ -1,3 +1,4 @@
>> +dts-dirs += allwinner
>>  dts-dirs += altera
>>  dts-dirs += amd
>>  dts-dirs += apm
>> diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
>> new file mode 100644
>> index 0000000..65f4e24
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/allwinner/Makefile
>> @@ -0,0 +1,5 @@
>> +dtb-$(CONFIG_ARCH_SUNXI) += pine64_plus.dtb pine64.dtb
>> +
>> +always		:= $(dtb-y)
>> +subdir-y	:= $(dts-dirs)
>> +clean-files	:= *.dtb
>> diff --git a/arch/arm64/boot/dts/allwinner/pine64.dts b/arch/arm64/boot/dts/allwinner/pine64.dts
> 
> Please see my followups to patch No. 5 and patch No. 10 in this series.
> s/pine64.dts/sun50i-pine64.dts/ ?

Really? Actually this should be more like pine64-pine64.dts, but since
the company name is identical to their (first?) product, I found it
rather weird to have this double naming.
The ARM DTs for instance are also just "juno.dts" and "juno-r1.dts".

> 
>> new file mode 100644
>> index 0000000..ebea5dd
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/allwinner/pine64.dts
>> @@ -0,0 +1,58 @@
>> +/*
>> + * Copyright (c) 2016 ARM Ltd.
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This library is free software; you can redistribute it and/or
>> + *     modify it under the terms of the GNU General Public License as
>> + *     published by the Free Software Foundation; either version 2 of the
>> + *     License, or (at your option) any later version.
>> + *
>> + *     This library is distributed in the hope that it will be useful,
>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + *     GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + *     obtaining a copy of this software and associated documentation
>> + *     files (the "Software"), to deal in the Software without
>> + *     restriction, including without limitation the rights to use,
>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
>> + *     sell copies of the Software, and to permit persons to whom the
>> + *     Software is furnished to do so, subject to the following
>> + *     conditions:
>> + *
>> + *     The above copyright notice and this permission notice shall be
>> + *     included in all copies or substantial portions of the Software.
>> + *
>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + *     OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "pine64_common.dtsi"
> 
> see above
> 
> Also a minor spelling nitpick: the other *common* dts/dtsi files
> use dashes instead of underscores, so with regard to naming
> consistency I would like to propose doing it the same way here.

Good point, will fix it!

Repeated rationale for the below comments.

Cheers,
Andre.

> 
>> +
>> +/ {
>> +	model = "Pine64";
>> +	compatible = "pine64,pine64", "allwinner,a64", "allwinner,sunxi";
> 
> see above
> 
>> +
>> +	chosen {
>> +		stdout-path = "serial0:115200n8";
>> +	};
>> +
>> +	memory {
>> +		reg = <0x40000000 0x20000000>;
>> +	};
>> +};
>> diff --git a/arch/arm64/boot/dts/allwinner/pine64_common.dtsi b/arch/arm64/boot/dts/allwinner/pine64_common.dtsi
> 
> see above
> 
>> new file mode 100644
>> index 0000000..d968d76
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/allwinner/pine64_common.dtsi
>> @@ -0,0 +1,76 @@
>> +/*
>> + * Copyright (c) 2016 ARM Ltd.
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This library is free software; you can redistribute it and/or
>> + *     modify it under the terms of the GNU General Public License as
>> + *     published by the Free Software Foundation; either version 2 of the
>> + *     License, or (at your option) any later version.
>> + *
>> + *     This library is distributed in the hope that it will be useful,
>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + *     GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + *     obtaining a copy of this software and associated documentation
>> + *     files (the "Software"), to deal in the Software without
>> + *     restriction, including without limitation the rights to use,
>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
>> + *     sell copies of the Software, and to permit persons to whom the
>> + *     Software is furnished to do so, subject to the following
>> + *     conditions:
>> + *
>> + *     The above copyright notice and this permission notice shall be
>> + *     included in all copies or substantial portions of the Software.
>> + *
>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + *     OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +#include "a64.dtsi"
> 
> see above
> 
>> +
>> +&mmc0 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&mmc0_pins>, <&mmc0_default_cd_pin>;
>> +	vmmc-supply = <&reg_vcc3v3>;
>> +	cd-gpios = <&pio 5 6 0>;
>> +	cd-inverted;
>> +	status = "okay";
>> +};
>> +
>> +&uart0 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&uart0_pins_a>;
>> +	status = "okay";
>> +};
>> +
>> +&uart2 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&uart2_pins>;
>> +	status = "okay";
>> +};
>> +
>> +&uart3 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&uart3_pins_a>;
>> +	status = "okay";
>> +};
>> +
>> +&uart4 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&uart4_pins>;
>> +	status = "okay";
>> +};
>> diff --git a/arch/arm64/boot/dts/allwinner/pine64_plus.dts b/arch/arm64/boot/dts/allwinner/pine64_plus.dts
>> new file mode 100644
>> index 0000000..344752e
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/allwinner/pine64_plus.dts
> 
> see above
> 
>> @@ -0,0 +1,59 @@
>> +/*
>> + * Copyright (c) 2016 ARM Ltd.
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This library is free software; you can redistribute it and/or
>> + *     modify it under the terms of the GNU General Public License as
>> + *     published by the Free Software Foundation; either version 2 of the
>> + *     License, or (at your option) any later version.
>> + *
>> + *     This library is distributed in the hope that it will be useful,
>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + *     GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + *     obtaining a copy of this software and associated documentation
>> + *     files (the "Software"), to deal in the Software without
>> + *     restriction, including without limitation the rights to use,
>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
>> + *     sell copies of the Software, and to permit persons to whom the
>> + *     Software is furnished to do so, subject to the following
>> + *     conditions:
>> + *
>> + *     The above copyright notice and this permission notice shall be
>> + *     included in all copies or substantial portions of the Software.
>> + *
>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + *     OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "pine64_common.dtsi"
> 
> see above
> 
>> +
>> +/ {
>> +	model = "Pine64+";
>> +	compatible = "pine64,pine64_plus", "allwinner,a64", "allwinner,sunxi";
> 
> see above
> 
>> +
>> +	chosen {
>> +		stdout-path = "serial0:115200n8";
>> +	};
>> +
>> +	/* There is a model with 2GB of DRAM, but U-Boot fixes this for us. */
>> +	memory {
>> +		reg = <0x40000000 0x40000000>;
>> +	};
>> +};
>> -- 
>> 2.6.4
> 
> Regards,
> Karsten
> 

Re: [PATCH 11/11] arm64: dts: add Pine64 support

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 11390 bytes --]

Hi,

On Mon, Feb 01, 2016 at 05:39:30PM +0000, Andre Przywara wrote:
> The Pine64 is a cost-efficient development board based on the
> Allwinner A64 SoC.
> There are three models: the basic version with Fast Ethernet and
> 512 MB of DRAM (Pine64) and two Pine64+ versions, which both
> feature Gigabit Ethernet and additional connectors for touchscreens
> and a camera. Or as my son put it: "Those are smaller and these are
> missing." ;-)
> The two Pine64+ models just differ in the amount of DRAM
> (1GB vs. 2GB). Since U-Boot will figure out the right size for us and
> patches the DT accordingly we just need to provide one DT for the
> Pine64+.
> 
> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
> ---
>  .../devicetree/bindings/vendor-prefixes.txt        |  1 +
>  arch/arm64/boot/dts/Makefile                       |  1 +
>  arch/arm64/boot/dts/allwinner/Makefile             |  5 ++
>  arch/arm64/boot/dts/allwinner/pine64.dts           | 58 +++++++++++++++++
>  arch/arm64/boot/dts/allwinner/pine64_common.dtsi   | 76 ++++++++++++++++++++++
>  arch/arm64/boot/dts/allwinner/pine64_plus.dts      | 59 +++++++++++++++++
>  6 files changed, 200 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/allwinner/Makefile
>  create mode 100644 arch/arm64/boot/dts/allwinner/pine64.dts
>  create mode 100644 arch/arm64/boot/dts/allwinner/pine64_common.dtsi
>  create mode 100644 arch/arm64/boot/dts/allwinner/pine64_plus.dts
> 
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index 72e2c5a..0c22fa9 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -175,6 +175,7 @@ parade	Parade Technologies Inc.
>  pericom	Pericom Technology Inc.
>  phytec	PHYTEC Messtechnik GmbH
>  picochip	Picochip Ltd
> +pine64	Pine64
>  plathome	Plat'Home Co., Ltd.
>  plda	PLDA
>  pixcir  PIXCIR MICROELECTRONICS Co., Ltd

Please make a separate patch for this one.

> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index f832b8a..3b7428a 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -1,3 +1,4 @@
> +dts-dirs += allwinner

Could you also add a patch to add this path to MAINTAINERS too?

>  dts-dirs += altera
>  dts-dirs += amd
>  dts-dirs += apm
> diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
> new file mode 100644
> index 0000000..65f4e24
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/Makefile
> @@ -0,0 +1,5 @@
> +dtb-$(CONFIG_ARCH_SUNXI) += pine64_plus.dtb pine64.dtb
> +
> +always		:= $(dtb-y)
> +subdir-y	:= $(dts-dirs)
> +clean-files	:= *.dtb
> diff --git a/arch/arm64/boot/dts/allwinner/pine64.dts b/arch/arm64/boot/dts/allwinner/pine64.dts
> new file mode 100644
> index 0000000..ebea5dd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/pine64.dts
> @@ -0,0 +1,58 @@
> +/*
> + * Copyright (c) 2016 ARM Ltd.
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This library is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This library is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +
> +#include "pine64_common.dtsi"
> +
> +/ {
> +	model = "Pine64";
> +	compatible = "pine64,pine64", "allwinner,a64", "allwinner,sunxi";
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory {
> +		reg = <0x40000000 0x20000000>;
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/allwinner/pine64_common.dtsi b/arch/arm64/boot/dts/allwinner/pine64_common.dtsi
> new file mode 100644
> index 0000000..d968d76
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/pine64_common.dtsi
> @@ -0,0 +1,76 @@
> +/*
> + * Copyright (c) 2016 ARM Ltd.
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This library is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This library is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include "a64.dtsi"
> +
> +&mmc0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mmc0_pins>, <&mmc0_default_cd_pin>;
> +	vmmc-supply = <&reg_vcc3v3>;
> +	cd-gpios = <&pio 5 6 0>;
> +	cd-inverted;
> +	status = "okay";
> +};
> +
> +&uart0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart0_pins_a>;
> +	status = "okay";
> +};
> +
> +&uart2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart2_pins>;
> +	status = "okay";
> +};
> +
> +&uart3 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart3_pins_a>;
> +	status = "okay";
> +};
> +
> +&uart4 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart4_pins>;
> +	status = "okay";
> +};

Our policy for boards with "open" pin headers the user can plug
anything he wants is that unless the pin is explicitly dedicated to
that usage, we simply leave them aside so that we don't enforce
anything.

>From the quick look at the schematics, I guess only the UART0 on the
10-pin expansion header is elligible.

> diff --git a/arch/arm64/boot/dts/allwinner/pine64_plus.dts b/arch/arm64/boot/dts/allwinner/pine64_plus.dts
> new file mode 100644
> index 0000000..344752e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/pine64_plus.dts
> @@ -0,0 +1,59 @@
> +/*
> + * Copyright (c) 2016 ARM Ltd.
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This library is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This library is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +
> +#include "pine64_common.dtsi"
> +
> +/ {
> +	model = "Pine64+";
> +	compatible = "pine64,pine64_plus", "allwinner,a64", "allwinner,sunxi";

The usual separator in the compatibles is a dash and not an underscore.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH 11/11] arm64: dts: add Pine64 support

[Andre Przywara]

Hi,

On 05/02/16 09:03, Maxime Ripard wrote:
> Hi,
> 
> On Mon, Feb 01, 2016 at 05:39:30PM +0000, Andre Przywara wrote:
>> The Pine64 is a cost-efficient development board based on the
>> Allwinner A64 SoC.
>> There are three models: the basic version with Fast Ethernet and
>> 512 MB of DRAM (Pine64) and two Pine64+ versions, which both
>> feature Gigabit Ethernet and additional connectors for touchscreens
>> and a camera. Or as my son put it: "Those are smaller and these are
>> missing." ;-)
>> The two Pine64+ models just differ in the amount of DRAM
>> (1GB vs. 2GB). Since U-Boot will figure out the right size for us and
>> patches the DT accordingly we just need to provide one DT for the
>> Pine64+.
>>
>> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
>> ---
>>  .../devicetree/bindings/vendor-prefixes.txt        |  1 +
>>  arch/arm64/boot/dts/Makefile                       |  1 +
>>  arch/arm64/boot/dts/allwinner/Makefile             |  5 ++
>>  arch/arm64/boot/dts/allwinner/pine64.dts           | 58 +++++++++++++++++
>>  arch/arm64/boot/dts/allwinner/pine64_common.dtsi   | 76 ++++++++++++++++++++++
>>  arch/arm64/boot/dts/allwinner/pine64_plus.dts      | 59 +++++++++++++++++
>>  6 files changed, 200 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/allwinner/Makefile
>>  create mode 100644 arch/arm64/boot/dts/allwinner/pine64.dts
>>  create mode 100644 arch/arm64/boot/dts/allwinner/pine64_common.dtsi
>>  create mode 100644 arch/arm64/boot/dts/allwinner/pine64_plus.dts
>>
>> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
>> index 72e2c5a..0c22fa9 100644
>> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
>> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
>> @@ -175,6 +175,7 @@ parade	Parade Technologies Inc.
>>  pericom	Pericom Technology Inc.
>>  phytec	PHYTEC Messtechnik GmbH
>>  picochip	Picochip Ltd
>> +pine64	Pine64
>>  plathome	Plat'Home Co., Ltd.
>>  plda	PLDA
>>  pixcir  PIXCIR MICROELECTRONICS Co., Ltd
> 
> Please make a separate patch for this one.
> 
>> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
>> index f832b8a..3b7428a 100644
>> --- a/arch/arm64/boot/dts/Makefile
>> +++ b/arch/arm64/boot/dts/Makefile
>> @@ -1,3 +1,4 @@
>> +dts-dirs += allwinner
> 
> Could you also add a patch to add this path to MAINTAINERS too?
> 
>>  dts-dirs += altera
>>  dts-dirs += amd
>>  dts-dirs += apm
>> diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
>> new file mode 100644
>> index 0000000..65f4e24
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/allwinner/Makefile
>> @@ -0,0 +1,5 @@
>> +dtb-$(CONFIG_ARCH_SUNXI) += pine64_plus.dtb pine64.dtb
>> +
>> +always		:= $(dtb-y)
>> +subdir-y	:= $(dts-dirs)
>> +clean-files	:= *.dtb
>> diff --git a/arch/arm64/boot/dts/allwinner/pine64.dts b/arch/arm64/boot/dts/allwinner/pine64.dts
>> new file mode 100644
>> index 0000000..ebea5dd
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/allwinner/pine64.dts
>> @@ -0,0 +1,58 @@
>> +/*
>> + * Copyright (c) 2016 ARM Ltd.
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This library is free software; you can redistribute it and/or
>> + *     modify it under the terms of the GNU General Public License as
>> + *     published by the Free Software Foundation; either version 2 of the
>> + *     License, or (at your option) any later version.
>> + *
>> + *     This library is distributed in the hope that it will be useful,
>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + *     GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + *     obtaining a copy of this software and associated documentation
>> + *     files (the "Software"), to deal in the Software without
>> + *     restriction, including without limitation the rights to use,
>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
>> + *     sell copies of the Software, and to permit persons to whom the
>> + *     Software is furnished to do so, subject to the following
>> + *     conditions:
>> + *
>> + *     The above copyright notice and this permission notice shall be
>> + *     included in all copies or substantial portions of the Software.
>> + *
>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + *     OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "pine64_common.dtsi"
>> +
>> +/ {
>> +	model = "Pine64";
>> +	compatible = "pine64,pine64", "allwinner,a64", "allwinner,sunxi";
>> +
>> +	chosen {
>> +		stdout-path = "serial0:115200n8";
>> +	};
>> +
>> +	memory {
>> +		reg = <0x40000000 0x20000000>;
>> +	};
>> +};
>> diff --git a/arch/arm64/boot/dts/allwinner/pine64_common.dtsi b/arch/arm64/boot/dts/allwinner/pine64_common.dtsi
>> new file mode 100644
>> index 0000000..d968d76
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/allwinner/pine64_common.dtsi
>> @@ -0,0 +1,76 @@
>> +/*
>> + * Copyright (c) 2016 ARM Ltd.
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This library is free software; you can redistribute it and/or
>> + *     modify it under the terms of the GNU General Public License as
>> + *     published by the Free Software Foundation; either version 2 of the
>> + *     License, or (at your option) any later version.
>> + *
>> + *     This library is distributed in the hope that it will be useful,
>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + *     GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + *     obtaining a copy of this software and associated documentation
>> + *     files (the "Software"), to deal in the Software without
>> + *     restriction, including without limitation the rights to use,
>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
>> + *     sell copies of the Software, and to permit persons to whom the
>> + *     Software is furnished to do so, subject to the following
>> + *     conditions:
>> + *
>> + *     The above copyright notice and this permission notice shall be
>> + *     included in all copies or substantial portions of the Software.
>> + *
>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + *     OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +#include "a64.dtsi"
>> +
>> +&mmc0 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&mmc0_pins>, <&mmc0_default_cd_pin>;
>> +	vmmc-supply = <&reg_vcc3v3>;
>> +	cd-gpios = <&pio 5 6 0>;
>> +	cd-inverted;
>> +	status = "okay";
>> +};
>> +
>> +&uart0 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&uart0_pins_a>;
>> +	status = "okay";
>> +};
>> +
>> +&uart2 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&uart2_pins>;
>> +	status = "okay";
>> +};
>> +
>> +&uart3 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&uart3_pins_a>;
>> +	status = "okay";
>> +};
>> +
>> +&uart4 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&uart4_pins>;
>> +	status = "okay";
>> +};
> 
> Our policy for boards with "open" pin headers the user can plug
> anything he wants is that unless the pin is explicitly dedicated to
> that usage, we simply leave them aside so that we don't enforce
> anything.

Makes sense, I just wonder what a user is expected to do if she wants to
use the serial ports?
Hack the DT?
Use U-Boot to create those nodes on the fly?
Use overlays?
Directly setup serial ports from userland? (thinking of this bloody
mechanism x86 (used to?) have)

Anyway, thanks for the comments, all make sense and I will fix them.

Cheers,
Andre.

> From the quick look at the schematics, I guess only the UART0 on the
> 10-pin expansion header is elligible.
> 
>> diff --git a/arch/arm64/boot/dts/allwinner/pine64_plus.dts b/arch/arm64/boot/dts/allwinner/pine64_plus.dts
>> new file mode 100644
>> index 0000000..344752e
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/allwinner/pine64_plus.dts
>> @@ -0,0 +1,59 @@
>> +/*
>> + * Copyright (c) 2016 ARM Ltd.
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This library is free software; you can redistribute it and/or
>> + *     modify it under the terms of the GNU General Public License as
>> + *     published by the Free Software Foundation; either version 2 of the
>> + *     License, or (at your option) any later version.
>> + *
>> + *     This library is distributed in the hope that it will be useful,
>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + *     GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + *     obtaining a copy of this software and associated documentation
>> + *     files (the "Software"), to deal in the Software without
>> + *     restriction, including without limitation the rights to use,
>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
>> + *     sell copies of the Software, and to permit persons to whom the
>> + *     Software is furnished to do so, subject to the following
>> + *     conditions:
>> + *
>> + *     The above copyright notice and this permission notice shall be
>> + *     included in all copies or substantial portions of the Software.
>> + *
>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + *     OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "pine64_common.dtsi"
>> +
>> +/ {
>> +	model = "Pine64+";
>> +	compatible = "pine64,pine64_plus", "allwinner,a64", "allwinner,sunxi";
> 
> The usual separator in the compatibles is a dash and not an underscore.
> 
> Thanks!
> Maxime
> 
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Re: [linux-sunxi] Re: [PATCH 11/11] arm64: dts: add Pine64 support

[Julian Calaby]

Hi Andre,

On Fri, Feb 5, 2016 at 9:04 PM, Andre Przywara <andre.przywara@arm.com> wrote:
> Hi,
>
> On 05/02/16 09:03, Maxime Ripard wrote:
>> Hi,
>>
>> On Mon, Feb 01, 2016 at 05:39:30PM +0000, Andre Przywara wrote:
>>> The Pine64 is a cost-efficient development board based on the
>>> Allwinner A64 SoC.
>>> There are three models: the basic version with Fast Ethernet and
>>> 512 MB of DRAM (Pine64) and two Pine64+ versions, which both
>>> feature Gigabit Ethernet and additional connectors for touchscreens
>>> and a camera. Or as my son put it: "Those are smaller and these are
>>> missing." ;-)
>>> The two Pine64+ models just differ in the amount of DRAM
>>> (1GB vs. 2GB). Since U-Boot will figure out the right size for us and
>>> patches the DT accordingly we just need to provide one DT for the
>>> Pine64+.
>>>
>>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>>> ---
>>>  .../devicetree/bindings/vendor-prefixes.txt        |  1 +
>>>  arch/arm64/boot/dts/Makefile                       |  1 +
>>>  arch/arm64/boot/dts/allwinner/Makefile             |  5 ++
>>>  arch/arm64/boot/dts/allwinner/pine64.dts           | 58 +++++++++++++++++
>>>  arch/arm64/boot/dts/allwinner/pine64_common.dtsi   | 76 ++++++++++++++++++++++
>>>  arch/arm64/boot/dts/allwinner/pine64_plus.dts      | 59 +++++++++++++++++
>>>  6 files changed, 200 insertions(+)
>>>  create mode 100644 arch/arm64/boot/dts/allwinner/Makefile
>>>  create mode 100644 arch/arm64/boot/dts/allwinner/pine64.dts
>>>  create mode 100644 arch/arm64/boot/dts/allwinner/pine64_common.dtsi
>>>  create mode 100644 arch/arm64/boot/dts/allwinner/pine64_plus.dts
>>>
>>> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
>>> index 72e2c5a..0c22fa9 100644
>>> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
>>> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
>>> @@ -175,6 +175,7 @@ parade   Parade Technologies Inc.
>>>  pericom     Pericom Technology Inc.
>>>  phytec      PHYTEC Messtechnik GmbH
>>>  picochip    Picochip Ltd
>>> +pine64      Pine64
>>>  plathome    Plat'Home Co., Ltd.
>>>  plda        PLDA
>>>  pixcir  PIXCIR MICROELECTRONICS Co., Ltd
>>
>> Please make a separate patch for this one.
>>
>>> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
>>> index f832b8a..3b7428a 100644
>>> --- a/arch/arm64/boot/dts/Makefile
>>> +++ b/arch/arm64/boot/dts/Makefile
>>> @@ -1,3 +1,4 @@
>>> +dts-dirs += allwinner
>>
>> Could you also add a patch to add this path to MAINTAINERS too?
>>
>>>  dts-dirs += altera
>>>  dts-dirs += amd
>>>  dts-dirs += apm
>>> diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
>>> new file mode 100644
>>> index 0000000..65f4e24
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/allwinner/Makefile
>>> @@ -0,0 +1,5 @@
>>> +dtb-$(CONFIG_ARCH_SUNXI) += pine64_plus.dtb pine64.dtb
>>> +
>>> +always              := $(dtb-y)
>>> +subdir-y    := $(dts-dirs)
>>> +clean-files := *.dtb
>>> diff --git a/arch/arm64/boot/dts/allwinner/pine64.dts b/arch/arm64/boot/dts/allwinner/pine64.dts
>>> new file mode 100644
>>> index 0000000..ebea5dd
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/allwinner/pine64.dts
>>> @@ -0,0 +1,58 @@
>>> +/*
>>> + * Copyright (c) 2016 ARM Ltd.
>>> + *
>>> + * This file is dual-licensed: you can use it either under the terms
>>> + * of the GPL or the X11 license, at your option. Note that this dual
>>> + * licensing only applies to this file, and not this project as a
>>> + * whole.
>>> + *
>>> + *  a) This library is free software; you can redistribute it and/or
>>> + *     modify it under the terms of the GNU General Public License as
>>> + *     published by the Free Software Foundation; either version 2 of the
>>> + *     License, or (at your option) any later version.
>>> + *
>>> + *     This library is distributed in the hope that it will be useful,
>>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>> + *     GNU General Public License for more details.
>>> + *
>>> + * Or, alternatively,
>>> + *
>>> + *  b) Permission is hereby granted, free of charge, to any person
>>> + *     obtaining a copy of this software and associated documentation
>>> + *     files (the "Software"), to deal in the Software without
>>> + *     restriction, including without limitation the rights to use,
>>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
>>> + *     sell copies of the Software, and to permit persons to whom the
>>> + *     Software is furnished to do so, subject to the following
>>> + *     conditions:
>>> + *
>>> + *     The above copyright notice and this permission notice shall be
>>> + *     included in all copies or substantial portions of the Software.
>>> + *
>>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>> + *     OTHER DEALINGS IN THE SOFTWARE.
>>> + */
>>> +
>>> +/dts-v1/;
>>> +
>>> +#include "pine64_common.dtsi"
>>> +
>>> +/ {
>>> +    model = "Pine64";
>>> +    compatible = "pine64,pine64", "allwinner,a64", "allwinner,sunxi";
>>> +
>>> +    chosen {
>>> +            stdout-path = "serial0:115200n8";
>>> +    };
>>> +
>>> +    memory {
>>> +            reg = <0x40000000 0x20000000>;
>>> +    };
>>> +};
>>> diff --git a/arch/arm64/boot/dts/allwinner/pine64_common.dtsi b/arch/arm64/boot/dts/allwinner/pine64_common.dtsi
>>> new file mode 100644
>>> index 0000000..d968d76
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/allwinner/pine64_common.dtsi
>>> @@ -0,0 +1,76 @@
>>> +/*
>>> + * Copyright (c) 2016 ARM Ltd.
>>> + *
>>> + * This file is dual-licensed: you can use it either under the terms
>>> + * of the GPL or the X11 license, at your option. Note that this dual
>>> + * licensing only applies to this file, and not this project as a
>>> + * whole.
>>> + *
>>> + *  a) This library is free software; you can redistribute it and/or
>>> + *     modify it under the terms of the GNU General Public License as
>>> + *     published by the Free Software Foundation; either version 2 of the
>>> + *     License, or (at your option) any later version.
>>> + *
>>> + *     This library is distributed in the hope that it will be useful,
>>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>> + *     GNU General Public License for more details.
>>> + *
>>> + * Or, alternatively,
>>> + *
>>> + *  b) Permission is hereby granted, free of charge, to any person
>>> + *     obtaining a copy of this software and associated documentation
>>> + *     files (the "Software"), to deal in the Software without
>>> + *     restriction, including without limitation the rights to use,
>>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
>>> + *     sell copies of the Software, and to permit persons to whom the
>>> + *     Software is furnished to do so, subject to the following
>>> + *     conditions:
>>> + *
>>> + *     The above copyright notice and this permission notice shall be
>>> + *     included in all copies or substantial portions of the Software.
>>> + *
>>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>> + *     OTHER DEALINGS IN THE SOFTWARE.
>>> + */
>>> +
>>> +#include "a64.dtsi"
>>> +
>>> +&mmc0 {
>>> +    pinctrl-names = "default";
>>> +    pinctrl-0 = <&mmc0_pins>, <&mmc0_default_cd_pin>;
>>> +    vmmc-supply = <&reg_vcc3v3>;
>>> +    cd-gpios = <&pio 5 6 0>;
>>> +    cd-inverted;
>>> +    status = "okay";
>>> +};
>>> +
>>> +&uart0 {
>>> +    pinctrl-names = "default";
>>> +    pinctrl-0 = <&uart0_pins_a>;
>>> +    status = "okay";
>>> +};
>>> +
>>> +&uart2 {
>>> +    pinctrl-names = "default";
>>> +    pinctrl-0 = <&uart2_pins>;
>>> +    status = "okay";
>>> +};
>>> +
>>> +&uart3 {
>>> +    pinctrl-names = "default";
>>> +    pinctrl-0 = <&uart3_pins_a>;
>>> +    status = "okay";
>>> +};
>>> +
>>> +&uart4 {
>>> +    pinctrl-names = "default";
>>> +    pinctrl-0 = <&uart4_pins>;
>>> +    status = "okay";
>>> +};
>>
>> Our policy for boards with "open" pin headers the user can plug
>> anything he wants is that unless the pin is explicitly dedicated to
>> that usage, we simply leave them aside so that we don't enforce
>> anything.
>
> Makes sense, I just wonder what a user is expected to do if she wants to
> use the serial ports?
> Hack the DT?
> Use U-Boot to create those nodes on the fly?
> Use overlays?
> Directly setup serial ports from userland? (thinking of this bloody
> mechanism x86 (used to?) have)

I believe that device tree overlays are the generally recommended method.

Thanks,

-- 
Julian Calaby

Email: julian.calaby@gmail.com
Profile: http://www.google.com/profiles/julian.calaby/

Re: Re: [PATCH 11/11] arm64: dts: add Pine64 support

[Danny Milosavljevic]

Hi,

On Mon, 8 Feb 2016 11:55:43 +1100
Julian Calaby <julian.calaby-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:

> I believe that device tree overlays are the generally recommended method.

I agree. But last time I tried, the device tree compiler didn't 
support overlays - neither in Debian nor in the in-kernel dtc ("-@" is 
unsupported; last tried with linux-4.3-rc7). 

And even if you could compile them, the platform has to support specifying which 
overlays to use in the first place (for example as a Linux cmdline option). 

For example Beaglebone Black (TI Sitara) does. I don't know whether sunxi does.

Also, the overlay dts files are very different from normal dts files, see 
<http://www.patternagents.com/news/2015/01/29/devicetree-overlays.html>.

The original Linux device tree changeset patchset also introduced an in-kernel 
interface for loading/unloading of DT overlays at runtime. AFAIK, this is still 
not available to user space.

More info at <https://lwn.net/Articles/616859/>.

(I tried some 4 months ago - it wasn't integrated enough. 
 So now I just patch the main dts every time - which I probably shouldn't)

Regards,
   Danny

Re: [PATCH 11/11] arm64: dts: add Pine64 support

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1395 bytes --]

Hi Andre,

On Fri, Feb 05, 2016 at 10:04:01AM +0000, Andre Przywara wrote:
> >> +&uart0 {
> >> +	pinctrl-names = "default";
> >> +	pinctrl-0 = <&uart0_pins_a>;
> >> +	status = "okay";
> >> +};
> >> +
> >> +&uart2 {
> >> +	pinctrl-names = "default";
> >> +	pinctrl-0 = <&uart2_pins>;
> >> +	status = "okay";
> >> +};
> >> +
> >> +&uart3 {
> >> +	pinctrl-names = "default";
> >> +	pinctrl-0 = <&uart3_pins_a>;
> >> +	status = "okay";
> >> +};
> >> +
> >> +&uart4 {
> >> +	pinctrl-names = "default";
> >> +	pinctrl-0 = <&uart4_pins>;
> >> +	status = "okay";
> >> +};
> > 
> > Our policy for boards with "open" pin headers the user can plug
> > anything he wants is that unless the pin is explicitly dedicated to
> > that usage, we simply leave them aside so that we don't enforce
> > anything.
> 
> Makes sense, I just wonder what a user is expected to do if she wants to
> use the serial ports?
> Hack the DT?
> Use U-Boot to create those nodes on the fly?
> Use overlays?
> Directly setup serial ports from userland? (thinking of this bloody
> mechanism x86 (used to?) have)

Until we have a configfs overlay interface, then yeah, we have to hack
the DT.

That's not very much different than what you'd have to do if you
wanted some other bus exposed on those pins though.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com