From: Thor Thayer <tthayer@opensource.altera.com>
To: Dinh Nguyen <dinguyen@opensource.altera.com>,
bp@alien8.de, dougthompson@xmission.com, m.chehab@samsung.com,
robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
linux@arm.linux.org.uk, grant.likely@linaro.org
Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, tthayer.linux@gmail.com
Subject: Re: [PATCHv2 11/11] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry
Date: Tue, 8 Mar 2016 09:59:51 -0600 [thread overview]
Message-ID: <56DEF6F7.1030100@opensource.altera.com> (raw)
In-Reply-To: <56DEE6AE.100@opensource.altera.com>
Hi Dinh,
On 03/08/2016 08:50 AM, Dinh Nguyen wrote:
>
>
> On 03/07/2016 01:43 PM, tthayer@opensource.altera.com wrote:
>> From: Thor Thayer <tthayer@opensource.altera.com>
>>
>> Add the device tree entries needed to support the Altera L2
>> cache EDAC on the Arria10 chip.
>>
>> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
>> ---
>> v2 Match register value (l2-ecc@ffd06010)
>> ---
>> arch/arm/boot/dts/socfpga_arria10.dtsi | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
>> index cce9e50..44aeb3f 100644
>> --- a/arch/arm/boot/dts/socfpga_arria10.dtsi
>> +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
>> @@ -599,6 +599,20 @@
>> reg = <0xffe00000 0x40000>;
>> };
>>
>> + eccmgr: eccmgr@ffd06090 {
>> + compatible = "altr,socfpga-ecc-manager";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + l2-ecc@ffd06010 {
>> + compatible = "altr,socfpga-a10-l2-ecc";
>> + reg = <0xffd06010 0x4>;
>> + interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> + };
>> +
>
> Just checking if these addresses are correct. The eccmgr is at
> 0xffd06090, but the l2-ecc is at 0xffd06010? I would have thought from
> the placement the l2-ecc address would be inside the eccmgr's address?
>
> Dinh
>
Yes, this is confusing and I'll clarify/reorganize in the next series.
The eccmgr is pointing to the ECC IRQ mask bits. These registers and the
L2 ECC registers are organized in different areas within the system manager.
I'm actually redoing the series since the Arria10 IRQ handling is
significantly different.
Since this change will affect the bindings and dti (the eccmgr will have
the IRQs), please disregard this series.
Sorry for the noise.
Thor
prev parent reply other threads:[~2016-03-08 15:59 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-07 19:42 [PATCHv2 0/11] Series adding Altera Arria10 L2 Cache EDAC tthayer
2016-03-07 19:42 ` [PATCHv2 01/11] EDAC: Altera L2 Kconfig change from select to depends upon tthayer
2016-03-07 19:42 ` [PATCHv2 02/11] EDAC, altera: Move Device structs and defines to header file tthayer
2016-03-07 19:42 ` [PATCHv2 03/11] EDAC, altera: Add register offset for ECC Enable tthayer
2016-03-07 19:43 ` [PATCHv2 04/11] EDAC, altera: Add register offset for ECC Error Inject tthayer
2016-03-07 19:43 ` [PATCHv2 05/11] EDAC, altera: Add register offset for ECC Error Clear tthayer
2016-03-07 19:43 ` [PATCHv2 06/11] EDAC, altera: Add IRQ flags to private data struct tthayer
2016-03-07 19:43 ` [PATCHv2 07/11] EDAC, altera: Add status offset & masks tthayer
2016-03-08 15:52 ` Thor Thayer
2016-03-07 19:43 ` [PATCHv2 08/11] Documentation: dt: socfpga: Add Altera Arria10 L2 cache binding tthayer
2016-03-07 19:43 ` [PATCHv2 09/11] EDAC, altera: Addition of Arria10 L2 Cache ECC tthayer
2016-03-07 19:43 ` [PATCHv2 10/11] ARM: socfpga: Enable Arria10 L2 cache ECC on startup tthayer
2016-03-08 14:45 ` Dinh Nguyen
2016-03-07 19:43 ` [PATCHv2 11/11] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry tthayer
2016-03-08 14:50 ` Dinh Nguyen
2016-03-08 15:59 ` Thor Thayer [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=56DEF6F7.1030100@opensource.altera.com \
--to=tthayer@opensource.altera.com \
--cc=bp@alien8.de \
--cc=devicetree@vger.kernel.org \
--cc=dinguyen@opensource.altera.com \
--cc=dougthompson@xmission.com \
--cc=galak@codeaurora.org \
--cc=grant.likely@linaro.org \
--cc=ijc+devicetree@hellion.org.uk \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-edac@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux@arm.linux.org.uk \
--cc=m.chehab@samsung.com \
--cc=mark.rutland@arm.com \
--cc=pawel.moll@arm.com \
--cc=robh+dt@kernel.org \
--cc=tthayer.linux@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).