Re: [PATCH 1/2] regulator: DT: Add support to scale ramp delay based on platform behavior

[Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]

On Friday 01 April 2016 12:01 AM, Mark Brown wrote:
> * PGP Signed by an unknown key
>
> On Thu, Mar 31, 2016 at 11:17:38PM +0530, Laxman Dewangan wrote:
>
>> HW and chip team did simulation with tegra and PMIC and found that the board
>> needs more capacitance then what Vendor recommended for proper signal
>> conditioning on interface. So they put the difference capactitance value and
>> this causes deviation in ramp delay from advertised value. In out design, we
>> measured the ramp time as 50mv/us when PMIC is configured for 100mV/us.
>> So for all settling time, we need to use the ramp as 50mV/us.
>>  From DT, I will provide regulator-ramp-delay as 50mv/us.
>> But I do not have property for saying 100mv/us for PMIC configurations and
>> this is what makes need of 2nd property.
> So the PMIC actually has a setting for the rate you're seeing but for
> some resaon you can't use it?

PMIC has the different rate setting what I am seeing on platform (measured).
HW team measured the ramp dealy with specific configuration of rate 
setting on PMIC which is not default (OTP-One time programmed from Vendor).

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