From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF8E622081; Sun, 4 Aug 2024 10:05:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722765921; cv=none; b=GW/Z90b3IV+L0ZZ2QF8dWqIVGtlNDHZnthhkJfBahZqUL1fincBX1JFEiaOD1WvWIi9q5VRMHtQfcRWMdRl7u2CZNkbPmSIA6MI+z6aAW7gvBgI0bToZoU8i3q10YXXOBg0mgMZB/pOA4gPP9SxTw8IAuWQrrqcWI/mn0D6ah/I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722765921; c=relaxed/simple; bh=XpNZadBa+Hc21nJ++6QdZ0FyJoC5Vf/Xt4oXdAm3XBA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=u7PTCwpRRNyBFXEM7Fpn/YKYrwgoxiAw/dr+4BxYJEgXhUgDg+JmHSO3BEMtgSLNowhTBJqPq6fTq7lC71ZdDEOd4onTeMcAmxi6q2kvAIel/3XHdDEjwlavjHQYcSYmsCTC2Q/HGBHvbSgnXhQ7rdIweqvQ8wgDCAC8DCgndQQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kD0iuVr1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kD0iuVr1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E4369C32786; Sun, 4 Aug 2024 10:05:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722765921; bh=XpNZadBa+Hc21nJ++6QdZ0FyJoC5Vf/Xt4oXdAm3XBA=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=kD0iuVr1PB7f7MrUAJfbslLa8ku748yFNRQrUjm7cjwd1TKt8UovtjoAQUifw3jCc XBawr5jHqOz+UkXLvdz1a3BouEcpmAKUj9u61PMInhK513mdcN6x8Dby00mctON5ee G+6YORwZz0TGgC3M+j1ITrvNK25Gdwfih09liqqaKwEEhH02X+lLOnNrRmU3updiLT dH5FEtFZV4N4/cWoQV3m6SKaWRwNsiAEQH79j9A37xpl4WFd2xjiMYNdUeWMzjvC/I qPNQi1zKdNsycQKPAR4DBuqK4eQ/GjCabC8H9MGgRhrb+PPd+NbNcKJk1SgZZkfrqU 2rMz1u/54tnlA== Message-ID: <56bd1478-ce8c-4c1d-ab16-afe4ad462bf5@kernel.org> Date: Sun, 4 Aug 2024 12:05:11 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] arm64: dts: rockchip: Add base DT for rk3528 SoC To: Yao Zi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Greg Kroah-Hartman , Jiri Slaby , Chris Morgan , Jonas Karlman , Tim Lunn , Andy Yan , Muhammed Efe Cetin , Jagan Teki , Dragan Simic , Ondrej Jirman Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org References: <20240803125510.4699-2-ziyao@disroot.org> <20240803125510.4699-5-ziyao@disroot.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 03/08/2024 14:55, Yao Zi wrote: > This initial device tree describes CPU, interrupts and UART on the chip > and is able to boot into basic kernel with only UART. Cache information > is omitted for now as there is no precise documentation. Support for > other features will be added later. > > Signed-off-by: Yao Zi > --- > arch/arm64/boot/dts/rockchip/rk3528.dtsi | 182 +++++++++++++++++++++++ > 1 file changed, 182 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3528.dtsi > > diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi > new file mode 100644 > index 000000000000..77687d9e7e80 > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi > @@ -0,0 +1,182 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. > + * Copyright (c) 2024 Yao Zi > + */ > + > +#include > +#include > + > +/ { > + compatible = "rockchip,rk3528"; > + > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + serial2 = &uart2; > + serial3 = &uart3; > + serial4 = &uart4; > + serial5 = &uart5; > + serial6 = &uart6; > + serial7 = &uart7; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x0>; > + enable-method = "psci"; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x1>; > + enable-method = "psci"; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x2>; > + enable-method = "psci"; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x3>; > + enable-method = "psci"; > + }; > + }; > + > + psci { > + compatible = "arm,psci-1.0", "arm,psci-0.2"; > + method = "smc"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + ; > + }; > + > + xin24m: xin24m { Please use name for all fixed clocks which matches current format recommendation: 'clock-([0-9]+|[a-z0-9-]+)+' https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml?h=v6.11-rc1 > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <24000000>; > + clock-output-names = "xin24m"; > + }; > + > + gic: interrupt-controller@fed01000 { Why this all is outside of SoC? Best regards, Krzysztof