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([2a02:810d:15c0:828:49e6:bb8c:a05b:c4ed]) by smtp.gmail.com with ESMTPSA id a29-20020a509b5d000000b004fd204d180dsm1029128edj.64.2023.04.06.11.25.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Apr 2023 11:25:56 -0700 (PDT) Message-ID: <56e47e45-b3c0-4d32-923c-88023faef827@linaro.org> Date: Thu, 6 Apr 2023 20:25:54 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH v1 3/3] riscv: dts: starfive: add PCIe dts configuration for JH7110 Content-Language: en-US To: Minda Chen , Emil Renner Berthing , Conor Dooley , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-pci@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie References: <20230406111142.74410-1-minda.chen@starfivetech.com> <20230406111142.74410-4-minda.chen@starfivetech.com> From: Krzysztof Kozlowski In-Reply-To: <20230406111142.74410-4-minda.chen@starfivetech.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 06/04/2023 13:11, Minda Chen wrote: > The PCIe is a PCIe2, single lane PCIe compliant controller. > > Signed-off-by: Minda Chen > --- > .../jh7110-starfive-visionfive-2.dtsi | 58 ++++++++++++ > arch/riscv/boot/dts/starfive/jh7110.dtsi | 88 +++++++++++++++++++ > 2 files changed, 146 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index cf0a66faf5d3..4552919e69b0 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -191,6 +191,50 @@ > }; > }; > > + pcie0_wake_default: pcie0_wake_default { No underscores in node names. Test your patches against bindings before sending. > uart0_pins: uart0-0 { > tx-pins { > pinmux = @@ -228,3 +272,17 @@ > dr_mode = "peripheral"; > status = "okay"; > }; > + > +&pcie0 { > + pinctrl-names = "default"; > + reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; > + phys = <&pciephy0>; > + status = "okay"; > +}; > + > +&pcie1 { > + pinctrl-names = "default"; > + reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; > + phys = <&pciephy1>; > + status = "okay"; > +}; > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index 2f67196ffac0..c309ec550ba7 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -642,5 +642,93 @@ > #reset-cells = <1>; > power-domains = <&pwrc JH7110_PD_VOUT>; > }; > + > + pcie0: pcie@2B000000 { Lower case hex. > + compatible = "starfive,jh7110-pcie"; > + #address-cells = <3>; > + #size-cells = <2>; > + #interrupt-cells = <1>; Why reg is not second property? > + reg = <0x0 0x2B000000 0x0 0x1000000 > + 0x9 0x40000000 0x0 0x10000000>; > + reg-names = "reg", "config"; > + device_type = "pci"; > + starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>; > + bus-range = <0x0 0xff>; > + ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, > + <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; > + interrupts = <56>; Your binding requires cells, so I am pretty sure you did not test what you wrote. Best regards, Krzysztof