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[88.156.142.67]) by smtp.gmail.com with ESMTPSA id q23-20020ac246f7000000b004a27d2ea029sm128432lfo.172.2022.11.17.04.33.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 17 Nov 2022 04:33:31 -0800 (PST) Message-ID: <56e640fe-d3b7-31f1-2171-5040a7e043d2@linaro.org> Date: Thu, 17 Nov 2022 13:33:30 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v8 06/17] dt-bindings: mfd: amd,pensando-elbasr: Add AMD Pensando Elba System Resource chip Content-Language: en-US To: "Larson, Bradley" , Rob Herring , Brad Larson Cc: "adrian.hunter@intel.com" , "alcooperx@gmail.com" , "andy.shevchenko@gmail.com" , "arnd@arndb.de" , "brijeshkumar.singh@amd.com" , "broonie@kernel.org" , "catalin.marinas@arm.com" , "devicetree@vger.kernel.org" , "fancer.lancer@gmail.com" , "gerg@linux-m68k.org" , "gsomlo@gmail.com" , "krzk@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "lee.jones@linaro.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mmc@vger.kernel.org" , "p.yadav@ti.com" , "p.zabel@pengutronix.de" , "piotrs@cadence.com" , "rdunlap@infradead.org" , "samuel@sholland.org" , "Suthikulpanit, Suravee" , "Lendacky, Thomas" , "ulf.hansson@linaro.org" , "will@kernel.org" , "yamada.masahiro@socionext.com" References: <20221116193940.67445-1-blarson@amd.com> <20221116223045.GA1130586-robh@kernel.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 17/11/2022 01:41, Larson, Bradley wrote: > [AMD Official Use Only - General] > > From: Rob Herring > Sent: Wednesday, November 16, 2022 2:30 PM > >>> v8: >>> - Apply review request changes and picked the two unique examples >>> for the 4 chip-selects as one has the reset control support and >>> the other an interrupt. Missed the --in-reply-to in git >>> send-email for v7, included in this update. >> >> No, you haven't. By default in git, you don't have to do anything. See >> --thread and --no-chain-reply-to options. If you are messing with >> --in-reply-to, you are doing it wrong. >> >> Please resend the whole series properly threaded. > > Will resend the series > >>> diff --git a/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml b/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml >>> new file mode 100644 >>> index 000000000000..622c93402a86 >>> --- /dev/null >> +++ b/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml >>> @@ -0,0 +1,60 @@ > ... >>> + >>> +title: AMD Pensando Elba SoC Resource Controller >>> + >>> +description: | >>> + AMD Pensando Elba SoC Resource Controller functions are >>> + accessed with four chip-selects. Reset control is on CS0. >> >> One device with 4 chip-selects? Then I'd expect 'reg = <0 1 2 3>;' >> >> Hard to say more because I don't have the whole thread nor remember what >> exactly we discussed before. That was 100s of bindings ago... > > I agree and the example for v7 had all 4 chip-selects shown. This is not a pick and > choose device on what functions to use for a usable system. Krzysztof requested > only showing two chip-selects in the example. The problem is that you describe here SPI controller (and its chip selects) but binding is for the SPI device. The example is not the problem... > ... >>> +examples: >>> + - | >>> + #include >>> + >>> + spi { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + num-cs = <4>; Drop this property as well, unless it is necessary to explain "amd,pensando-elbasr" device. >>> + >>> + system-controller@0 { >>> + compatible = "amd,pensando-elbasr"; >>> + reg = <0>; >>> + spi-max-frequency = <12000000>; >>> + #reset-cells = <1>; >>> + }; Best regards, Krzysztof