From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Subject: Re: [PATCH v4 1/2] dt-bindings: pci: tegra: Update for per-lane PHYs Date: Mon, 11 Apr 2016 11:38:49 -0600 Message-ID: <570BE129.40907@wwwdotorg.org> References: <1460131994-24493-1-git-send-email-thierry.reding@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1460131994-24493-1-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Thierry Reding Cc: Bjorn Helgaas , Alexandre Courbot , linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org On 04/08/2016 10:13 AM, Thierry Reding wrote: > From: Thierry Reding > > Changes to the pad controller device tree binding have required that > each lane be associated with a separate PHY. Update the PCI host bridge > device tree binding to allow each root port to define the list of PHYs > required to drive the lanes associated with it. I think the feedback I gave on v3 still applies here (I'm talking about the comments on the patch, not the commit description). http://www.spinics.net/lists/linux-pci/msg49718.html