[PATCH v2 0/4] irqchip: lpc32xx: add LPC32xx irqchip driver

[PATCH v2 0/4] irqchip: lpc32xx: add LPC32xx irqchip driver

[Vladimir Zapolskiy]

The change replaces legacy NXP LPC32xx irqchip driver with a new one.

Legacy LPC32xx interrupt controller driver was broken since commit
76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler"), which
requires a private interrupt handler, otherwise any fired SIC1 generated
interrupt (mapped to MIC hwirq 0) breaks the kernel with the message
"unexpected IRQ trap at vector 00".

Summary of changes from v1 to v2:
* 2 of 10 from v1 changes are found in v4.6 and thus skipped from this
  series,
* removed all changes related to optional property 'wakeup-source',
  which will be needed later on to support interrupts as wakeup sources,
* removed introduced optional property 'interrupt-controller-name',
* moved DTS changes after new driver, new driver alone used with
  old DTS allows to boot LPC32xx boards,
* added a change which actually removes legacy driver,
* improvements in the driver based on a review findings from Marc.
* minor improvements all over the code.

v1 of the changeset can be found here:

   http://www.spinics.net/lists/devicetree/msg103231.html

Vladimir Zapolskiy (4):
  dt-bindings: interrupt-controllers: add description of SIC1 and SIC2
  irqchip: add LPC32xx interrupt controller driver
  arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC
  ARM: lpc32xx: remove legacy irq controller driver

 .../interrupt-controller/nxp,lpc3220-mic.txt       |  70 +--
 arch/arm/Kconfig                                   |   2 +
 arch/arm/boot/dts/lpc32xx.dtsi                     |  58 ++-
 arch/arm/mach-lpc32xx/Makefile                     |   2 +-
 arch/arm/mach-lpc32xx/irq.c                        | 477 ---------------------
 arch/arm/mach-lpc32xx/phy3250.c                    |   1 -
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-lpc32xx.c                      | 238 ++++++++++
 8 files changed, 329 insertions(+), 520 deletions(-)
 delete mode 100644 arch/arm/mach-lpc32xx/irq.c
 create mode 100644 drivers/irqchip/irq-lpc32xx.c

-- 
2.1.4

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[PATCH v2 1/4] dt-bindings: interrupt-controllers: add description of SIC1 and SIC2

[Vladimir Zapolskiy]

NXP LPC32xx has three interrupt controllers, namely root Main
Interrupt Controller (MIC) and two supplementary Sub Interrupt
Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2
are connected to MIC.

Signed-off-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
---
Changes from v1 to v2:
* removed introduced optional "interrupt-controller-name" property,
  for users the name of a controller will be constructed from mic/sic
  and controller physical address,
* removed introduced optional "wakeup-sources" property, a list of
  mappings between a hardware interrupt and its correspondent wakeup source
  to exit CPU STOP mode will be discussed later on,
* other negligible changes (rewording, small letters in unit address etc.)

 .../interrupt-controller/nxp,lpc3220-mic.txt       | 70 ++++++++++++++--------
 1 file changed, 46 insertions(+), 24 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt
index 539adca..38211f3 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt
@@ -1,38 +1,60 @@
-* NXP LPC32xx Main Interrupt Controller
-  (MIC, including SIC1 and SIC2 secondary controllers)
+* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers
 
 Required properties:
-- compatible: Should be "nxp,lpc3220-mic"
-- interrupt-controller: Identifies the node as an interrupt controller.
-- interrupt-parent: Empty for the interrupt controller itself
-- #interrupt-cells: The number of cells to define the interrupts. Should be 2.
-  The first cell is the IRQ number
-  The second cell is used to specify mode:
-      1 = low-to-high edge triggered
-      2 = high-to-low edge triggered
-      4 = active high level-sensitive
-      8 = active low level-sensitive
-      Default for internal sources should be set to 4 (active high).
-- reg: Should contain MIC registers location and length
+- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
+- reg: should contain IC registers location and length.
+- interrupt-controller: identifies the node as an interrupt controller.
+- #interrupt-cells: the number of cells to define an interrupt, should be 2.
+  The first cell is the IRQ number, the second cell is used to specify
+  one of the supported IRQ types:
+      IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
+      IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
+      IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
+      IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
+  Reset value is IRQ_TYPE_LEVEL_LOW.
+
+Optional properties:
+- interrupt-parent: empty for MIC interrupt controller, link to parent
+  MIC interrupt controller for SIC1 and SIC2
+- interrupts: empty for MIC interrupt controller, cascaded MIC
+  hardware interrupts for SIC1 and SIC2
 
 Examples:
-	/*
-	 * MIC
-	 */
+
+	/* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */
 	mic: interrupt-controller@40008000 {
 		compatible = "nxp,lpc3220-mic";
+		reg = <0x40008000 0x4000>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	sic1: interrupt-controller@4000c000 {
+		compatible = "nxp,lpc3220-sic";
+		reg = <0x4000c000 0x4000>;
 		interrupt-controller;
-		interrupt-parent;
 		#interrupt-cells = <2>;
-		reg = <0x40008000 0xC000>;
+
+		interrupt-parent = <&mic>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
+			     <30 IRQ_TYPE_LEVEL_LOW>;
 	};
 
-	/*
-	 * ADC
-	 */
+	sic2: interrupt-controller@40010000 {
+		compatible = "nxp,lpc3220-sic";
+		reg = <0x40010000 0x4000>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupt-parent = <&mic>;
+		interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
+			     <31 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	/* ADC */
 	adc@40048000 {
 		compatible = "nxp,lpc3220-adc";
 		reg = <0x40048000 0x1000>;
-		interrupt-parent = <&mic>;
-		interrupts = <39 4>;
+		interrupt-parent = <&sic1>;
+		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 	};
-- 
2.1.4

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Re: [PATCH v2 1/4] dt-bindings: interrupt-controllers: add description of SIC1 and SIC2

[Rob Herring]

On Mon, Apr 25, 2016 at 04:00:23AM +0300, Vladimir Zapolskiy wrote:
> NXP LPC32xx has three interrupt controllers, namely root Main
> Interrupt Controller (MIC) and two supplementary Sub Interrupt
> Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2
> are connected to MIC.
> 
> Signed-off-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
> ---
> Changes from v1 to v2:
> * removed introduced optional "interrupt-controller-name" property,
>   for users the name of a controller will be constructed from mic/sic
>   and controller physical address,
> * removed introduced optional "wakeup-sources" property, a list of
>   mappings between a hardware interrupt and its correspondent wakeup source
>   to exit CPU STOP mode will be discussed later on,
> * other negligible changes (rewording, small letters in unit address etc.)
> 
>  .../interrupt-controller/nxp,lpc3220-mic.txt       | 70 ++++++++++++++--------
>  1 file changed, 46 insertions(+), 24 deletions(-)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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Re: [PATCH v2 1/4] dt-bindings: interrupt-controllers: add description of SIC1 and SIC2

[Sylvain Lemieux]

On Mon, 2016-04-25 at 09:51 -0500, Rob Herring wrote:
> On Mon, Apr 25, 2016 at 04:00:23AM +0300, Vladimir Zapolskiy wrote:
> > NXP LPC32xx has three interrupt controllers, namely root Main
> > Interrupt Controller (MIC) and two supplementary Sub Interrupt
> > Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2
> > are connected to MIC.
> > 
> > Signed-off-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
> > ---
> > Changes from v1 to v2:
> > * removed introduced optional "interrupt-controller-name" property,
> >   for users the name of a controller will be constructed from mic/sic
> >   and controller physical address,
> > * removed introduced optional "wakeup-sources" property, a list of
> >   mappings between a hardware interrupt and its correspondent wakeup source
> >   to exit CPU STOP mode will be discussed later on,
> > * other negligible changes (rewording, small letters in unit address etc.)
> > 
> >  .../interrupt-controller/nxp,lpc3220-mic.txt       | 70 ++++++++++++++--------
> >  1 file changed, 46 insertions(+), 24 deletions(-)
> 
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

Acked-by: Sylvain Lemieux <slemieux.tyco-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

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[PATCH v2 3/4] arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC

[Vladimir Zapolskiy]

The change adds separate device nodes for SIC1 and SIC2 interrupt
controllers and reparents all defined SIC1 and SIC2 interrupt
producers to the correspondent interrupt controller, this is needed to
perform switching to a new LPC32xx MIC/SIC interrupt controller driver.

Signed-off-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
---
Changes from v1 to v2:
* squashed two step change in lpc32xx.dtsi - new irqchip driver can be
  used (i.e. board boots with access to userspace) with old DTS file,
  so there is no need to fix DTS firstly and then switch to a new driver,
* removed "interrupt-controller-name" and "wakeup-sources" properties
  from all interrupt controllers,
* removed outdated comment.

 arch/arm/boot/dts/lpc32xx.dtsi | 58 +++++++++++++++++++++++++++++-------------
 1 file changed, 41 insertions(+), 17 deletions(-)

diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 73c4746..4570ddc 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -92,7 +92,8 @@
 			ohci: ohci@0 {
 				compatible = "nxp,ohci-nxp", "usb-ohci";
 				reg = <0x0 0x300>;
-				interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
 				status = "disabled";
 			};
@@ -100,10 +101,11 @@
 			usbd: usbd@0 {
 				compatible = "nxp,lpc3220-udc";
 				reg = <0x0 0x300>;
-				interrupts = <61 IRQ_TYPE_LEVEL_HIGH>,
-					     <62 IRQ_TYPE_LEVEL_HIGH>,
-					     <60 IRQ_TYPE_LEVEL_HIGH>,
-					     <58 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-parent = <&sic1>;
+				interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
+					     <30 IRQ_TYPE_LEVEL_HIGH>,
+					     <28 IRQ_TYPE_LEVEL_HIGH>,
+					     <26 IRQ_TYPE_LEVEL_LOW>;
 				clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
 				status = "disabled";
 			};
@@ -111,7 +113,8 @@
 			i2cusb: i2c@300 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x300 0x100>;
-				interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -263,7 +266,8 @@
 			i2c1: i2c@400A0000 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x400A0000 0x100>;
-				interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-parent = <&sic1>;
+				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				pnx,timeout = <0x64>;
@@ -273,7 +277,8 @@
 			i2c2: i2c@400A8000 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x400A8000 0x100>;
-				interrupts = <50 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-parent = <&sic1>;
+				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				pnx,timeout = <0x64>;
@@ -314,12 +319,6 @@
 				};
 			};
 
-			/*
-			 * MIC Interrupt controller includes:
-			 *   MIC @40008000
-			 *   SIC1 @4000C000
-			 *   SIC2 @40010000
-			 */
 			mic: interrupt-controller@40008000 {
 				compatible = "nxp,lpc3220-mic";
 				interrupt-controller;
@@ -327,6 +326,28 @@
 				#interrupt-cells = <2>;
 			};
 
+			sic1: interrupt-controller@4000c000 {
+				compatible = "nxp,lpc3220-sic";
+				reg = <0x4000c000 0x4000>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				interrupt-parent = <&mic>;
+				interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
+					     <30 IRQ_TYPE_LEVEL_LOW>;
+				};
+
+			sic2: interrupt-controller@40010000 {
+				compatible = "nxp,lpc3220-sic";
+				reg = <0x40010000 0x4000>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				interrupt-parent = <&mic>;
+				interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
+					     <31 IRQ_TYPE_LEVEL_LOW>;
+			};
+
 			uart1: serial@40014000 {
 				compatible = "nxp,lpc3220-hsuart";
 				reg = <0x40014000 0x1000>;
@@ -351,7 +372,8 @@
 			rtc: rtc@40024000 {
 				compatible = "nxp,lpc3220-rtc";
 				reg = <0x40024000 0x1000>;
-				interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_RTC>;
 			};
 
@@ -404,7 +426,8 @@
 			adc: adc@40048000 {
 				compatible = "nxp,lpc3220-adc";
 				reg = <0x40048000 0x1000>;
-				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_ADC>;
 				status = "disabled";
 			};
@@ -412,7 +435,8 @@
 			tsc: tsc@40048000 {
 				compatible = "nxp,lpc3220-tsc";
 				reg = <0x40048000 0x1000>;
-				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_ADC>;
 				status = "disabled";
 			};
-- 
2.1.4

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Re: [PATCH v2 3/4] arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC

[Sylvain Lemieux]

Hi Vladimir,

On Mon, 2016-04-25 at 04:00 +0300, Vladimir Zapolskiy wrote:
> The change adds separate device nodes for SIC1 and SIC2 interrupt
> controllers and reparents all defined SIC1 and SIC2 interrupt
> producers to the correspondent interrupt controller, this is needed to
> perform switching to a new LPC32xx MIC/SIC interrupt controller driver.
> 
> Signed-off-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
> ---
> Changes from v1 to v2:
> * squashed two step change in lpc32xx.dtsi - new irqchip driver can be
>   used (i.e. board boots with access to userspace) with old DTS file,
>   so there is no need to fix DTS firstly and then switch to a new driver,
> * removed "interrupt-controller-name" and "wakeup-sources" properties
>   from all interrupt controllers,
> * removed outdated comment.
> 
>  arch/arm/boot/dts/lpc32xx.dtsi | 58 +++++++++++++++++++++++++++++-------------
>  1 file changed, 41 insertions(+), 17 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
> index 73c4746..4570ddc 100644
> --- a/arch/arm/boot/dts/lpc32xx.dtsi
> +++ b/arch/arm/boot/dts/lpc32xx.dtsi
> @@ -92,7 +92,8 @@

...
>  
> -			/*
> -			 * MIC Interrupt controller includes:
> -			 *   MIC @40008000
> -			 *   SIC1 @4000C000
> -			 *   SIC2 @40010000
> -			 */
>  			mic: interrupt-controller@40008000 {
>  				compatible = "nxp,lpc3220-mic";
>  				interrupt-controller;
> @@ -327,6 +326,28 @@

I think your are missing one change in your patch,
the mic register range should be 0x4000, not 0xC000.

Everything else is OK.

>  				#interrupt-cells = <2>;
>  			};
>  
> +			sic1: interrupt-controller@4000c000 {
> +				compatible = "nxp,lpc3220-sic";
> +				reg = <0x4000c000 0x4000>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +
> +				interrupt-parent = <&mic>;
> +				interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
> +					     <30 IRQ_TYPE_LEVEL_LOW>;
> +				};
> +
> +			sic2: interrupt-controller@40010000 {
> +				compatible = "nxp,lpc3220-sic";
> +				reg = <0x40010000 0x4000>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +
> +				interrupt-parent = <&mic>;
> +				interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
> +					     <31 IRQ_TYPE_LEVEL_LOW>;
> +			};
> +
...

Sylvain


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Re: [PATCH v2 3/4] arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC

[Vladimir Zapolskiy]

Hi Sylvain,

On 25.04.2016 19:05, Sylvain Lemieux wrote:
> Hi Vladimir,
> 
> On Mon, 2016-04-25 at 04:00 +0300, Vladimir Zapolskiy wrote:
>> The change adds separate device nodes for SIC1 and SIC2 interrupt
>> controllers and reparents all defined SIC1 and SIC2 interrupt
>> producers to the correspondent interrupt controller, this is needed to
>> perform switching to a new LPC32xx MIC/SIC interrupt controller driver.
>>
>> Signed-off-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
>> ---
>> Changes from v1 to v2:
>> * squashed two step change in lpc32xx.dtsi - new irqchip driver can be
>>   used (i.e. board boots with access to userspace) with old DTS file,
>>   so there is no need to fix DTS firstly and then switch to a new driver,
>> * removed "interrupt-controller-name" and "wakeup-sources" properties
>>   from all interrupt controllers,
>> * removed outdated comment.
>>
>>  arch/arm/boot/dts/lpc32xx.dtsi | 58 +++++++++++++++++++++++++++++-------------
>>  1 file changed, 41 insertions(+), 17 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
>> index 73c4746..4570ddc 100644
>> --- a/arch/arm/boot/dts/lpc32xx.dtsi
>> +++ b/arch/arm/boot/dts/lpc32xx.dtsi
>> @@ -92,7 +92,8 @@
> 
> ...
>>  
>> -			/*
>> -			 * MIC Interrupt controller includes:
>> -			 *   MIC @40008000
>> -			 *   SIC1 @4000C000
>> -			 *   SIC2 @40010000
>> -			 */
>>  			mic: interrupt-controller@40008000 {
>>  				compatible = "nxp,lpc3220-mic";
>>  				interrupt-controller;
>> @@ -327,6 +326,28 @@
> 
> I think your are missing one change in your patch,
> the mic register range should be 0x4000, not 0xC000.
> 
> Everything else is OK.

Good catch, thank you for pointing it out, and let me fix it
immediately. Fortunately it is corrected in an example from v2 1/4.

>>  				#interrupt-cells = <2>;
>>  			};
>>  
>> +			sic1: interrupt-controller@4000c000 {
>> +				compatible = "nxp,lpc3220-sic";
>> +				reg = <0x4000c000 0x4000>;
>> +				interrupt-controller;
>> +				#interrupt-cells = <2>;
>> +
>> +				interrupt-parent = <&mic>;
>> +				interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
>> +					     <30 IRQ_TYPE_LEVEL_LOW>;
>> +				};
>> +
>> +			sic2: interrupt-controller@40010000 {
>> +				compatible = "nxp,lpc3220-sic";
>> +				reg = <0x40010000 0x4000>;
>> +				interrupt-controller;
>> +				#interrupt-cells = <2>;
>> +
>> +				interrupt-parent = <&mic>;
>> +				interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
>> +					     <31 IRQ_TYPE_LEVEL_LOW>;
>> +			};
>> +
> ...
> 

--
With best wishes,
Vladimir
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[PATCH v3 3/4] arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC

[Vladimir Zapolskiy]

The change adds separate device nodes for SIC1 and SIC2 interrupt
controllers and reparents all defined SIC1 and SIC2 interrupt
producers to the correspondent interrupt controller, this is needed to
perform switching to a new LPC32xx MIC/SIC interrupt controller driver.

Signed-off-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
---
Changes from v2 to v3:
* fix io region size for MIC controller after moving SIC1/SIC2
  controllers out,
* move MIC 'reg' property up to follow 'compatible' property.

Changes from v1 to v2:
* squashed two step change in lpc32xx.dtsi - new irqchip driver can be
  used (i.e. board boots with access to userspace) with old DTS file,
  so there is no need to fix DTS firstly and then switch to a new driver,
* removed "interrupt-controller-name" and "wakeup-sources" properties
  from all interrupt controllers,
* removed outdated comment.

 arch/arm/boot/dts/lpc32xx.dtsi | 60 +++++++++++++++++++++++++++++-------------
 1 file changed, 42 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 73c4746..e295e1e 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -92,7 +92,8 @@
 			ohci: ohci@0 {
 				compatible = "nxp,ohci-nxp", "usb-ohci";
 				reg = <0x0 0x300>;
-				interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
 				status = "disabled";
 			};
@@ -100,10 +101,11 @@
 			usbd: usbd@0 {
 				compatible = "nxp,lpc3220-udc";
 				reg = <0x0 0x300>;
-				interrupts = <61 IRQ_TYPE_LEVEL_HIGH>,
-					     <62 IRQ_TYPE_LEVEL_HIGH>,
-					     <60 IRQ_TYPE_LEVEL_HIGH>,
-					     <58 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-parent = <&sic1>;
+				interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
+					     <30 IRQ_TYPE_LEVEL_HIGH>,
+					     <28 IRQ_TYPE_LEVEL_HIGH>,
+					     <26 IRQ_TYPE_LEVEL_LOW>;
 				clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
 				status = "disabled";
 			};
@@ -111,7 +113,8 @@
 			i2cusb: i2c@300 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x300 0x100>;
-				interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -263,7 +266,8 @@
 			i2c1: i2c@400A0000 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x400A0000 0x100>;
-				interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-parent = <&sic1>;
+				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				pnx,timeout = <0x64>;
@@ -273,7 +277,8 @@
 			i2c2: i2c@400A8000 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x400A8000 0x100>;
-				interrupts = <50 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-parent = <&sic1>;
+				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				pnx,timeout = <0x64>;
@@ -314,19 +319,35 @@
 				};
 			};
 
-			/*
-			 * MIC Interrupt controller includes:
-			 *   MIC @40008000
-			 *   SIC1 @4000C000
-			 *   SIC2 @40010000
-			 */
 			mic: interrupt-controller@40008000 {
 				compatible = "nxp,lpc3220-mic";
+				reg = <0x40008000 0x4000>;
 				interrupt-controller;
-				reg = <0x40008000 0xC000>;
 				#interrupt-cells = <2>;
 			};
 
+			sic1: interrupt-controller@4000c000 {
+				compatible = "nxp,lpc3220-sic";
+				reg = <0x4000c000 0x4000>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				interrupt-parent = <&mic>;
+				interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
+					     <30 IRQ_TYPE_LEVEL_LOW>;
+				};
+
+			sic2: interrupt-controller@40010000 {
+				compatible = "nxp,lpc3220-sic";
+				reg = <0x40010000 0x4000>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				interrupt-parent = <&mic>;
+				interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
+					     <31 IRQ_TYPE_LEVEL_LOW>;
+			};
+
 			uart1: serial@40014000 {
 				compatible = "nxp,lpc3220-hsuart";
 				reg = <0x40014000 0x1000>;
@@ -351,7 +372,8 @@
 			rtc: rtc@40024000 {
 				compatible = "nxp,lpc3220-rtc";
 				reg = <0x40024000 0x1000>;
-				interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_RTC>;
 			};
 
@@ -404,7 +426,8 @@
 			adc: adc@40048000 {
 				compatible = "nxp,lpc3220-adc";
 				reg = <0x40048000 0x1000>;
-				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_ADC>;
 				status = "disabled";
 			};
@@ -412,7 +435,8 @@
 			tsc: tsc@40048000 {
 				compatible = "nxp,lpc3220-tsc";
 				reg = <0x40048000 0x1000>;
-				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_ADC>;
 				status = "disabled";
 			};
-- 
2.1.4

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Re: [PATCH v3 3/4] arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC

[Sylvain Lemieux]

Hi Vladimir,

On Tue, 2016-04-26 at 00:02 +0300, Vladimir Zapolskiy wrote:
> The change adds separate device nodes for SIC1 and SIC2 interrupt
> controllers and reparents all defined SIC1 and SIC2 interrupt
> producers to the correspondent interrupt controller, this is needed to
> perform switching to a new LPC32xx MIC/SIC interrupt controller driver.
> 
> Signed-off-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
> ---
> Changes from v2 to v3:
> * fix io region size for MIC controller after moving SIC1/SIC2
>   controllers out,
> * move MIC 'reg' property up to follow 'compatible' property.
> 
> Changes from v1 to v2:
> * squashed two step change in lpc32xx.dtsi - new irqchip driver can be
>   used (i.e. board boots with access to userspace) with old DTS file,
>   so there is no need to fix DTS firstly and then switch to a new driver,
> * removed "interrupt-controller-name" and "wakeup-sources" properties
>   from all interrupt controllers,
> * removed outdated comment.
> 
>  arch/arm/boot/dts/lpc32xx.dtsi | 60 +++++++++++++++++++++++++++++-------------
>  1 file changed, 42 insertions(+), 18 deletions(-)
> 
Please use capital letter for the word ARM in the patch title.

Acked-by: Sylvain Lemieux <slemieux.tyco-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>





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Re: [PATCH v3 3/4] arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC

[Vladimir Zapolskiy]

Hi Sylvain,

On 26.04.2016 15:26, Sylvain Lemieux wrote:
> Hi Vladimir,
> 
> On Tue, 2016-04-26 at 00:02 +0300, Vladimir Zapolskiy wrote:
>> The change adds separate device nodes for SIC1 and SIC2 interrupt
>> controllers and reparents all defined SIC1 and SIC2 interrupt
>> producers to the correspondent interrupt controller, this is needed to
>> perform switching to a new LPC32xx MIC/SIC interrupt controller driver.
>>
>> Signed-off-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
>> ---
>> Changes from v2 to v3:
>> * fix io region size for MIC controller after moving SIC1/SIC2
>>   controllers out,
>> * move MIC 'reg' property up to follow 'compatible' property.
>>
>> Changes from v1 to v2:
>> * squashed two step change in lpc32xx.dtsi - new irqchip driver can be
>>   used (i.e. board boots with access to userspace) with old DTS file,
>>   so there is no need to fix DTS firstly and then switch to a new driver,
>> * removed "interrupt-controller-name" and "wakeup-sources" properties
>>   from all interrupt controllers,
>> * removed outdated comment.
>>
>>  arch/arm/boot/dts/lpc32xx.dtsi | 60 +++++++++++++++++++++++++++++-------------
>>  1 file changed, 42 insertions(+), 18 deletions(-)
>>
> Please use capital letter for the word ARM in the patch title.

right, I'll change it on application, thank you for review.

> Acked-by: Sylvain Lemieux <slemieux.tyco-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> 

--
With best wishes,
Vladimir
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