* [PATCH 01/18] dmaengine: st_fdma: Add STMicroelectronics FDMA DT binding documentation
2016-04-21 11:04 [PATCH 00/18] Add support for FDMA DMA controller found on STi chipsets Peter Griffin
@ 2016-04-21 11:04 ` Peter Griffin
[not found] ` <1461236675-10176-2-git-send-email-peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2016-04-21 11:04 ` [PATCH 02/18] dmaengine: st_fdma: Add STMicroelectronics FDMA driver header file Peter Griffin
` (16 subsequent siblings)
17 siblings, 1 reply; 53+ messages in thread
From: Peter Griffin @ 2016-04-21 11:04 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, srinivas.kandagatla,
maxime.coquelin, patrice.chotard, vinod.koul
Cc: peter.griffin, lee.jones, dmaengine, devicetree, arnd, broonie,
ludovic.barre
This patch adds the DT binding documentation for the FDMA constroller
found on STi based chipsets from STMicroelectronics.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
Documentation/devicetree/bindings/dma/st_fdma.txt | 87 +++++++++++++++++++++++
1 file changed, 87 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/st_fdma.txt
diff --git a/Documentation/devicetree/bindings/dma/st_fdma.txt b/Documentation/devicetree/bindings/dma/st_fdma.txt
new file mode 100644
index 0000000..13029dc
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/st_fdma.txt
@@ -0,0 +1,87 @@
+* STMicroelectronics Flexible Direct Memory Access Device Tree bindings
+
+The FDMA is a general-purpose direct memory access controller capable of
+supporting 16 independent DMA channels. It accepts up to 32 DMA requests.
+The FDMA is based on a Slim processor which require a firmware.
+
+* FDMA Controller
+
+Required properties:
+- compatible : Should be one of
+ - st,stih407-fdma-mpe31-11
+ - st,stih407-fdma-mpe31-12
+ - st,stih407-fdma-mpe31-13
+- reg : Should contain DMA registers location and length
+- interrupts : Should contain one interrupt shared by all channels
+- dma-channels : Number of channels supported by the controller
+- #dma-cells : Must be <3>. See DMA client section below
+- clocks : Must contain an entry for each name in clock-names
+- clock-names : Must contain "fdma_slim, fdma_hi, fdma_low, fdma_ic" entries
+See: Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+
+Example:
+
+ fdma1-app: dma-controller@8e40000 {
+ compatible = "st,stih407-fdma-mpe31-11";
+ reg = <0x8e40000 0x20000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>;
+ dma-channels = <16>;
+ #dma-cells = <3>;
+ clocks = <&CLK_S_C0_FLEXGEN CLK_FDMA>,
+ <&CLK_S_C0_FLEXGEN CLK_TX_ICN_DMU>,
+ <&CLK_S_C0_FLEXGEN CLK_TX_ICN_DMU>,
+ <&CLK_S_C0_FLEXGEN CLK_EXT2F_A9>;
+ clock-names = "fdma_slim",
+ "fdma_hi",
+ "fdma_low",
+ "fdma_ic";
+ };
+
+* DMA client
+
+Required properties:
+- dmas: Comma separated list of dma channel requests
+- dma-names: Names of the aforementioned requested channels
+
+Each dmas request consists of 4 cells:
+1. A phandle pointing to the FDMA controller
+2. The request line number
+3. A 32bit mask specifying (see include/linux/platform_data/dma-st-fdma.h)
+ -bit 2-0: Holdoff value, dreq will be masked for
+ 0x0: 0-0.5us
+ 0x1: 0.5-1us
+ 0x2: 1-1.5us
+ -bit 17: data swap
+ 0x0: disabled
+ 0x1: enabled
+ -bit 21: Increment Address
+ 0x0: no address increment between transfers
+ 0x1: increment address between transfers
+ -bit 22: 2 STBus Initiator Coprocessor interface
+ 0x0: high priority port
+ 0x1: low priority port
+4. transfers type
+ 0 free running
+ 1 paced
+
+Example:
+
+ sti_uni_player2: sti-uni-player@2 {
+ compatible = "st,sti-uni-player";
+ status = "disabled";
+ #sound-dai-cells = <0>;
+ st,syscfg = <&syscfg_core>;
+ clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
+ assigned-clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
+ assigned-clock-parents = <&clk_s_d0_quadfs 2>;
+ assigned-clock-rates = <50000000>;
+ reg = <0x8D82000 0x158>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
+ dmas = <&fdma0 4 0 1>;
+ dai-name = "Uni Player #1 (DAC)";
+ dma-names = "tx";
+ st,uniperiph-id = <2>;
+ st,version = <5>;
+ st,mode = "PCM";
+ };
--
1.9.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 02/18] dmaengine: st_fdma: Add STMicroelectronics FDMA driver header file
2016-04-21 11:04 [PATCH 00/18] Add support for FDMA DMA controller found on STi chipsets Peter Griffin
2016-04-21 11:04 ` [PATCH 01/18] dmaengine: st_fdma: Add STMicroelectronics FDMA DT binding documentation Peter Griffin
@ 2016-04-21 11:04 ` Peter Griffin
[not found] ` <1461236675-10176-3-git-send-email-peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2016-04-21 11:04 ` [PATCH 03/18] dmaengine: st_fdma: Add STMicroelectronics FDMA engine driver support Peter Griffin
` (15 subsequent siblings)
17 siblings, 1 reply; 53+ messages in thread
From: Peter Griffin @ 2016-04-21 11:04 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, srinivas.kandagatla,
maxime.coquelin, patrice.chotard, vinod.koul
Cc: peter.griffin, lee.jones, dmaengine, devicetree, arnd, broonie,
ludovic.barre
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/dma/st_fdma.h | 281 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 281 insertions(+)
create mode 100644 drivers/dma/st_fdma.h
diff --git a/drivers/dma/st_fdma.h b/drivers/dma/st_fdma.h
new file mode 100644
index 0000000..746aee0
--- /dev/null
+++ b/drivers/dma/st_fdma.h
@@ -0,0 +1,281 @@
+/*
+ * st_fdma.h
+ *
+ * Copyright (C) 2014 STMicroelectronics
+ * Author: Ludovic Barre <Ludovic.barre@st.com>
+ * License terms: GNU General Public License (GPL), version 2
+ */
+#ifndef __DMA_ST_FDMA_H
+#define __DMA_ST_FDMA_H
+
+#include <linux/dmaengine.h>
+#include <linux/interrupt.h>
+
+#include "virt-dma.h"
+
+#define ST_FDMA_NR_DREQS 32
+#define EM_SLIM 102 /* No official SLIM ELF ID */
+#define FW_NAME_SIZE 30
+
+enum {
+ CLK_SLIM,
+ CLK_HI,
+ CLK_LOW,
+ CLK_IC,
+ CLK_MAX_NUM,
+};
+
+#define NAME_SZ 10
+
+struct st_fdma_ram {
+ char name[NAME_SZ];
+ u32 offset;
+ u32 size;
+};
+
+/**
+ * struct st_fdma_generic_node - Free running/paced generic node
+ *
+ * @length: Length in bytes of a line in a 2D mem to mem
+ * @sstride: Stride, in bytes, between source lines in a 2D data move
+ * @dstride: Stride, in bytes, between destination lines in a 2D data move
+ */
+struct st_fdma_generic_node {
+ u32 length;
+ u32 sstride;
+ u32 dstride;
+};
+
+/**
+ * struct st_fdma_hw_node - Node structure used by fdma hw
+ *
+ * @next: Pointer to next node
+ * @control: Transfer Control Parameters
+ * @nbytes: Number of Bytes to read
+ * @saddr: Source address
+ * @daddr: Destination address
+ *
+ * @generic: generic node for free running/paced transfert type
+ * 2 others transfert type are possible, but not yet implemented
+ *
+ * The NODE structures must be aligned to a 32 byte boundary
+ */
+struct st_fdma_hw_node {
+ u32 next;
+ u32 control;
+ u32 nbytes;
+ u32 saddr;
+ u32 daddr;
+ union {
+ struct st_fdma_generic_node generic;
+ };
+} __aligned(32);
+
+/*
+ * node control parameters
+ */
+#define NODE_CTRL_REQ_MAP_MASK GENMASK(4, 0)
+#define NODE_CTRL_REQ_MAP_FREE_RUN 0x0
+#define NODE_CTRL_REQ_MAP_DREQ(n) ((n) & NODE_CTRL_REQ_MAP_MASK)
+#define NODE_CTRL_REQ_MAP_EXT NODE_CTRL_REQ_MAP_MASK
+#define NODE_CTRL_SRC_MASK GENMASK(6, 5)
+#define NODE_CTRL_SRC_STATIC BIT(5)
+#define NODE_CTRL_SRC_INCR BIT(6)
+#define NODE_CTRL_DST_MASK GENMASK(8, 7)
+#define NODE_CTRL_DST_STATIC BIT(7)
+#define NODE_CTRL_DST_INCR BIT(8)
+#define NODE_CTRL_SECURE BIT(15)
+#define NODE_CTRL_PAUSE_EON BIT(30)
+#define NODE_CTRL_INT_EON BIT(31)
+
+/**
+ * struct st_fdma_sw_node - descriptor structure for link list
+ *
+ * @pdesc: Physical address of desc
+ * @node: link used for putting this into a channel queue
+ */
+struct st_fdma_sw_node {
+ dma_addr_t pdesc;
+ struct st_fdma_hw_node *desc;
+};
+
+struct st_fdma_driverdata {
+ const struct st_fdma_ram *fdma_mem;
+ u32 num_mem;
+ u32 id;
+ char name[NAME_SZ];
+};
+
+struct st_fdma_desc {
+ struct virt_dma_desc vdesc;
+ struct st_fdma_chan *fchan;
+ bool iscyclic;
+ unsigned int n_nodes;
+ struct st_fdma_sw_node node[];
+};
+
+enum st_fdma_type {
+ ST_FDMA_TYPE_FREE_RUN,
+ ST_FDMA_TYPE_PACED,
+};
+
+struct st_fdma_cfg {
+ struct device_node *of_node;
+ enum st_fdma_type type;
+ dma_addr_t dev_addr;
+ enum dma_transfer_direction dir;
+ int req_line; /* request line */
+ long req_ctrl; /* Request control */
+};
+
+struct st_fdma_chan {
+ struct st_fdma_dev *fdev;
+ struct dma_pool *node_pool;
+ struct dma_slave_config scfg;
+ struct st_fdma_cfg cfg;
+
+ int dreq_line;
+
+ struct virt_dma_chan vchan;
+ struct st_fdma_desc *fdesc;
+ enum dma_status status;
+};
+
+struct st_fdma_dev {
+ struct device *dev;
+ const struct st_fdma_driverdata *drvdata;
+ struct dma_device dma_device;
+
+ void __iomem *io_base;
+ struct resource *io_res;
+ struct clk *clks[CLK_MAX_NUM];
+
+ struct st_fdma_chan *chans;
+
+ spinlock_t dreq_lock;
+ unsigned long dreq_mask;
+
+ u32 nr_channels;
+ char fw_name[FW_NAME_SIZE];
+
+ atomic_t fw_loaded;
+};
+
+/* Registers*/
+/* FDMA interface */
+#define FDMA_ID_OFST 0x00000
+#define FDMA_VER_OFST 0x00004
+
+#define FDMA_EN_OFST 0x00008
+#define FDMA_EN_RUN BIT(0)
+
+#define FDMA_CLK_GATE_OFST 0x0000C
+#define FDMA_CLK_GATE_DIS BIT(0)
+#define FDMA_CLK_GATE_RESET BIT(2)
+
+#define FDMA_SLIM_PC_OFST 0x00020
+
+#define FDMA_REV_ID_OFST 0x10000
+#define FDMA_REV_ID_MIN_MASK GENMASK(15, 8)
+#define FDMA_REV_ID_MIN(id) ((id & FDMA_REV_ID_MIN_MASK) >> 8)
+#define FDMA_REV_ID_MAJ_MASK GENMASK(23, 16)
+#define FDMA_REV_ID_MAJ(id) ((id & FDMA_REV_ID_MAJ_MASK) >> 16)
+
+#define FDMA_STBUS_SYNC_OFST 0x17F88
+#define FDMA_STBUS_SYNC_DIS BIT(0)
+
+#define FDMA_CMD_STA_OFST 0x17FC0
+#define FDMA_CMD_SET_OFST 0x17FC4
+#define FDMA_CMD_CLR_OFST 0x17FC8
+#define FDMA_CMD_MASK_OFST 0x17FCC
+#define FDMA_CMD_START(ch) (0x1 << (ch << 1))
+#define FDMA_CMD_PAUSE(ch) (0x2 << (ch << 1))
+#define FDMA_CMD_FLUSH(ch) (0x3 << (ch << 1))
+
+#define FDMA_INT_STA_OFST 0x17FD0
+#define FDMA_INT_STA_CH 0x1
+#define FDMA_INT_STA_ERR 0x2
+
+#define FDMA_INT_SET_OFST 0x17FD4
+#define FDMA_INT_CLR_OFST 0x17FD8
+#define FDMA_INT_MASK_OFST 0x17FDC
+
+#define fdma_read(fdev, name) \
+ readl_relaxed((fdev)->io_base + FDMA_##name##_OFST)
+
+#define fdma_write(fdev, val, name) \
+ writel_relaxed((val), (fdev)->io_base + FDMA_##name##_OFST)
+
+/* fchan interface */
+#define FDMA_CH_CMD_OFST 0x10200
+#define FDMA_CH_CMD_STA_MASK GENMASK(1, 0)
+#define FDMA_CH_CMD_STA_IDLE (0x0)
+#define FDMA_CH_CMD_STA_START (0x1)
+#define FDMA_CH_CMD_STA_RUNNING (0x2)
+#define FDMA_CH_CMD_STA_PAUSED (0x3)
+#define FDMA_CH_CMD_ERR_MASK GENMASK(4, 2)
+#define FDMA_CH_CMD_ERR_INT (0x0 << 2)
+#define FDMA_CH_CMD_ERR_NAND (0x1 << 2)
+#define FDMA_CH_CMD_ERR_MCHI (0x2 << 2)
+#define FDMA_CH_CMD_DATA_MASK GENMASK(31, 5)
+#define fchan_read(fchan, name) \
+ readl_relaxed((fchan)->fdev->io_base \
+ + (fchan)->vchan.chan.chan_id * 0x4 \
+ + FDMA_##name##_OFST)
+
+#define fchan_write(fchan, val, name) \
+ writel_relaxed((val), (fchan)->fdev->io_base \
+ + (fchan)->vchan.chan.chan_id * 0x4 \
+ + FDMA_##name##_OFST)
+
+/* req interface */
+#define FDMA_REQ_CTRL_OFST 0x10240
+#define dreq_write(fchan, val, name) \
+ writel_relaxed((val), (fchan)->fdev->io_base \
+ + fchan->dreq_line * 0x04 \
+ + FDMA_##name##_OFST)
+/* node interface */
+#define FDMA_NODE_SZ 128
+#define FDMA_PTRN_OFST 0x10800
+#define FDMA_CNTN_OFST 0x10808
+#define FDMA_SADDRN_OFST 0x1080c
+#define FDMA_DADDRN_OFST 0x10810
+#define fnode_read(fchan, name) \
+ readl_relaxed((fchan)->fdev->io_base \
+ + (fchan)->vchan.chan.chan_id * FDMA_NODE_SZ \
+ + FDMA_##name##_OFST)
+
+#define fnode_write(fchan, val, name) \
+ writel_relaxed((val), (fchan)->fdev->io_base \
+ + (fchan)->vchan.chan.chan_id * FDMA_NODE_SZ \
+ + FDMA_##name##_OFST)
+
+/*
+ * request control bits
+ */
+#define REQ_CTRL_NUM_OPS_MASK GENMASK(31, 24)
+#define REQ_CTRL_NUM_OPS(n) (REQ_CTRL_NUM_OPS_MASK & ((n) << 24))
+#define REQ_CTRL_INITIATOR_MASK BIT(22)
+#define REQ_CTRL_INIT0 (0x0 << 22)
+#define REQ_CTRL_INIT1 (0x1 << 22)
+#define REQ_CTRL_INC_ADDR_ON BIT(21)
+#define REQ_CTRL_DATA_SWAP_ON BIT(17)
+#define REQ_CTRL_WNR BIT(14)
+#define REQ_CTRL_OPCODE_MASK GENMASK(7, 4)
+#define REQ_CTRL_OPCODE_LD_ST1 (0x0 << 4)
+#define REQ_CTRL_OPCODE_LD_ST2 (0x1 << 4)
+#define REQ_CTRL_OPCODE_LD_ST4 (0x2 << 4)
+#define REQ_CTRL_OPCODE_LD_ST8 (0x3 << 4)
+#define REQ_CTRL_OPCODE_LD_ST16 (0x4 << 4)
+#define REQ_CTRL_OPCODE_LD_ST32 (0x5 << 4)
+#define REQ_CTRL_OPCODE_LD_ST64 (0x6 << 4)
+#define REQ_CTRL_HOLDOFF_MASK GENMASK(2, 0)
+#define REQ_CTRL_HOLDOFF(n) ((n) & REQ_CTRL_HOLDOFF_MASK)
+
+/* bits used by client to configure request control */
+#define REQ_CTRL_CFG_MASK (REQ_CTRL_HOLDOFF_MASK | REQ_CTRL_DATA_SWAP_ON \
+ | REQ_CTRL_INC_ADDR_ON | REQ_CTRL_INITIATOR_MASK)
+
+bool st_fdma_filter_fn(struct dma_chan *chan, void *param);
+
+#endif /* __DMA_ST_FDMA_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 03/18] dmaengine: st_fdma: Add STMicroelectronics FDMA engine driver support
2016-04-21 11:04 [PATCH 00/18] Add support for FDMA DMA controller found on STi chipsets Peter Griffin
2016-04-21 11:04 ` [PATCH 01/18] dmaengine: st_fdma: Add STMicroelectronics FDMA DT binding documentation Peter Griffin
2016-04-21 11:04 ` [PATCH 02/18] dmaengine: st_fdma: Add STMicroelectronics FDMA driver header file Peter Griffin
@ 2016-04-21 11:04 ` Peter Griffin
2016-04-21 11:24 ` Arnd Bergmann
` (2 more replies)
2016-04-21 11:04 ` [PATCH 04/18] dmaengine: st_fdma: Add xp70 firmware loading mechanism Peter Griffin
` (14 subsequent siblings)
17 siblings, 3 replies; 53+ messages in thread
From: Peter Griffin @ 2016-04-21 11:04 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, srinivas.kandagatla,
maxime.coquelin, patrice.chotard, vinod.koul
Cc: devicetree, arnd, peter.griffin, broonie, dmaengine, lee.jones,
ludovic.barre
This patch adds support for the Flexible Direct Memory Access (FDMA) core
driver. The FDMA is a slim core CPU with a dedicated firmware.
It is a general purpose DMA controller capable of supporting 16
independent DMA channels. Data moves maybe from memory to memory
or between memory and paced latency critical real time targets and it
is found on al STi based chipsets.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/dma/Kconfig | 12 +
drivers/dma/Makefile | 1 +
drivers/dma/st_fdma.c | 967 ++++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 980 insertions(+)
create mode 100644 drivers/dma/st_fdma.c
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index d96d87c..5910c4f 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -527,6 +527,18 @@ config ZX_DMA
help
Support the DMA engine for ZTE ZX296702 platform devices.
+config ST_FDMA
+ tristate "ST FDMA dmaengine support"
+ depends on ARCH_STI
+ select DMA_ENGINE
+ select FW_LOADER
+ select DMA_VIRTUAL_CHANNELS
+ help
+ Enable support for ST FDMA controller.
+ It supports 16 independent DMA channels, accepts up to 32 DMA requests
+
+ Say Y here if you have such a chipset.
+ If unsure, say N.
# driver files
source "drivers/dma/bestcomm/Kconfig"
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 6084127..b81ca99 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -65,6 +65,7 @@ obj-$(CONFIG_TI_DMA_CROSSBAR) += ti-dma-crossbar.o
obj-$(CONFIG_TI_EDMA) += edma.o
obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
obj-$(CONFIG_ZX_DMA) += zx296702_dma.o
+obj-$(CONFIG_ST_FDMA) += st_fdma.o
obj-y += qcom/
obj-y += xilinx/
diff --git a/drivers/dma/st_fdma.c b/drivers/dma/st_fdma.c
new file mode 100644
index 0000000..9bf0100
--- /dev/null
+++ b/drivers/dma/st_fdma.c
@@ -0,0 +1,967 @@
+/*
+ * st_fdma.c
+ *
+ * Copyright (C) 2014 STMicroelectronics
+ * Author: Ludovic Barre <Ludovic.barre@st.com>
+ * License terms: GNU General Public License (GPL), version 2
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/dmaengine.h>
+#include <linux/dmapool.h>
+#include <linux/firmware.h>
+#include <linux/elf.h>
+#include <linux/atomic.h>
+
+#include "st_fdma.h"
+#include "dmaengine.h"
+#include "virt-dma.h"
+
+static char *fdma_clk_name[CLK_MAX_NUM] = {
+ [CLK_SLIM] = "fdma_slim",
+ [CLK_HI] = "fdma_hi",
+ [CLK_LOW] = "fdma_low",
+ [CLK_IC] = "fdma_ic",
+};
+
+static int st_fdma_clk_get(struct st_fdma_dev *fdev)
+{
+ int i;
+
+ for (i = 0; i < CLK_MAX_NUM; i++) {
+ fdev->clks[i] = devm_clk_get(fdev->dev, fdma_clk_name[i]);
+ if (IS_ERR(fdev->clks[i])) {
+ dev_err(fdev->dev,
+ "failed to get clock: %s\n", fdma_clk_name[i]);
+ return PTR_ERR(fdev->clks[i]);
+ }
+ }
+
+ if (i != CLK_MAX_NUM) {
+ dev_err(fdev->dev, "all clocks are not defined\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int st_fdma_clk_enable(struct st_fdma_dev *fdev)
+{
+ int i, ret;
+
+ for (i = 0; i < CLK_MAX_NUM; i++) {
+ ret = clk_prepare_enable(fdev->clks[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static void st_fdma_clk_disable(struct st_fdma_dev *fdev)
+{
+ int i;
+
+ for (i = 0; i < CLK_MAX_NUM; i++)
+ clk_disable_unprepare(fdev->clks[i]);
+}
+
+static inline struct st_fdma_chan *to_st_fdma_chan(struct dma_chan *c)
+{
+ return container_of(c, struct st_fdma_chan, vchan.chan);
+}
+
+static struct st_fdma_desc *to_st_fdma_desc(struct virt_dma_desc *vd)
+{
+ return container_of(vd, struct st_fdma_desc, vdesc);
+}
+
+static void st_fdma_enable(struct st_fdma_dev *fdev)
+{
+ unsigned long hw_id, hw_ver, fw_rev;
+ u32 val;
+
+ /* disable CPU pipeline clock & reset cpu pipeline */
+ val = FDMA_CLK_GATE_DIS | FDMA_CLK_GATE_RESET;
+ fdma_write(fdev, val, CLK_GATE);
+ /* disable SLIM core STBus sync */
+ fdma_write(fdev, FDMA_STBUS_SYNC_DIS, STBUS_SYNC);
+ /* enable cpu pipeline clock */
+ fdma_write(fdev, !FDMA_CLK_GATE_DIS, CLK_GATE);
+ /* clear int & cmd mailbox */
+ fdma_write(fdev, ~0UL, INT_CLR);
+ fdma_write(fdev, ~0UL, CMD_CLR);
+ /* enable all channels cmd & int */
+ fdma_write(fdev, ~0UL, INT_MASK);
+ fdma_write(fdev, ~0UL, CMD_MASK);
+ /* enable cpu */
+ writel(FDMA_EN_RUN, fdev->io_base + FDMA_EN_OFST);
+
+ hw_id = fdma_read(fdev, ID);
+ hw_ver = fdma_read(fdev, VER);
+ fw_rev = fdma_read(fdev, REV_ID);
+
+ dev_info(fdev->dev, "fw rev:%ld.%ld on SLIM %ld.%ld\n",
+ FDMA_REV_ID_MAJ(fw_rev), FDMA_REV_ID_MIN(fw_rev),
+ hw_id, hw_ver);
+}
+
+static int st_fdma_disable(struct st_fdma_dev *fdev)
+{
+ /* mask all (cmd & int) channels */
+ fdma_write(fdev, 0UL, INT_MASK);
+ fdma_write(fdev, 0UL, CMD_MASK);
+ /* disable cpu pipeline clock */
+ fdma_write(fdev, FDMA_CLK_GATE_DIS, CLK_GATE);
+ writel(!FDMA_EN_RUN, fdev->io_base + FDMA_EN_OFST);
+
+ return readl(fdev->io_base + FDMA_EN_OFST);
+}
+
+static int st_fdma_dreq_get(struct st_fdma_chan *fchan)
+{
+ struct st_fdma_dev *fdev = fchan->fdev;
+ u32 req_line_cfg = fchan->cfg.req_line;
+ u32 dreq_line;
+ int try = 0;
+
+ /*
+ * dreq_mask is shared for n channels of fdma, so all accesses must be
+ * atomic. if the dreq_mask it change between ffz ant set_bit,
+ * we retry
+ */
+ do {
+ if (fdev->dreq_mask == ~0L) {
+ dev_err(fdev->dev, "No req lines available\n");
+ return -EINVAL;
+ }
+
+ if (try || req_line_cfg >= ST_FDMA_NR_DREQS) {
+ dev_err(fdev->dev, "Invalid or used req line\n");
+ return -EINVAL;
+ } else {
+ dreq_line = req_line_cfg;
+ }
+
+ try++;
+ } while (test_and_set_bit(dreq_line, &fdev->dreq_mask));
+
+ dev_dbg(fdev->dev, "get dreq_line:%d mask:%#lx\n",
+ dreq_line, fdev->dreq_mask);
+
+ return dreq_line;
+}
+
+static void st_fdma_dreq_put(struct st_fdma_chan *fchan)
+{
+ struct st_fdma_dev *fdev = fchan->fdev;
+
+ dev_dbg(fdev->dev, "put dreq_line:%#x\n", fchan->dreq_line);
+ clear_bit(fchan->dreq_line, &fdev->dreq_mask);
+}
+
+static void st_fdma_xfer_desc(struct st_fdma_chan *fchan)
+{
+ struct virt_dma_desc *vdesc;
+ unsigned long nbytes, ch_cmd, cmd;
+
+ vdesc = vchan_next_desc(&fchan->vchan);
+ if (!vdesc)
+ return;
+
+ fchan->fdesc = to_st_fdma_desc(vdesc);
+ nbytes = fchan->fdesc->node[0].desc->nbytes;
+ cmd = FDMA_CMD_START(fchan->vchan.chan.chan_id);
+ ch_cmd = fchan->fdesc->node[0].pdesc | FDMA_CH_CMD_STA_START;
+
+ /* start the channel for the descriptor */
+ fnode_write(fchan, nbytes, CNTN);
+ fchan_write(fchan, ch_cmd, CH_CMD);
+ writel(cmd, fchan->fdev->io_base + FDMA_CMD_SET_OFST);
+
+ dev_dbg(fchan->fdev->dev, "start chan:%d\n", fchan->vchan.chan.chan_id);
+}
+
+static void st_fdma_ch_sta_update(struct st_fdma_chan *fchan,
+ unsigned long int_sta)
+{
+ unsigned long ch_sta, ch_err;
+ int ch_id = fchan->vchan.chan.chan_id;
+ struct st_fdma_dev *fdev = fchan->fdev;
+
+ ch_sta = fchan_read(fchan, CH_CMD);
+ ch_err = ch_sta & FDMA_CH_CMD_ERR_MASK;
+ ch_sta &= FDMA_CH_CMD_STA_MASK;
+
+ if (int_sta & FDMA_INT_STA_ERR) {
+ dev_warn(fdev->dev, "chan:%d, error:%ld\n", ch_id, ch_err);
+ fchan->status = DMA_ERROR;
+ return;
+ }
+
+ switch (ch_sta) {
+ case FDMA_CH_CMD_STA_PAUSED:
+ fchan->status = DMA_PAUSED;
+ break;
+ case FDMA_CH_CMD_STA_RUNNING:
+ fchan->status = DMA_IN_PROGRESS;
+ break;
+ }
+}
+
+static irqreturn_t st_fdma_irq_handler(int irq, void *dev_id)
+{
+ struct st_fdma_dev *fdev = dev_id;
+ irqreturn_t ret = IRQ_NONE;
+ struct st_fdma_chan *fchan = &fdev->chans[0];
+ unsigned long int_sta, clr;
+
+ int_sta = fdma_read(fdev, INT_STA);
+ clr = int_sta;
+
+ for (; int_sta != 0 ; int_sta >>= 2, fchan++) {
+ if (!(int_sta & (FDMA_INT_STA_CH | FDMA_INT_STA_ERR)))
+ continue;
+
+ spin_lock(&fchan->vchan.lock);
+ st_fdma_ch_sta_update(fchan, int_sta);
+
+ if (fchan->fdesc) {
+ if (!fchan->fdesc->iscyclic) {
+ list_del(&fchan->fdesc->vdesc.node);
+ vchan_cookie_complete(&fchan->fdesc->vdesc);
+ fchan->fdesc = NULL;
+ fchan->status = DMA_COMPLETE;
+ } else {
+ vchan_cyclic_callback(&fchan->fdesc->vdesc);
+ }
+
+ /* Start the next descriptor (if available) */
+ if (!fchan->fdesc)
+ st_fdma_xfer_desc(fchan);
+ }
+
+ spin_unlock(&fchan->vchan.lock);
+ ret = IRQ_HANDLED;
+ }
+
+ fdma_write(fdev, clr, INT_CLR);
+
+ return ret;
+}
+
+static struct dma_chan *st_fdma_of_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ struct st_fdma_dev *fdev = ofdma->of_dma_data;
+ struct st_fdma_cfg cfg;
+
+ if (dma_spec->args_count < 1)
+ return NULL;
+
+ cfg.of_node = dma_spec->np;
+ cfg.req_line = dma_spec->args[0];
+ cfg.req_ctrl = 0;
+ cfg.type = ST_FDMA_TYPE_FREE_RUN;
+
+ if (dma_spec->args_count > 1)
+ cfg.req_ctrl = dma_spec->args[1] & REQ_CTRL_CFG_MASK;
+
+ if (dma_spec->args_count > 2)
+ cfg.type = dma_spec->args[2];
+
+ dev_dbg(fdev->dev, "xlate req_line:%d type:%d req_ctrl:%#lx\n",
+ cfg.req_line, cfg.type, cfg.req_ctrl);
+
+ return dma_request_channel(fdev->dma_device.cap_mask,
+ st_fdma_filter_fn, &cfg);
+}
+
+static void st_fdma_free_desc(struct virt_dma_desc *vdesc)
+{
+ struct st_fdma_desc *fdesc;
+ int i;
+
+ fdesc = to_st_fdma_desc(vdesc);
+ for (i = 0; i < fdesc->n_nodes; i++)
+ dma_pool_free(fdesc->fchan->node_pool,
+ fdesc->node[i].desc,
+ fdesc->node[i].pdesc);
+ kfree(fdesc);
+}
+
+static struct st_fdma_desc *st_fdma_alloc_desc(struct st_fdma_chan *fchan,
+ int sg_len)
+{
+ struct st_fdma_desc *fdesc;
+ int i;
+
+ fdesc = kzalloc(sizeof(*fdesc) +
+ sizeof(struct st_fdma_sw_node) * sg_len, GFP_NOWAIT);
+ if (!fdesc)
+ return NULL;
+
+ fdesc->fchan = fchan;
+ fdesc->n_nodes = sg_len;
+ for (i = 0; i < sg_len; i++) {
+ fdesc->node[i].desc = dma_pool_alloc(fchan->node_pool,
+ GFP_NOWAIT, &fdesc->node[i].pdesc);
+ if (!fdesc->node[i].desc)
+ goto err;
+ }
+ return fdesc;
+
+err:
+ while (--i >= 0)
+ dma_pool_free(fchan->node_pool, fdesc->node[i].desc,
+ fdesc->node[i].pdesc);
+ kfree(fdesc);
+ return NULL;
+}
+
+static int st_fdma_alloc_chan_res(struct dma_chan *chan)
+{
+ struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
+
+ if (fchan->cfg.type == ST_FDMA_TYPE_FREE_RUN) {
+ fchan->dreq_line = 0;
+ } else {
+ fchan->dreq_line = st_fdma_dreq_get(fchan);
+ if (IS_ERR_VALUE(fchan->dreq_line))
+ return -EINVAL;
+ }
+
+ /* Create the dma pool for descriptor allocation */
+ fchan->node_pool = dmam_pool_create(dev_name(&chan->dev->device),
+ fchan->fdev->dev,
+ sizeof(struct st_fdma_hw_node),
+ __alignof__(struct st_fdma_hw_node),
+ 0);
+
+ if (!fchan->node_pool) {
+ dev_err(fchan->fdev->dev, "unable to allocate desc pool\n");
+ return -ENOMEM;
+ }
+
+ dev_dbg(fchan->fdev->dev, "alloc ch_id:%d type:%d\n",
+ fchan->vchan.chan.chan_id, fchan->cfg.type);
+
+ return 0;
+}
+
+static void st_fdma_free_chan_res(struct dma_chan *chan)
+{
+ struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
+ unsigned long flags;
+ LIST_HEAD(head);
+
+ dev_dbg(fchan->fdev->dev, "freeing chan:%d\n",
+ fchan->vchan.chan.chan_id);
+
+ if (fchan->cfg.type != ST_FDMA_TYPE_FREE_RUN)
+ st_fdma_dreq_put(fchan);
+
+ spin_lock_irqsave(&fchan->vchan.lock, flags);
+ fchan->fdesc = NULL;
+ vchan_get_all_descriptors(&fchan->vchan, &head);
+ spin_unlock_irqrestore(&fchan->vchan.lock, flags);
+
+ dma_pool_destroy(fchan->node_pool);
+ fchan->node_pool = NULL;
+ memset(&fchan->cfg, 0, sizeof(struct st_fdma_cfg));
+}
+
+static struct dma_async_tx_descriptor *st_fdma_prep_dma_memcpy(
+ struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
+ size_t len, unsigned long flags)
+{
+ struct st_fdma_chan *fchan;
+ struct st_fdma_desc *fdesc;
+ struct st_fdma_hw_node *hw_node;
+
+ if (!len)
+ return NULL;
+
+ fchan = to_st_fdma_chan(chan);
+
+ if (!atomic_read(&fchan->fdev->fw_loaded)) {
+ dev_err(fchan->fdev->dev, "%s: fdma fw not loaded\n", __func__);
+ return NULL;
+ }
+
+ /* We only require a single descriptor */
+ fdesc = st_fdma_alloc_desc(fchan, 1);
+ if (!fdesc) {
+ dev_err(fchan->fdev->dev, "no memory for desc\n");
+ return NULL;
+ }
+
+ hw_node = fdesc->node[0].desc;
+ hw_node->next = 0;
+ hw_node->control = NODE_CTRL_REQ_MAP_FREE_RUN;
+ hw_node->control |= NODE_CTRL_SRC_INCR;
+ hw_node->control |= NODE_CTRL_DST_INCR;
+ hw_node->control |= NODE_CTRL_INT_EON;
+ hw_node->nbytes = len;
+ hw_node->saddr = src;
+ hw_node->daddr = dst;
+ hw_node->generic.length = len;
+ hw_node->generic.sstride = 0;
+ hw_node->generic.dstride = 0;
+
+ return vchan_tx_prep(&fchan->vchan, &fdesc->vdesc, flags);
+}
+
+static int config_reqctrl(struct st_fdma_chan *fchan,
+ enum dma_transfer_direction direction)
+{
+ u32 maxburst = 0, addr = 0;
+ enum dma_slave_buswidth width;
+ int ch_id = fchan->vchan.chan.chan_id;
+ struct st_fdma_dev *fdev = fchan->fdev;
+
+ if (direction == DMA_DEV_TO_MEM) {
+ fchan->cfg.req_ctrl &= ~REQ_CTRL_WNR;
+ maxburst = fchan->scfg.src_maxburst;
+ width = fchan->scfg.src_addr_width;
+ addr = fchan->scfg.src_addr;
+ } else if (direction == DMA_MEM_TO_DEV) {
+ fchan->cfg.req_ctrl |= REQ_CTRL_WNR;
+ maxburst = fchan->scfg.dst_maxburst;
+ width = fchan->scfg.dst_addr_width;
+ addr = fchan->scfg.dst_addr;
+ } else {
+ return -EINVAL;
+ }
+
+ fchan->cfg.req_ctrl &= ~REQ_CTRL_OPCODE_MASK;
+ if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
+ fchan->cfg.req_ctrl |= REQ_CTRL_OPCODE_LD_ST1;
+ else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
+ fchan->cfg.req_ctrl |= REQ_CTRL_OPCODE_LD_ST2;
+ else if (width == DMA_SLAVE_BUSWIDTH_4_BYTES)
+ fchan->cfg.req_ctrl |= REQ_CTRL_OPCODE_LD_ST4;
+ else if (width == DMA_SLAVE_BUSWIDTH_8_BYTES)
+ fchan->cfg.req_ctrl |= REQ_CTRL_OPCODE_LD_ST8;
+ else
+ return -EINVAL;
+
+ fchan->cfg.req_ctrl &= ~REQ_CTRL_NUM_OPS_MASK;
+ fchan->cfg.req_ctrl |= REQ_CTRL_NUM_OPS(maxburst-1);
+ dreq_write(fchan, fchan->cfg.req_ctrl, REQ_CTRL);
+
+ fchan->cfg.dev_addr = addr;
+ fchan->cfg.dir = direction;
+
+ dev_dbg(fdev->dev, "chan:%d config_reqctrl:%#x req_ctrl:%#lx\n",
+ ch_id, addr, fchan->cfg.req_ctrl);
+
+ return 0;
+}
+
+static void fill_hw_node(struct st_fdma_hw_node *hw_node,
+ struct st_fdma_chan *fchan,
+ enum dma_transfer_direction direction)
+{
+
+ if (direction == DMA_MEM_TO_DEV) {
+ hw_node->control |= NODE_CTRL_SRC_INCR;
+ hw_node->control |= NODE_CTRL_DST_STATIC;
+ hw_node->daddr = fchan->cfg.dev_addr;
+ } else {
+ hw_node->control |= NODE_CTRL_SRC_STATIC;
+ hw_node->control |= NODE_CTRL_DST_INCR;
+ hw_node->saddr = fchan->cfg.dev_addr;
+ }
+ hw_node->generic.sstride = 0;
+ hw_node->generic.dstride = 0;
+}
+
+static struct dma_async_tx_descriptor *st_fdma_prep_dma_cyclic(
+ struct dma_chan *chan, dma_addr_t buf_addr, size_t len,
+ size_t period_len, enum dma_transfer_direction direction,
+ unsigned long flags)
+{
+ struct st_fdma_chan *fchan;
+ struct st_fdma_desc *fdesc;
+ int sg_len, i;
+
+ if (!chan || !len || !period_len)
+ return NULL;
+
+ fchan = to_st_fdma_chan(chan);
+
+ if (!atomic_read(&fchan->fdev->fw_loaded)) {
+ dev_err(fchan->fdev->dev, "%s: fdma fw not loaded\n", __func__);
+ return NULL;
+ }
+
+ if (!is_slave_direction(direction)) {
+ dev_err(fchan->fdev->dev, "bad direction?\n");
+ return NULL;
+ }
+
+ if (config_reqctrl(fchan, direction)) {
+ dev_err(fchan->fdev->dev, "bad width or direction\n");
+ return NULL;
+ }
+
+ /* the buffer length must be a multiple of period_len */
+ if (len % period_len != 0) {
+ dev_err(fchan->fdev->dev, "len is not multiple of period\n");
+ return NULL;
+ }
+
+ sg_len = len / period_len;
+ fdesc = st_fdma_alloc_desc(fchan, sg_len);
+ if (!fdesc) {
+ dev_err(fchan->fdev->dev, "no memory for desc\n");
+ return NULL;
+ }
+
+ fdesc->iscyclic = true;
+
+ for (i = 0; i < sg_len; i++) {
+ struct st_fdma_hw_node *hw_node = fdesc->node[i].desc;
+
+ hw_node->next = fdesc->node[(i + 1) % sg_len].pdesc;
+
+ hw_node->control = NODE_CTRL_REQ_MAP_DREQ(fchan->dreq_line);
+ hw_node->control |= NODE_CTRL_INT_EON;
+
+
+ fill_hw_node(hw_node, fchan, direction);
+
+ if (direction == DMA_MEM_TO_DEV)
+ hw_node->saddr = buf_addr + (i * period_len);
+ else
+ hw_node->daddr = buf_addr + (i * period_len);
+
+ hw_node->nbytes = period_len;
+ hw_node->generic.length = period_len;
+ }
+
+ return vchan_tx_prep(&fchan->vchan, &fdesc->vdesc, flags);
+}
+
+static struct dma_async_tx_descriptor *st_fdma_prep_slave_sg(
+ struct dma_chan *chan, struct scatterlist *sgl,
+ unsigned int sg_len, enum dma_transfer_direction direction,
+ unsigned long flags, void *context)
+{
+ struct st_fdma_chan *fchan;
+ struct st_fdma_desc *fdesc;
+ struct st_fdma_hw_node *hw_node;
+ struct scatterlist *sg;
+ int i;
+
+ if (!chan || !sgl || !sg_len)
+ return NULL;
+
+ fchan = to_st_fdma_chan(chan);
+
+ if (!atomic_read(&fchan->fdev->fw_loaded)) {
+ dev_err(fchan->fdev->dev, "%s: fdma fw not loaded\n", __func__);
+ return NULL;
+ }
+
+ if (!is_slave_direction(direction)) {
+ dev_err(fchan->fdev->dev, "bad direction?\n");
+ return NULL;
+ }
+
+ fdesc = st_fdma_alloc_desc(fchan, sg_len);
+ if (!fdesc) {
+ dev_err(fchan->fdev->dev, "no memory for desc\n");
+ return NULL;
+ }
+
+ fdesc->iscyclic = false;
+
+ for_each_sg(sgl, sg, sg_len, i) {
+ hw_node = fdesc->node[i].desc;
+
+ hw_node->next = fdesc->node[(i + 1) % sg_len].pdesc;
+ hw_node->control = NODE_CTRL_REQ_MAP_DREQ(fchan->dreq_line);
+
+ fill_hw_node(hw_node, fchan, direction);
+
+ if (direction == DMA_MEM_TO_DEV)
+ hw_node->saddr = sg_dma_address(sg);
+ else
+ hw_node->daddr = sg_dma_address(sg);
+
+ hw_node->nbytes = sg_dma_len(sg);
+ hw_node->generic.length = sg_dma_len(sg);
+ }
+
+ /* interrupt at end of last node */
+ hw_node->control |= NODE_CTRL_INT_EON;
+
+ return vchan_tx_prep(&fchan->vchan, &fdesc->vdesc, flags);
+}
+
+static size_t st_fdma_desc_residue(struct st_fdma_chan *fchan,
+ struct virt_dma_desc *vdesc,
+ bool in_progress)
+{
+ struct st_fdma_desc *fdesc = fchan->fdesc;
+ size_t residue = 0;
+ dma_addr_t cur_addr = 0;
+ int i;
+
+ if (in_progress) {
+ cur_addr = fchan_read(fchan, CH_CMD);
+ cur_addr &= FDMA_CH_CMD_DATA_MASK;
+ }
+
+ for (i = fchan->fdesc->n_nodes - 1 ; i >= 0; i--) {
+ if (cur_addr == fdesc->node[i].pdesc) {
+ residue += fnode_read(fchan, CNTN);
+ break;
+ }
+ residue += fdesc->node[i].desc->nbytes;
+ }
+
+ return residue;
+}
+
+static enum dma_status st_fdma_tx_status(struct dma_chan *chan,
+ dma_cookie_t cookie,
+ struct dma_tx_state *txstate)
+{
+ struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
+ struct virt_dma_desc *vd;
+ enum dma_status ret;
+ unsigned long flags;
+
+ ret = dma_cookie_status(chan, cookie, txstate);
+ if (ret == DMA_COMPLETE)
+ return ret;
+
+ if (!txstate)
+ return fchan->status;
+
+ spin_lock_irqsave(&fchan->vchan.lock, flags);
+ vd = vchan_find_desc(&fchan->vchan, cookie);
+ if (fchan->fdesc && cookie == fchan->fdesc->vdesc.tx.cookie)
+ txstate->residue = st_fdma_desc_residue(fchan, vd, true);
+ else if (vd)
+ txstate->residue = st_fdma_desc_residue(fchan, vd, false);
+ else
+ txstate->residue = 0;
+
+ spin_unlock_irqrestore(&fchan->vchan.lock, flags);
+
+ return fchan->status;
+}
+
+static void st_fdma_issue_pending(struct dma_chan *chan)
+{
+ struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
+ unsigned long flags;
+
+ spin_lock_irqsave(&fchan->vchan.lock, flags);
+
+ if (vchan_issue_pending(&fchan->vchan) && !fchan->fdesc)
+ st_fdma_xfer_desc(fchan);
+
+ spin_unlock_irqrestore(&fchan->vchan.lock, flags);
+}
+
+static int st_fdma_pause(struct dma_chan *chan)
+{
+ unsigned long flags;
+ LIST_HEAD(head);
+ struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
+ int ch_id = fchan->vchan.chan.chan_id;
+ unsigned long cmd = FDMA_CMD_PAUSE(ch_id);
+
+ dev_dbg(fchan->fdev->dev, "pause chan:%d\n", ch_id);
+
+ spin_lock_irqsave(&fchan->vchan.lock, flags);
+ if (fchan->fdesc)
+ fdma_write(fchan->fdev, cmd, CMD_SET);
+ spin_unlock_irqrestore(&fchan->vchan.lock, flags);
+
+ return 0;
+}
+
+static int st_fdma_resume(struct dma_chan *chan)
+{
+ unsigned long flags;
+ unsigned long val;
+ struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
+ int ch_id = fchan->vchan.chan.chan_id;
+
+ dev_dbg(fchan->fdev->dev, "resume chan:%d\n", ch_id);
+
+ spin_lock_irqsave(&fchan->vchan.lock, flags);
+ if (fchan->fdesc) {
+ val = fchan_read(fchan, CH_CMD);
+ val &= FDMA_CH_CMD_DATA_MASK;
+ fchan_write(fchan, val, CH_CMD);
+ }
+ spin_unlock_irqrestore(&fchan->vchan.lock, flags);
+
+ return 0;
+}
+
+static int st_fdma_terminate_all(struct dma_chan *chan)
+{
+ unsigned long flags;
+ LIST_HEAD(head);
+ struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
+ int ch_id = fchan->vchan.chan.chan_id;
+ unsigned long cmd = FDMA_CMD_PAUSE(ch_id);
+
+ dev_dbg(fchan->fdev->dev, "terminate chan:%d\n", ch_id);
+
+ spin_lock_irqsave(&fchan->vchan.lock, flags);
+ fdma_write(fchan->fdev, cmd, CMD_SET);
+ fchan->fdesc = NULL;
+ vchan_get_all_descriptors(&fchan->vchan, &head);
+ spin_unlock_irqrestore(&fchan->vchan.lock, flags);
+ vchan_dma_desc_free_list(&fchan->vchan, &head);
+
+ return 0;
+}
+
+static int st_fdma_slave_config(struct dma_chan *chan,
+ struct dma_slave_config *slave_cfg)
+{
+ struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
+ memcpy(&fchan->scfg, slave_cfg, sizeof(fchan->scfg));
+ return 0;
+}
+
+static const struct st_fdma_ram fdma_mpe31_mem[] = {
+ { .name = "dmem", .offset = 0x10000, .size = 0x3000 },
+ { .name = "imem", .offset = 0x18000, .size = 0x8000 },
+};
+
+static const struct st_fdma_driverdata fdma_mpe31_stih407_11 = {
+ .fdma_mem = fdma_mpe31_mem,
+ .num_mem = ARRAY_SIZE(fdma_mpe31_mem),
+ .name = "STiH407",
+ .id = 0,
+};
+
+static const struct st_fdma_driverdata fdma_mpe31_stih407_12 = {
+ .fdma_mem = fdma_mpe31_mem,
+ .num_mem = ARRAY_SIZE(fdma_mpe31_mem),
+ .name = "STiH407",
+ .id = 1,
+};
+
+static const struct st_fdma_driverdata fdma_mpe31_stih407_13 = {
+ .fdma_mem = fdma_mpe31_mem,
+ .num_mem = ARRAY_SIZE(fdma_mpe31_mem),
+ .name = "STiH407",
+ .id = 2,
+};
+
+static const struct of_device_id st_fdma_match[] = {
+ { .compatible = "st,stih407-fdma-mpe31-11"
+ , .data = &fdma_mpe31_stih407_11 },
+ { .compatible = "st,stih407-fdma-mpe31-12"
+ , .data = &fdma_mpe31_stih407_12 },
+ { .compatible = "st,stih407-fdma-mpe31-13"
+ , .data = &fdma_mpe31_stih407_13 },
+ {},
+};
+MODULE_DEVICE_TABLE(of, st_fdma_match);
+
+static int st_fdma_parse_dt(struct platform_device *pdev,
+ const struct st_fdma_driverdata *drvdata,
+ struct st_fdma_dev *fdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ int ret;
+
+ if (!np)
+ goto err;
+
+ ret = of_property_read_u32(np, "dma-channels", &fdev->nr_channels);
+ if (ret)
+ goto err;
+
+ snprintf(fdev->fw_name, FW_NAME_SIZE, "fdma_%s_%d.elf",
+ drvdata->name, drvdata->id);
+
+err:
+ return ret;
+}
+#define FDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
+ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
+ BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
+ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
+
+static int st_fdma_probe(struct platform_device *pdev)
+{
+ struct st_fdma_dev *fdev;
+ const struct of_device_id *match;
+ struct device_node *np = pdev->dev.of_node;
+ const struct st_fdma_driverdata *drvdata;
+ int irq, ret, i;
+
+ match = of_match_device((st_fdma_match), &pdev->dev);
+ if (!match || !match->data) {
+ dev_err(&pdev->dev, "No device match found\n");
+ return -ENODEV;
+ }
+
+ drvdata = match->data;
+
+ fdev = devm_kzalloc(&pdev->dev, sizeof(*fdev), GFP_KERNEL);
+ if (!fdev)
+ return -ENOMEM;
+
+ ret = st_fdma_parse_dt(pdev, drvdata, fdev);
+ if (ret) {
+ dev_err(&pdev->dev, "unable to find platform data\n");
+ goto err;
+ }
+
+ fdev->chans = devm_kzalloc(&pdev->dev,
+ fdev->nr_channels
+ * sizeof(struct st_fdma_chan), GFP_KERNEL);
+ if (!fdev->chans)
+ return -ENOMEM;
+
+ fdev->dev = &pdev->dev;
+ fdev->drvdata = drvdata;
+ platform_set_drvdata(pdev, fdev);
+
+ fdev->io_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ fdev->io_base = devm_ioremap_resource(&pdev->dev, fdev->io_res);
+ if (IS_ERR(fdev->io_base))
+ return PTR_ERR(fdev->io_base);
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "Failed to get irq resource\n");
+ return -EINVAL;
+ }
+
+ ret = devm_request_irq(&pdev->dev, irq, st_fdma_irq_handler, 0,
+ dev_name(&pdev->dev), fdev);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to request irq\n");
+ goto err;
+ }
+
+ ret = st_fdma_clk_get(fdev);
+ if (ret)
+ goto err;
+
+ ret = st_fdma_clk_enable(fdev);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to enable clocks\n");
+ goto err_clk;
+ }
+
+ /* Initialise list of FDMA channels */
+ INIT_LIST_HEAD(&fdev->dma_device.channels);
+ for (i = 0; i < fdev->nr_channels; i++) {
+ struct st_fdma_chan *fchan = &fdev->chans[i];
+
+ fchan->fdev = fdev;
+ fchan->vchan.desc_free = st_fdma_free_desc;
+ vchan_init(&fchan->vchan, &fdev->dma_device);
+ }
+
+ /* Initialise the FDMA dreq (reserve 0 & 31 for FDMA use) */
+ fdev->dreq_mask = BIT(0) | BIT(31);
+
+ dma_cap_set(DMA_SLAVE, fdev->dma_device.cap_mask);
+ dma_cap_set(DMA_CYCLIC, fdev->dma_device.cap_mask);
+ dma_cap_set(DMA_MEMCPY, fdev->dma_device.cap_mask);
+
+ fdev->dma_device.dev = &pdev->dev;
+ fdev->dma_device.device_alloc_chan_resources = st_fdma_alloc_chan_res;
+ fdev->dma_device.device_free_chan_resources = st_fdma_free_chan_res;
+ fdev->dma_device.device_prep_dma_cyclic = st_fdma_prep_dma_cyclic;
+ fdev->dma_device.device_prep_slave_sg = st_fdma_prep_slave_sg;
+ fdev->dma_device.device_prep_dma_memcpy = st_fdma_prep_dma_memcpy;
+ fdev->dma_device.device_tx_status = st_fdma_tx_status;
+ fdev->dma_device.device_issue_pending = st_fdma_issue_pending;
+ fdev->dma_device.device_terminate_all = st_fdma_terminate_all;
+ fdev->dma_device.device_config = st_fdma_slave_config;
+ fdev->dma_device.device_pause = st_fdma_pause;
+ fdev->dma_device.device_resume = st_fdma_resume;
+
+ fdev->dma_device.src_addr_widths = FDMA_DMA_BUSWIDTHS;
+ fdev->dma_device.dst_addr_widths = FDMA_DMA_BUSWIDTHS;
+ fdev->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
+ fdev->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
+
+ ret = dma_async_device_register(&fdev->dma_device);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to register DMA device\n");
+ goto err_clk;
+ }
+
+ ret = of_dma_controller_register(np, st_fdma_of_xlate, fdev);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to register controller\n");
+ goto err_dma_dev;
+ }
+
+ dev_info(&pdev->dev, "ST FDMA engine driver, irq:%d\n", irq);
+
+ return 0;
+
+err_dma_dev:
+ dma_async_device_unregister(&fdev->dma_device);
+err_clk:
+ st_fdma_clk_disable(fdev);
+err:
+ return ret;
+}
+
+static int st_fdma_remove(struct platform_device *pdev)
+{
+ struct st_fdma_dev *fdev = platform_get_drvdata(pdev);
+
+ st_fdma_clk_disable(fdev);
+
+ return 0;
+}
+
+static struct platform_driver st_fdma_platform_driver = {
+ .driver = {
+ .name = "st-fdma",
+ .of_match_table = st_fdma_match,
+ },
+ .probe = st_fdma_probe,
+ .remove = st_fdma_remove,
+};
+module_platform_driver(st_fdma_platform_driver);
+
+bool st_fdma_filter_fn(struct dma_chan *chan, void *param)
+{
+ struct st_fdma_cfg *config = param;
+ struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
+
+ if (!param)
+ return false;
+
+ if (fchan->fdev->dma_device.dev->of_node != config->of_node)
+ return false;
+
+ fchan->cfg = *config;
+
+ return true;
+}
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("STMicroelectronics FDMA engine driver");
+MODULE_AUTHOR("Ludovic.barre <Ludovic.barre@st.com>");
--
1.9.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [PATCH 03/18] dmaengine: st_fdma: Add STMicroelectronics FDMA engine driver support
2016-04-21 11:04 ` [PATCH 03/18] dmaengine: st_fdma: Add STMicroelectronics FDMA engine driver support Peter Griffin
@ 2016-04-21 11:24 ` Arnd Bergmann
2016-04-21 11:26 ` Appana Durga Kedareswara Rao
2016-04-26 16:56 ` Vinod Koul
2 siblings, 0 replies; 53+ messages in thread
From: Arnd Bergmann @ 2016-04-21 11:24 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Peter Griffin, linux-kernel, srinivas.kandagatla, maxime.coquelin,
patrice.chotard, vinod.koul, devicetree, broonie, dmaengine,
lee.jones, ludovic.barre
On Thursday 21 April 2016 12:04:20 Peter Griffin wrote:
> This patch adds support for the Flexible Direct Memory Access (FDMA) core
> driver. The FDMA is a slim core CPU with a dedicated firmware.
> It is a general purpose DMA controller capable of supporting 16
> independent DMA channels. Data moves maybe from memory to memory
> or between memory and paced latency critical real time targets and it
> is found on al STi based chipsets.
>
> Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> drivers/dma/Kconfig | 12 +
> drivers/dma/Makefile | 1 +
> drivers/dma/st_fdma.c | 967 ++++++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 980 insertions(+)
> create mode 100644 drivers/dma/st_fdma.c
>
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index d96d87c..5910c4f 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -527,6 +527,18 @@ config ZX_DMA
> help
> Support the DMA engine for ZTE ZX296702 platform devices.
>
> +config ST_FDMA
> + tristate "ST FDMA dmaengine support"
> + depends on ARCH_STI
Try to ensure that the driver builds on x86 (possibly adding
further dependencies if needed), then make this
depends on ARCH_STI || COMPILE_TEST
to get better build coverage.
> +static struct dma_chan *st_fdma_of_xlate(struct of_phandle_args *dma_spec,
> + struct of_dma *ofdma)
> +{
> + struct st_fdma_dev *fdev = ofdma->of_dma_data;
> + struct st_fdma_cfg cfg;
> +
> + if (dma_spec->args_count < 1)
> + return NULL;
> +
> + cfg.of_node = dma_spec->np;
> + cfg.req_line = dma_spec->args[0];
> + cfg.req_ctrl = 0;
> + cfg.type = ST_FDMA_TYPE_FREE_RUN;
> +
> + if (dma_spec->args_count > 1)
> + cfg.req_ctrl = dma_spec->args[1] & REQ_CTRL_CFG_MASK;
> +
> + if (dma_spec->args_count > 2)
> + cfg.type = dma_spec->args[2];
> +
> + dev_dbg(fdev->dev, "xlate req_line:%d type:%d req_ctrl:%#lx\n",
> + cfg.req_line, cfg.type, cfg.req_ctrl);
> +
> + return dma_request_channel(fdev->dma_device.cap_mask,
> + st_fdma_filter_fn, &cfg);
> +}
No need to look at all DMA channels in the system here with
dma_request_channel(). Just call dma_get_any_slave_channel()
to get the first available channel for this engine, then
set the configuration right in that channel data while parsing
the DT properties.
Arnd
^ permalink raw reply [flat|nested] 53+ messages in thread* RE: [PATCH 03/18] dmaengine: st_fdma: Add STMicroelectronics FDMA engine driver support
2016-04-21 11:04 ` [PATCH 03/18] dmaengine: st_fdma: Add STMicroelectronics FDMA engine driver support Peter Griffin
2016-04-21 11:24 ` Arnd Bergmann
@ 2016-04-21 11:26 ` Appana Durga Kedareswara Rao
[not found] ` <C246CAC1457055469EF09E3A7AC4E11A4A57989B-4lKfpRxZ5enZMOc0yg5rMog+Gb3gawCHQz34XiSyOiE@public.gmane.org>
2016-04-26 16:56 ` Vinod Koul
2 siblings, 1 reply; 53+ messages in thread
From: Appana Durga Kedareswara Rao @ 2016-04-21 11:26 UTC (permalink / raw)
To: Peter Griffin, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, srinivas.kandagatla@gmail.com,
maxime.coquelin@st.com, patrice.chotard@st.com,
vinod.koul@intel.com
Cc: lee.jones@linaro.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, arnd@arndb.de, broonie@kernel.org,
ludovic.barre@st.com, Appana Durga Kedareswara Rao
> -----Original Message-----
> From: dmaengine-owner@vger.kernel.org [mailto:dmaengine-
> owner@vger.kernel.org] On Behalf Of Peter Griffin
> Sent: Thursday, April 21, 2016 4:34 PM
> To: linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> srinivas.kandagatla@gmail.com; maxime.coquelin@st.com;
> patrice.chotard@st.com; vinod.koul@intel.com
> Cc: peter.griffin@linaro.org; lee.jones@linaro.org;
> dmaengine@vger.kernel.org; devicetree@vger.kernel.org; arnd@arndb.de;
> broonie@kernel.org; ludovic.barre@st.com
> Subject: [PATCH 03/18] dmaengine: st_fdma: Add STMicroelectronics FDMA
> engine driver support
>
> This patch adds support for the Flexible Direct Memory Access (FDMA) core
> driver. The FDMA is a slim core CPU with a dedicated firmware.
> It is a general purpose DMA controller capable of supporting 16
> independent DMA channels. Data moves maybe from memory to memory
> or between memory and paced latency critical real time targets and it
> is found on al STi based chipsets.
>
> Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> drivers/dma/Kconfig | 12 +
> drivers/dma/Makefile | 1 +
> drivers/dma/st_fdma.c | 967
> ++++++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 980 insertions(+)
> create mode 100644 drivers/dma/st_fdma.c
>
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index d96d87c..5910c4f 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -527,6 +527,18 @@ config ZX_DMA
> help
> Support the DMA engine for ZTE ZX296702 platform devices.
>
> +config ST_FDMA
> + tristate "ST FDMA dmaengine support"
> + depends on ARCH_STI
> + select DMA_ENGINE
> + select FW_LOADER
> + select DMA_VIRTUAL_CHANNELS
> + help
> + Enable support for ST FDMA controller.
> + It supports 16 independent DMA channels, accepts up to 32 DMA
> requests
> +
> + Say Y here if you have such a chipset.
> + If unsure, say N.
>
> # driver files
> source "drivers/dma/bestcomm/Kconfig"
> diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
> index 6084127..b81ca99 100644
> --- a/drivers/dma/Makefile
> +++ b/drivers/dma/Makefile
> @@ -65,6 +65,7 @@ obj-$(CONFIG_TI_DMA_CROSSBAR) += ti-dma-crossbar.o
> obj-$(CONFIG_TI_EDMA) += edma.o
> obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
> obj-$(CONFIG_ZX_DMA) += zx296702_dma.o
> +obj-$(CONFIG_ST_FDMA) += st_fdma.o
>
> obj-y += qcom/
> obj-y += xilinx/
> diff --git a/drivers/dma/st_fdma.c b/drivers/dma/st_fdma.c
> new file mode 100644
> index 0000000..9bf0100
> --- /dev/null
> +++ b/drivers/dma/st_fdma.c
> @@ -0,0 +1,967 @@
> +/*
> + * st_fdma.c
> + *
> + * Copyright (C) 2014 STMicroelectronics
> + * Author: Ludovic Barre <Ludovic.barre@st.com>
> + * License terms: GNU General Public License (GPL), version 2
> + */
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_dma.h>
> +#include <linux/platform_device.h>
> +#include <linux/interrupt.h>
> +#include <linux/clk.h>
> +#include <linux/dmaengine.h>
> +#include <linux/dmapool.h>
> +#include <linux/firmware.h>
> +#include <linux/elf.h>
> +#include <linux/atomic.h>
> +
> +#include "st_fdma.h"
> +#include "dmaengine.h"
> +#include "virt-dma.h"
> +
> +static char *fdma_clk_name[CLK_MAX_NUM] = {
> + [CLK_SLIM] = "fdma_slim",
> + [CLK_HI] = "fdma_hi",
> + [CLK_LOW] = "fdma_low",
> + [CLK_IC] = "fdma_ic",
> +};
> +
> +static int st_fdma_clk_get(struct st_fdma_dev *fdev)
> +{
> + int i;
> +
> + for (i = 0; i < CLK_MAX_NUM; i++) {
> + fdev->clks[i] = devm_clk_get(fdev->dev, fdma_clk_name[i]);
> + if (IS_ERR(fdev->clks[i])) {
> + dev_err(fdev->dev,
> + "failed to get clock: %s\n", fdma_clk_name[i]);
> + return PTR_ERR(fdev->clks[i]);
> + }
> + }
> +
> + if (i != CLK_MAX_NUM) {
> + dev_err(fdev->dev, "all clocks are not defined\n");
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int st_fdma_clk_enable(struct st_fdma_dev *fdev)
> +{
> + int i, ret;
> +
> + for (i = 0; i < CLK_MAX_NUM; i++) {
> + ret = clk_prepare_enable(fdev->clks[i]);
> + if (ret < 0)
You should disable and unprepared the other clocks...
Kedar...
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static void st_fdma_clk_disable(struct st_fdma_dev *fdev)
> +{
> + int i;
> +
> + for (i = 0; i < CLK_MAX_NUM; i++)
> + clk_disable_unprepare(fdev->clks[i]);
> +}
> +
> +static inline struct st_fdma_chan *to_st_fdma_chan(struct dma_chan *c)
> +{
> + return container_of(c, struct st_fdma_chan, vchan.chan);
> +}
> +
> +static struct st_fdma_desc *to_st_fdma_desc(struct virt_dma_desc *vd)
> +{
> + return container_of(vd, struct st_fdma_desc, vdesc);
> +}
> +
> +static void st_fdma_enable(struct st_fdma_dev *fdev)
> +{
> + unsigned long hw_id, hw_ver, fw_rev;
> + u32 val;
> +
> + /* disable CPU pipeline clock & reset cpu pipeline */
> + val = FDMA_CLK_GATE_DIS | FDMA_CLK_GATE_RESET;
> + fdma_write(fdev, val, CLK_GATE);
> + /* disable SLIM core STBus sync */
> + fdma_write(fdev, FDMA_STBUS_SYNC_DIS, STBUS_SYNC);
> + /* enable cpu pipeline clock */
> + fdma_write(fdev, !FDMA_CLK_GATE_DIS, CLK_GATE);
> + /* clear int & cmd mailbox */
> + fdma_write(fdev, ~0UL, INT_CLR);
> + fdma_write(fdev, ~0UL, CMD_CLR);
> + /* enable all channels cmd & int */
> + fdma_write(fdev, ~0UL, INT_MASK);
> + fdma_write(fdev, ~0UL, CMD_MASK);
> + /* enable cpu */
> + writel(FDMA_EN_RUN, fdev->io_base + FDMA_EN_OFST);
> +
> + hw_id = fdma_read(fdev, ID);
> + hw_ver = fdma_read(fdev, VER);
> + fw_rev = fdma_read(fdev, REV_ID);
> +
> + dev_info(fdev->dev, "fw rev:%ld.%ld on SLIM %ld.%ld\n",
> + FDMA_REV_ID_MAJ(fw_rev), FDMA_REV_ID_MIN(fw_rev),
> + hw_id, hw_ver);
> +}
> +
> +static int st_fdma_disable(struct st_fdma_dev *fdev)
> +{
> + /* mask all (cmd & int) channels */
> + fdma_write(fdev, 0UL, INT_MASK);
> + fdma_write(fdev, 0UL, CMD_MASK);
> + /* disable cpu pipeline clock */
> + fdma_write(fdev, FDMA_CLK_GATE_DIS, CLK_GATE);
> + writel(!FDMA_EN_RUN, fdev->io_base + FDMA_EN_OFST);
> +
> + return readl(fdev->io_base + FDMA_EN_OFST);
> +}
> +
> +static int st_fdma_dreq_get(struct st_fdma_chan *fchan)
> +{
> + struct st_fdma_dev *fdev = fchan->fdev;
> + u32 req_line_cfg = fchan->cfg.req_line;
> + u32 dreq_line;
> + int try = 0;
> +
> + /*
> + * dreq_mask is shared for n channels of fdma, so all accesses must be
> + * atomic. if the dreq_mask it change between ffz ant set_bit,
> + * we retry
> + */
> + do {
> + if (fdev->dreq_mask == ~0L) {
> + dev_err(fdev->dev, "No req lines available\n");
> + return -EINVAL;
> + }
> +
> + if (try || req_line_cfg >= ST_FDMA_NR_DREQS) {
> + dev_err(fdev->dev, "Invalid or used req line\n");
> + return -EINVAL;
> + } else {
> + dreq_line = req_line_cfg;
> + }
> +
> + try++;
> + } while (test_and_set_bit(dreq_line, &fdev->dreq_mask));
> +
> + dev_dbg(fdev->dev, "get dreq_line:%d mask:%#lx\n",
> + dreq_line, fdev->dreq_mask);
> +
> + return dreq_line;
> +}
> +
> +static void st_fdma_dreq_put(struct st_fdma_chan *fchan)
> +{
> + struct st_fdma_dev *fdev = fchan->fdev;
> +
> + dev_dbg(fdev->dev, "put dreq_line:%#x\n", fchan->dreq_line);
> + clear_bit(fchan->dreq_line, &fdev->dreq_mask);
> +}
> +
> +static void st_fdma_xfer_desc(struct st_fdma_chan *fchan)
> +{
> + struct virt_dma_desc *vdesc;
> + unsigned long nbytes, ch_cmd, cmd;
> +
> + vdesc = vchan_next_desc(&fchan->vchan);
> + if (!vdesc)
> + return;
> +
> + fchan->fdesc = to_st_fdma_desc(vdesc);
> + nbytes = fchan->fdesc->node[0].desc->nbytes;
> + cmd = FDMA_CMD_START(fchan->vchan.chan.chan_id);
> + ch_cmd = fchan->fdesc->node[0].pdesc | FDMA_CH_CMD_STA_START;
> +
> + /* start the channel for the descriptor */
> + fnode_write(fchan, nbytes, CNTN);
> + fchan_write(fchan, ch_cmd, CH_CMD);
> + writel(cmd, fchan->fdev->io_base + FDMA_CMD_SET_OFST);
> +
> + dev_dbg(fchan->fdev->dev, "start chan:%d\n", fchan-
> >vchan.chan.chan_id);
> +}
> +
> +static void st_fdma_ch_sta_update(struct st_fdma_chan *fchan,
> + unsigned long int_sta)
> +{
> + unsigned long ch_sta, ch_err;
> + int ch_id = fchan->vchan.chan.chan_id;
> + struct st_fdma_dev *fdev = fchan->fdev;
> +
> + ch_sta = fchan_read(fchan, CH_CMD);
> + ch_err = ch_sta & FDMA_CH_CMD_ERR_MASK;
> + ch_sta &= FDMA_CH_CMD_STA_MASK;
> +
> + if (int_sta & FDMA_INT_STA_ERR) {
> + dev_warn(fdev->dev, "chan:%d, error:%ld\n", ch_id, ch_err);
> + fchan->status = DMA_ERROR;
> + return;
> + }
> +
> + switch (ch_sta) {
> + case FDMA_CH_CMD_STA_PAUSED:
> + fchan->status = DMA_PAUSED;
> + break;
> + case FDMA_CH_CMD_STA_RUNNING:
> + fchan->status = DMA_IN_PROGRESS;
> + break;
> + }
> +}
> +
> +static irqreturn_t st_fdma_irq_handler(int irq, void *dev_id)
> +{
> + struct st_fdma_dev *fdev = dev_id;
> + irqreturn_t ret = IRQ_NONE;
> + struct st_fdma_chan *fchan = &fdev->chans[0];
> + unsigned long int_sta, clr;
> +
> + int_sta = fdma_read(fdev, INT_STA);
> + clr = int_sta;
> +
> + for (; int_sta != 0 ; int_sta >>= 2, fchan++) {
> + if (!(int_sta & (FDMA_INT_STA_CH | FDMA_INT_STA_ERR)))
> + continue;
> +
> + spin_lock(&fchan->vchan.lock);
> + st_fdma_ch_sta_update(fchan, int_sta);
> +
> + if (fchan->fdesc) {
> + if (!fchan->fdesc->iscyclic) {
> + list_del(&fchan->fdesc->vdesc.node);
> + vchan_cookie_complete(&fchan->fdesc-
> >vdesc);
> + fchan->fdesc = NULL;
> + fchan->status = DMA_COMPLETE;
> + } else {
> + vchan_cyclic_callback(&fchan->fdesc->vdesc);
> + }
> +
> + /* Start the next descriptor (if available) */
> + if (!fchan->fdesc)
> + st_fdma_xfer_desc(fchan);
> + }
> +
> + spin_unlock(&fchan->vchan.lock);
> + ret = IRQ_HANDLED;
> + }
> +
> + fdma_write(fdev, clr, INT_CLR);
> +
> + return ret;
> +}
> +
> +static struct dma_chan *st_fdma_of_xlate(struct of_phandle_args *dma_spec,
> + struct of_dma *ofdma)
> +{
> + struct st_fdma_dev *fdev = ofdma->of_dma_data;
> + struct st_fdma_cfg cfg;
> +
> + if (dma_spec->args_count < 1)
> + return NULL;
> +
> + cfg.of_node = dma_spec->np;
> + cfg.req_line = dma_spec->args[0];
> + cfg.req_ctrl = 0;
> + cfg.type = ST_FDMA_TYPE_FREE_RUN;
> +
> + if (dma_spec->args_count > 1)
> + cfg.req_ctrl = dma_spec->args[1] & REQ_CTRL_CFG_MASK;
> +
> + if (dma_spec->args_count > 2)
> + cfg.type = dma_spec->args[2];
> +
> + dev_dbg(fdev->dev, "xlate req_line:%d type:%d req_ctrl:%#lx\n",
> + cfg.req_line, cfg.type, cfg.req_ctrl);
> +
> + return dma_request_channel(fdev->dma_device.cap_mask,
> + st_fdma_filter_fn, &cfg);
> +}
> +
> +static void st_fdma_free_desc(struct virt_dma_desc *vdesc)
> +{
> + struct st_fdma_desc *fdesc;
> + int i;
> +
> + fdesc = to_st_fdma_desc(vdesc);
> + for (i = 0; i < fdesc->n_nodes; i++)
> + dma_pool_free(fdesc->fchan->node_pool,
> + fdesc->node[i].desc,
> + fdesc->node[i].pdesc);
> + kfree(fdesc);
> +}
> +
> +static struct st_fdma_desc *st_fdma_alloc_desc(struct st_fdma_chan *fchan,
> + int sg_len)
> +{
> + struct st_fdma_desc *fdesc;
> + int i;
> +
> + fdesc = kzalloc(sizeof(*fdesc) +
> + sizeof(struct st_fdma_sw_node) * sg_len,
> GFP_NOWAIT);
> + if (!fdesc)
> + return NULL;
> +
> + fdesc->fchan = fchan;
> + fdesc->n_nodes = sg_len;
> + for (i = 0; i < sg_len; i++) {
> + fdesc->node[i].desc = dma_pool_alloc(fchan->node_pool,
> + GFP_NOWAIT, &fdesc->node[i].pdesc);
> + if (!fdesc->node[i].desc)
> + goto err;
> + }
> + return fdesc;
> +
> +err:
> + while (--i >= 0)
> + dma_pool_free(fchan->node_pool, fdesc->node[i].desc,
> + fdesc->node[i].pdesc);
> + kfree(fdesc);
> + return NULL;
> +}
> +
> +static int st_fdma_alloc_chan_res(struct dma_chan *chan)
> +{
> + struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
> +
> + if (fchan->cfg.type == ST_FDMA_TYPE_FREE_RUN) {
> + fchan->dreq_line = 0;
> + } else {
> + fchan->dreq_line = st_fdma_dreq_get(fchan);
> + if (IS_ERR_VALUE(fchan->dreq_line))
> + return -EINVAL;
> + }
> +
> + /* Create the dma pool for descriptor allocation */
> + fchan->node_pool = dmam_pool_create(dev_name(&chan->dev-
> >device),
> + fchan->fdev->dev,
> + sizeof(struct st_fdma_hw_node),
> + __alignof__(struct
> st_fdma_hw_node),
> + 0);
> +
> + if (!fchan->node_pool) {
> + dev_err(fchan->fdev->dev, "unable to allocate desc pool\n");
> + return -ENOMEM;
> + }
> +
> + dev_dbg(fchan->fdev->dev, "alloc ch_id:%d type:%d\n",
> + fchan->vchan.chan.chan_id, fchan->cfg.type);
> +
> + return 0;
> +}
> +
> +static void st_fdma_free_chan_res(struct dma_chan *chan)
> +{
> + struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
> + unsigned long flags;
> + LIST_HEAD(head);
> +
> + dev_dbg(fchan->fdev->dev, "freeing chan:%d\n",
> + fchan->vchan.chan.chan_id);
> +
> + if (fchan->cfg.type != ST_FDMA_TYPE_FREE_RUN)
> + st_fdma_dreq_put(fchan);
> +
> + spin_lock_irqsave(&fchan->vchan.lock, flags);
> + fchan->fdesc = NULL;
> + vchan_get_all_descriptors(&fchan->vchan, &head);
> + spin_unlock_irqrestore(&fchan->vchan.lock, flags);
> +
> + dma_pool_destroy(fchan->node_pool);
> + fchan->node_pool = NULL;
> + memset(&fchan->cfg, 0, sizeof(struct st_fdma_cfg));
> +}
> +
> +static struct dma_async_tx_descriptor *st_fdma_prep_dma_memcpy(
> + struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
> + size_t len, unsigned long flags)
> +{
> + struct st_fdma_chan *fchan;
> + struct st_fdma_desc *fdesc;
> + struct st_fdma_hw_node *hw_node;
> +
> + if (!len)
> + return NULL;
> +
> + fchan = to_st_fdma_chan(chan);
> +
> + if (!atomic_read(&fchan->fdev->fw_loaded)) {
> + dev_err(fchan->fdev->dev, "%s: fdma fw not loaded\n",
> __func__);
> + return NULL;
> + }
> +
> + /* We only require a single descriptor */
> + fdesc = st_fdma_alloc_desc(fchan, 1);
> + if (!fdesc) {
> + dev_err(fchan->fdev->dev, "no memory for desc\n");
> + return NULL;
> + }
> +
> + hw_node = fdesc->node[0].desc;
> + hw_node->next = 0;
> + hw_node->control = NODE_CTRL_REQ_MAP_FREE_RUN;
> + hw_node->control |= NODE_CTRL_SRC_INCR;
> + hw_node->control |= NODE_CTRL_DST_INCR;
> + hw_node->control |= NODE_CTRL_INT_EON;
> + hw_node->nbytes = len;
> + hw_node->saddr = src;
> + hw_node->daddr = dst;
> + hw_node->generic.length = len;
> + hw_node->generic.sstride = 0;
> + hw_node->generic.dstride = 0;
> +
> + return vchan_tx_prep(&fchan->vchan, &fdesc->vdesc, flags);
> +}
> +
> +static int config_reqctrl(struct st_fdma_chan *fchan,
> + enum dma_transfer_direction direction)
> +{
> + u32 maxburst = 0, addr = 0;
> + enum dma_slave_buswidth width;
> + int ch_id = fchan->vchan.chan.chan_id;
> + struct st_fdma_dev *fdev = fchan->fdev;
> +
> + if (direction == DMA_DEV_TO_MEM) {
> + fchan->cfg.req_ctrl &= ~REQ_CTRL_WNR;
> + maxburst = fchan->scfg.src_maxburst;
> + width = fchan->scfg.src_addr_width;
> + addr = fchan->scfg.src_addr;
> + } else if (direction == DMA_MEM_TO_DEV) {
> + fchan->cfg.req_ctrl |= REQ_CTRL_WNR;
> + maxburst = fchan->scfg.dst_maxburst;
> + width = fchan->scfg.dst_addr_width;
> + addr = fchan->scfg.dst_addr;
> + } else {
> + return -EINVAL;
> + }
> +
> + fchan->cfg.req_ctrl &= ~REQ_CTRL_OPCODE_MASK;
> + if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
> + fchan->cfg.req_ctrl |= REQ_CTRL_OPCODE_LD_ST1;
> + else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
> + fchan->cfg.req_ctrl |= REQ_CTRL_OPCODE_LD_ST2;
> + else if (width == DMA_SLAVE_BUSWIDTH_4_BYTES)
> + fchan->cfg.req_ctrl |= REQ_CTRL_OPCODE_LD_ST4;
> + else if (width == DMA_SLAVE_BUSWIDTH_8_BYTES)
> + fchan->cfg.req_ctrl |= REQ_CTRL_OPCODE_LD_ST8;
> + else
> + return -EINVAL;
> +
> + fchan->cfg.req_ctrl &= ~REQ_CTRL_NUM_OPS_MASK;
> + fchan->cfg.req_ctrl |= REQ_CTRL_NUM_OPS(maxburst-1);
> + dreq_write(fchan, fchan->cfg.req_ctrl, REQ_CTRL);
> +
> + fchan->cfg.dev_addr = addr;
> + fchan->cfg.dir = direction;
> +
> + dev_dbg(fdev->dev, "chan:%d config_reqctrl:%#x req_ctrl:%#lx\n",
> + ch_id, addr, fchan->cfg.req_ctrl);
> +
> + return 0;
> +}
> +
> +static void fill_hw_node(struct st_fdma_hw_node *hw_node,
> + struct st_fdma_chan *fchan,
> + enum dma_transfer_direction direction)
> +{
> +
> + if (direction == DMA_MEM_TO_DEV) {
> + hw_node->control |= NODE_CTRL_SRC_INCR;
> + hw_node->control |= NODE_CTRL_DST_STATIC;
> + hw_node->daddr = fchan->cfg.dev_addr;
> + } else {
> + hw_node->control |= NODE_CTRL_SRC_STATIC;
> + hw_node->control |= NODE_CTRL_DST_INCR;
> + hw_node->saddr = fchan->cfg.dev_addr;
> + }
> + hw_node->generic.sstride = 0;
> + hw_node->generic.dstride = 0;
> +}
> +
> +static struct dma_async_tx_descriptor *st_fdma_prep_dma_cyclic(
> + struct dma_chan *chan, dma_addr_t buf_addr, size_t len,
> + size_t period_len, enum dma_transfer_direction direction,
> + unsigned long flags)
> +{
> + struct st_fdma_chan *fchan;
> + struct st_fdma_desc *fdesc;
> + int sg_len, i;
> +
> + if (!chan || !len || !period_len)
> + return NULL;
> +
> + fchan = to_st_fdma_chan(chan);
> +
> + if (!atomic_read(&fchan->fdev->fw_loaded)) {
> + dev_err(fchan->fdev->dev, "%s: fdma fw not loaded\n",
> __func__);
> + return NULL;
> + }
> +
> + if (!is_slave_direction(direction)) {
> + dev_err(fchan->fdev->dev, "bad direction?\n");
> + return NULL;
> + }
> +
> + if (config_reqctrl(fchan, direction)) {
> + dev_err(fchan->fdev->dev, "bad width or direction\n");
> + return NULL;
> + }
> +
> + /* the buffer length must be a multiple of period_len */
> + if (len % period_len != 0) {
> + dev_err(fchan->fdev->dev, "len is not multiple of period\n");
> + return NULL;
> + }
> +
> + sg_len = len / period_len;
> + fdesc = st_fdma_alloc_desc(fchan, sg_len);
> + if (!fdesc) {
> + dev_err(fchan->fdev->dev, "no memory for desc\n");
> + return NULL;
> + }
> +
> + fdesc->iscyclic = true;
> +
> + for (i = 0; i < sg_len; i++) {
> + struct st_fdma_hw_node *hw_node = fdesc->node[i].desc;
> +
> + hw_node->next = fdesc->node[(i + 1) % sg_len].pdesc;
> +
> + hw_node->control = NODE_CTRL_REQ_MAP_DREQ(fchan-
> >dreq_line);
> + hw_node->control |= NODE_CTRL_INT_EON;
> +
> +
> + fill_hw_node(hw_node, fchan, direction);
> +
> + if (direction == DMA_MEM_TO_DEV)
> + hw_node->saddr = buf_addr + (i * period_len);
> + else
> + hw_node->daddr = buf_addr + (i * period_len);
> +
> + hw_node->nbytes = period_len;
> + hw_node->generic.length = period_len;
> + }
> +
> + return vchan_tx_prep(&fchan->vchan, &fdesc->vdesc, flags);
> +}
> +
> +static struct dma_async_tx_descriptor *st_fdma_prep_slave_sg(
> + struct dma_chan *chan, struct scatterlist *sgl,
> + unsigned int sg_len, enum dma_transfer_direction direction,
> + unsigned long flags, void *context)
> +{
> + struct st_fdma_chan *fchan;
> + struct st_fdma_desc *fdesc;
> + struct st_fdma_hw_node *hw_node;
> + struct scatterlist *sg;
> + int i;
> +
> + if (!chan || !sgl || !sg_len)
> + return NULL;
> +
> + fchan = to_st_fdma_chan(chan);
> +
> + if (!atomic_read(&fchan->fdev->fw_loaded)) {
> + dev_err(fchan->fdev->dev, "%s: fdma fw not loaded\n",
> __func__);
> + return NULL;
> + }
> +
> + if (!is_slave_direction(direction)) {
> + dev_err(fchan->fdev->dev, "bad direction?\n");
> + return NULL;
> + }
> +
> + fdesc = st_fdma_alloc_desc(fchan, sg_len);
> + if (!fdesc) {
> + dev_err(fchan->fdev->dev, "no memory for desc\n");
> + return NULL;
> + }
> +
> + fdesc->iscyclic = false;
> +
> + for_each_sg(sgl, sg, sg_len, i) {
> + hw_node = fdesc->node[i].desc;
> +
> + hw_node->next = fdesc->node[(i + 1) % sg_len].pdesc;
> + hw_node->control = NODE_CTRL_REQ_MAP_DREQ(fchan-
> >dreq_line);
> +
> + fill_hw_node(hw_node, fchan, direction);
> +
> + if (direction == DMA_MEM_TO_DEV)
> + hw_node->saddr = sg_dma_address(sg);
> + else
> + hw_node->daddr = sg_dma_address(sg);
> +
> + hw_node->nbytes = sg_dma_len(sg);
> + hw_node->generic.length = sg_dma_len(sg);
> + }
> +
> + /* interrupt at end of last node */
> + hw_node->control |= NODE_CTRL_INT_EON;
> +
> + return vchan_tx_prep(&fchan->vchan, &fdesc->vdesc, flags);
> +}
> +
> +static size_t st_fdma_desc_residue(struct st_fdma_chan *fchan,
> + struct virt_dma_desc *vdesc,
> + bool in_progress)
> +{
> + struct st_fdma_desc *fdesc = fchan->fdesc;
> + size_t residue = 0;
> + dma_addr_t cur_addr = 0;
> + int i;
> +
> + if (in_progress) {
> + cur_addr = fchan_read(fchan, CH_CMD);
> + cur_addr &= FDMA_CH_CMD_DATA_MASK;
> + }
> +
> + for (i = fchan->fdesc->n_nodes - 1 ; i >= 0; i--) {
> + if (cur_addr == fdesc->node[i].pdesc) {
> + residue += fnode_read(fchan, CNTN);
> + break;
> + }
> + residue += fdesc->node[i].desc->nbytes;
> + }
> +
> + return residue;
> +}
> +
> +static enum dma_status st_fdma_tx_status(struct dma_chan *chan,
> + dma_cookie_t cookie,
> + struct dma_tx_state *txstate)
> +{
> + struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
> + struct virt_dma_desc *vd;
> + enum dma_status ret;
> + unsigned long flags;
> +
> + ret = dma_cookie_status(chan, cookie, txstate);
> + if (ret == DMA_COMPLETE)
> + return ret;
> +
> + if (!txstate)
> + return fchan->status;
> +
> + spin_lock_irqsave(&fchan->vchan.lock, flags);
> + vd = vchan_find_desc(&fchan->vchan, cookie);
> + if (fchan->fdesc && cookie == fchan->fdesc->vdesc.tx.cookie)
> + txstate->residue = st_fdma_desc_residue(fchan, vd, true);
> + else if (vd)
> + txstate->residue = st_fdma_desc_residue(fchan, vd, false);
> + else
> + txstate->residue = 0;
> +
> + spin_unlock_irqrestore(&fchan->vchan.lock, flags);
> +
> + return fchan->status;
> +}
> +
> +static void st_fdma_issue_pending(struct dma_chan *chan)
> +{
> + struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
> + unsigned long flags;
> +
> + spin_lock_irqsave(&fchan->vchan.lock, flags);
> +
> + if (vchan_issue_pending(&fchan->vchan) && !fchan->fdesc)
> + st_fdma_xfer_desc(fchan);
> +
> + spin_unlock_irqrestore(&fchan->vchan.lock, flags);
> +}
> +
> +static int st_fdma_pause(struct dma_chan *chan)
> +{
> + unsigned long flags;
> + LIST_HEAD(head);
> + struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
> + int ch_id = fchan->vchan.chan.chan_id;
> + unsigned long cmd = FDMA_CMD_PAUSE(ch_id);
> +
> + dev_dbg(fchan->fdev->dev, "pause chan:%d\n", ch_id);
> +
> + spin_lock_irqsave(&fchan->vchan.lock, flags);
> + if (fchan->fdesc)
> + fdma_write(fchan->fdev, cmd, CMD_SET);
> + spin_unlock_irqrestore(&fchan->vchan.lock, flags);
> +
> + return 0;
> +}
> +
> +static int st_fdma_resume(struct dma_chan *chan)
> +{
> + unsigned long flags;
> + unsigned long val;
> + struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
> + int ch_id = fchan->vchan.chan.chan_id;
> +
> + dev_dbg(fchan->fdev->dev, "resume chan:%d\n", ch_id);
> +
> + spin_lock_irqsave(&fchan->vchan.lock, flags);
> + if (fchan->fdesc) {
> + val = fchan_read(fchan, CH_CMD);
> + val &= FDMA_CH_CMD_DATA_MASK;
> + fchan_write(fchan, val, CH_CMD);
> + }
> + spin_unlock_irqrestore(&fchan->vchan.lock, flags);
> +
> + return 0;
> +}
> +
> +static int st_fdma_terminate_all(struct dma_chan *chan)
> +{
> + unsigned long flags;
> + LIST_HEAD(head);
> + struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
> + int ch_id = fchan->vchan.chan.chan_id;
> + unsigned long cmd = FDMA_CMD_PAUSE(ch_id);
> +
> + dev_dbg(fchan->fdev->dev, "terminate chan:%d\n", ch_id);
> +
> + spin_lock_irqsave(&fchan->vchan.lock, flags);
> + fdma_write(fchan->fdev, cmd, CMD_SET);
> + fchan->fdesc = NULL;
> + vchan_get_all_descriptors(&fchan->vchan, &head);
> + spin_unlock_irqrestore(&fchan->vchan.lock, flags);
> + vchan_dma_desc_free_list(&fchan->vchan, &head);
> +
> + return 0;
> +}
> +
> +static int st_fdma_slave_config(struct dma_chan *chan,
> + struct dma_slave_config *slave_cfg)
> +{
> + struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
> + memcpy(&fchan->scfg, slave_cfg, sizeof(fchan->scfg));
> + return 0;
> +}
> +
> +static const struct st_fdma_ram fdma_mpe31_mem[] = {
> + { .name = "dmem", .offset = 0x10000, .size = 0x3000 },
> + { .name = "imem", .offset = 0x18000, .size = 0x8000 },
> +};
> +
> +static const struct st_fdma_driverdata fdma_mpe31_stih407_11 = {
> + .fdma_mem = fdma_mpe31_mem,
> + .num_mem = ARRAY_SIZE(fdma_mpe31_mem),
> + .name = "STiH407",
> + .id = 0,
> +};
> +
> +static const struct st_fdma_driverdata fdma_mpe31_stih407_12 = {
> + .fdma_mem = fdma_mpe31_mem,
> + .num_mem = ARRAY_SIZE(fdma_mpe31_mem),
> + .name = "STiH407",
> + .id = 1,
> +};
> +
> +static const struct st_fdma_driverdata fdma_mpe31_stih407_13 = {
> + .fdma_mem = fdma_mpe31_mem,
> + .num_mem = ARRAY_SIZE(fdma_mpe31_mem),
> + .name = "STiH407",
> + .id = 2,
> +};
> +
> +static const struct of_device_id st_fdma_match[] = {
> + { .compatible = "st,stih407-fdma-mpe31-11"
> + , .data = &fdma_mpe31_stih407_11 },
> + { .compatible = "st,stih407-fdma-mpe31-12"
> + , .data = &fdma_mpe31_stih407_12 },
> + { .compatible = "st,stih407-fdma-mpe31-13"
> + , .data = &fdma_mpe31_stih407_13 },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, st_fdma_match);
> +
> +static int st_fdma_parse_dt(struct platform_device *pdev,
> + const struct st_fdma_driverdata *drvdata,
> + struct st_fdma_dev *fdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + int ret;
> +
> + if (!np)
> + goto err;
> +
> + ret = of_property_read_u32(np, "dma-channels", &fdev->nr_channels);
> + if (ret)
> + goto err;
> +
> + snprintf(fdev->fw_name, FW_NAME_SIZE, "fdma_%s_%d.elf",
> + drvdata->name, drvdata->id);
> +
> +err:
> + return ret;
> +}
> +#define FDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE)
> | \
> + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
> + BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
> + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
> +
> +static int st_fdma_probe(struct platform_device *pdev)
> +{
> + struct st_fdma_dev *fdev;
> + const struct of_device_id *match;
> + struct device_node *np = pdev->dev.of_node;
> + const struct st_fdma_driverdata *drvdata;
> + int irq, ret, i;
> +
> + match = of_match_device((st_fdma_match), &pdev->dev);
> + if (!match || !match->data) {
> + dev_err(&pdev->dev, "No device match found\n");
> + return -ENODEV;
> + }
> +
> + drvdata = match->data;
> +
> + fdev = devm_kzalloc(&pdev->dev, sizeof(*fdev), GFP_KERNEL);
> + if (!fdev)
> + return -ENOMEM;
> +
> + ret = st_fdma_parse_dt(pdev, drvdata, fdev);
> + if (ret) {
> + dev_err(&pdev->dev, "unable to find platform data\n");
> + goto err;
> + }
> +
> + fdev->chans = devm_kzalloc(&pdev->dev,
> + fdev->nr_channels
> + * sizeof(struct st_fdma_chan), GFP_KERNEL);
> + if (!fdev->chans)
> + return -ENOMEM;
> +
> + fdev->dev = &pdev->dev;
> + fdev->drvdata = drvdata;
> + platform_set_drvdata(pdev, fdev);
> +
> + fdev->io_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + fdev->io_base = devm_ioremap_resource(&pdev->dev, fdev->io_res);
> + if (IS_ERR(fdev->io_base))
> + return PTR_ERR(fdev->io_base);
> +
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0) {
> + dev_err(&pdev->dev, "Failed to get irq resource\n");
> + return -EINVAL;
> + }
> +
> + ret = devm_request_irq(&pdev->dev, irq, st_fdma_irq_handler, 0,
> + dev_name(&pdev->dev), fdev);
> + if (ret) {
> + dev_err(&pdev->dev, "Failed to request irq\n");
> + goto err;
> + }
> +
> + ret = st_fdma_clk_get(fdev);
> + if (ret)
> + goto err;
> +
> + ret = st_fdma_clk_enable(fdev);
> + if (ret) {
> + dev_err(&pdev->dev, "Failed to enable clocks\n");
> + goto err_clk;
> + }
> +
> + /* Initialise list of FDMA channels */
> + INIT_LIST_HEAD(&fdev->dma_device.channels);
> + for (i = 0; i < fdev->nr_channels; i++) {
> + struct st_fdma_chan *fchan = &fdev->chans[i];
> +
> + fchan->fdev = fdev;
> + fchan->vchan.desc_free = st_fdma_free_desc;
> + vchan_init(&fchan->vchan, &fdev->dma_device);
> + }
> +
> + /* Initialise the FDMA dreq (reserve 0 & 31 for FDMA use) */
> + fdev->dreq_mask = BIT(0) | BIT(31);
> +
> + dma_cap_set(DMA_SLAVE, fdev->dma_device.cap_mask);
> + dma_cap_set(DMA_CYCLIC, fdev->dma_device.cap_mask);
> + dma_cap_set(DMA_MEMCPY, fdev->dma_device.cap_mask);
> +
> + fdev->dma_device.dev = &pdev->dev;
> + fdev->dma_device.device_alloc_chan_resources =
> st_fdma_alloc_chan_res;
> + fdev->dma_device.device_free_chan_resources =
> st_fdma_free_chan_res;
> + fdev->dma_device.device_prep_dma_cyclic =
> st_fdma_prep_dma_cyclic;
> + fdev->dma_device.device_prep_slave_sg = st_fdma_prep_slave_sg;
> + fdev->dma_device.device_prep_dma_memcpy =
> st_fdma_prep_dma_memcpy;
> + fdev->dma_device.device_tx_status = st_fdma_tx_status;
> + fdev->dma_device.device_issue_pending = st_fdma_issue_pending;
> + fdev->dma_device.device_terminate_all = st_fdma_terminate_all;
> + fdev->dma_device.device_config = st_fdma_slave_config;
> + fdev->dma_device.device_pause = st_fdma_pause;
> + fdev->dma_device.device_resume = st_fdma_resume;
> +
> + fdev->dma_device.src_addr_widths = FDMA_DMA_BUSWIDTHS;
> + fdev->dma_device.dst_addr_widths = FDMA_DMA_BUSWIDTHS;
> + fdev->dma_device.directions = BIT(DMA_DEV_TO_MEM) |
> BIT(DMA_MEM_TO_DEV);
> + fdev->dma_device.residue_granularity =
> DMA_RESIDUE_GRANULARITY_BURST;
> +
> + ret = dma_async_device_register(&fdev->dma_device);
> + if (ret) {
> + dev_err(&pdev->dev, "Failed to register DMA device\n");
> + goto err_clk;
> + }
> +
> + ret = of_dma_controller_register(np, st_fdma_of_xlate, fdev);
> + if (ret) {
> + dev_err(&pdev->dev, "Failed to register controller\n");
> + goto err_dma_dev;
> + }
> +
> + dev_info(&pdev->dev, "ST FDMA engine driver, irq:%d\n", irq);
> +
> + return 0;
> +
> +err_dma_dev:
> + dma_async_device_unregister(&fdev->dma_device);
> +err_clk:
> + st_fdma_clk_disable(fdev);
> +err:
> + return ret;
> +}
> +
> +static int st_fdma_remove(struct platform_device *pdev)
> +{
> + struct st_fdma_dev *fdev = platform_get_drvdata(pdev);
> +
> + st_fdma_clk_disable(fdev);
> +
> + return 0;
> +}
> +
> +static struct platform_driver st_fdma_platform_driver = {
> + .driver = {
> + .name = "st-fdma",
> + .of_match_table = st_fdma_match,
> + },
> + .probe = st_fdma_probe,
> + .remove = st_fdma_remove,
> +};
> +module_platform_driver(st_fdma_platform_driver);
> +
> +bool st_fdma_filter_fn(struct dma_chan *chan, void *param)
> +{
> + struct st_fdma_cfg *config = param;
> + struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
> +
> + if (!param)
> + return false;
> +
> + if (fchan->fdev->dma_device.dev->of_node != config->of_node)
> + return false;
> +
> + fchan->cfg = *config;
> +
> + return true;
> +}
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("STMicroelectronics FDMA engine driver");
> +MODULE_AUTHOR("Ludovic.barre <Ludovic.barre@st.com>");
> --
> 1.9.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe dmaengine" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 53+ messages in thread* Re: [PATCH 03/18] dmaengine: st_fdma: Add STMicroelectronics FDMA engine driver support
2016-04-21 11:04 ` [PATCH 03/18] dmaengine: st_fdma: Add STMicroelectronics FDMA engine driver support Peter Griffin
2016-04-21 11:24 ` Arnd Bergmann
2016-04-21 11:26 ` Appana Durga Kedareswara Rao
@ 2016-04-26 16:56 ` Vinod Koul
2016-04-27 12:59 ` Peter Griffin
2 siblings, 1 reply; 53+ messages in thread
From: Vinod Koul @ 2016-04-26 16:56 UTC (permalink / raw)
To: Peter Griffin
Cc: linux-arm-kernel, linux-kernel, srinivas.kandagatla,
maxime.coquelin, patrice.chotard, lee.jones, dmaengine,
devicetree, arnd, broonie, ludovic.barre
On Thu, Apr 21, 2016 at 12:04:20PM +0100, Peter Griffin wrote:
> + if (!atomic_read(&fchan->fdev->fw_loaded)) {
> + dev_err(fchan->fdev->dev, "%s: fdma fw not loaded\n", __func__);
> + return NULL;
> + }
so who is loading the fw and setting fw_loaded, it is not set in this patch?
> + if (direction == DMA_DEV_TO_MEM) {
> + fchan->cfg.req_ctrl &= ~REQ_CTRL_WNR;
> + maxburst = fchan->scfg.src_maxburst;
> + width = fchan->scfg.src_addr_width;
> + addr = fchan->scfg.src_addr;
> + } else if (direction == DMA_MEM_TO_DEV) {
> + fchan->cfg.req_ctrl |= REQ_CTRL_WNR;
> + maxburst = fchan->scfg.dst_maxburst;
> + width = fchan->scfg.dst_addr_width;
> + addr = fchan->scfg.dst_addr;
> + } else {
> + return -EINVAL;
> + }
switch please
> +
> + fchan->cfg.req_ctrl &= ~REQ_CTRL_OPCODE_MASK;
> + if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
> + fchan->cfg.req_ctrl |= REQ_CTRL_OPCODE_LD_ST1;
> + else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
> + fchan->cfg.req_ctrl |= REQ_CTRL_OPCODE_LD_ST2;
> + else if (width == DMA_SLAVE_BUSWIDTH_4_BYTES)
> + fchan->cfg.req_ctrl |= REQ_CTRL_OPCODE_LD_ST4;
> + else if (width == DMA_SLAVE_BUSWIDTH_8_BYTES)
> + fchan->cfg.req_ctrl |= REQ_CTRL_OPCODE_LD_ST8;
> + else
> + return -EINVAL;
here as well
> +static void fill_hw_node(struct st_fdma_hw_node *hw_node,
> + struct st_fdma_chan *fchan,
> + enum dma_transfer_direction direction)
> +{
> +
> + if (direction == DMA_MEM_TO_DEV) {
> + hw_node->control |= NODE_CTRL_SRC_INCR;
> + hw_node->control |= NODE_CTRL_DST_STATIC;
> + hw_node->daddr = fchan->cfg.dev_addr;
> + } else {
> + hw_node->control |= NODE_CTRL_SRC_STATIC;
> + hw_node->control |= NODE_CTRL_DST_INCR;
> + hw_node->saddr = fchan->cfg.dev_addr;
> + }
empty line here at other places too. The code looks very compressed and bit
harder to read overall
> + fdesc = st_fdma_alloc_desc(fchan, sg_len);
> + if (!fdesc) {
> + dev_err(fchan->fdev->dev, "no memory for desc\n");
> + return NULL;
> + }
> +
> + fdesc->iscyclic = false;
> +
> + for_each_sg(sgl, sg, sg_len, i) {
> + hw_node = fdesc->node[i].desc;
> +
> + hw_node->next = fdesc->node[(i + 1) % sg_len].pdesc;
> + hw_node->control = NODE_CTRL_REQ_MAP_DREQ(fchan->dreq_line);
> +
> + fill_hw_node(hw_node, fchan, direction);
> +
> + if (direction == DMA_MEM_TO_DEV)
> + hw_node->saddr = sg_dma_address(sg);
> + else
> + hw_node->daddr = sg_dma_address(sg);
> +
> + hw_node->nbytes = sg_dma_len(sg);
> + hw_node->generic.length = sg_dma_len(sg);
> + }
> +
> + /* interrupt at end of last node */
> + hw_node->control |= NODE_CTRL_INT_EON;
> +
> + return vchan_tx_prep(&fchan->vchan, &fdesc->vdesc, flags);
bunch of this seems similar to cyclic case, can you create common setup
routine for these, anyway cyclic is a special cases of slave_sg
> +
> + ret = dma_cookie_status(chan, cookie, txstate);
> + if (ret == DMA_COMPLETE)
> + return ret;
> +
> + if (!txstate)
> + return fchan->status;
why channel status, query is for descriptor
> +static int st_fdma_remove(struct platform_device *pdev)
> +{
> + struct st_fdma_dev *fdev = platform_get_drvdata(pdev);
> +
> + st_fdma_clk_disable(fdev);
and you irq is still enabled and tasklets can be scheduled!!
--
~Vinod
^ permalink raw reply [flat|nested] 53+ messages in thread* Re: [PATCH 03/18] dmaengine: st_fdma: Add STMicroelectronics FDMA engine driver support
2016-04-26 16:56 ` Vinod Koul
@ 2016-04-27 12:59 ` Peter Griffin
2016-05-02 9:30 ` Vinod Koul
0 siblings, 1 reply; 53+ messages in thread
From: Peter Griffin @ 2016-04-27 12:59 UTC (permalink / raw)
To: Vinod Koul
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
srinivas.kandagatla-Re5JQEeQqe8AvxtiuMwx3w,
maxime.coquelin-qxv4g6HH51o, patrice.chotard-qxv4g6HH51o,
lee.jones-QSEj5FYQhm4dnm+yROfE0A,
dmaengine-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
broonie-DgEjT+Ai2ygdnm+yROfE0A, ludovic.barre-qxv4g6HH51o
Hi Vinod,
Thanks for reviewing.
On Tue, 26 Apr 2016, Vinod Koul wrote:
> On Thu, Apr 21, 2016 at 12:04:20PM +0100, Peter Griffin wrote:
>
> > + if (!atomic_read(&fchan->fdev->fw_loaded)) {
> > + dev_err(fchan->fdev->dev, "%s: fdma fw not loaded\n", __func__);
> > + return NULL;
> > + }
>
> so who is loading the fw and setting fw_loaded, it is not set in this patch?
This shouldn't be in this patch. It should have been added as part of the
"dmaengine: st_fdma: Add xp70 firmware loading mechanism" patch.
>
> > + if (direction == DMA_DEV_TO_MEM) {
> > + fchan->cfg.req_ctrl &= ~REQ_CTRL_WNR;
> > + maxburst = fchan->scfg.src_maxburst;
> > + width = fchan->scfg.src_addr_width;
> > + addr = fchan->scfg.src_addr;
> > + } else if (direction == DMA_MEM_TO_DEV) {
> > + fchan->cfg.req_ctrl |= REQ_CTRL_WNR;
> > + maxburst = fchan->scfg.dst_maxburst;
> > + width = fchan->scfg.dst_addr_width;
> > + addr = fchan->scfg.dst_addr;
> > + } else {
> > + return -EINVAL;
> > + }
>
> switch please
Ok, will fix in v4
>
> > +
> > + fchan->cfg.req_ctrl &= ~REQ_CTRL_OPCODE_MASK;
> > + if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
> > + fchan->cfg.req_ctrl |= REQ_CTRL_OPCODE_LD_ST1;
> > + else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
> > + fchan->cfg.req_ctrl |= REQ_CTRL_OPCODE_LD_ST2;
> > + else if (width == DMA_SLAVE_BUSWIDTH_4_BYTES)
> > + fchan->cfg.req_ctrl |= REQ_CTRL_OPCODE_LD_ST4;
> > + else if (width == DMA_SLAVE_BUSWIDTH_8_BYTES)
> > + fchan->cfg.req_ctrl |= REQ_CTRL_OPCODE_LD_ST8;
> > + else
> > + return -EINVAL;
>
> here as well
Ok, will fix in v4.
>
> > +static void fill_hw_node(struct st_fdma_hw_node *hw_node,
> > + struct st_fdma_chan *fchan,
> > + enum dma_transfer_direction direction)
> > +{
> > +
> > + if (direction == DMA_MEM_TO_DEV) {
> > + hw_node->control |= NODE_CTRL_SRC_INCR;
> > + hw_node->control |= NODE_CTRL_DST_STATIC;
> > + hw_node->daddr = fchan->cfg.dev_addr;
> > + } else {
> > + hw_node->control |= NODE_CTRL_SRC_STATIC;
> > + hw_node->control |= NODE_CTRL_DST_INCR;
> > + hw_node->saddr = fchan->cfg.dev_addr;
> > + }
>
> empty line here at other places too. The code looks very compressed and bit
> harder to read overall
Ok, will fix in v4.
>
> > + fdesc = st_fdma_alloc_desc(fchan, sg_len);
> > + if (!fdesc) {
> > + dev_err(fchan->fdev->dev, "no memory for desc\n");
> > + return NULL;
> > + }
> > +
> > + fdesc->iscyclic = false;
> > +
> > + for_each_sg(sgl, sg, sg_len, i) {
> > + hw_node = fdesc->node[i].desc;
> > +
> > + hw_node->next = fdesc->node[(i + 1) % sg_len].pdesc;
> > + hw_node->control = NODE_CTRL_REQ_MAP_DREQ(fchan->dreq_line);
> > +
> > + fill_hw_node(hw_node, fchan, direction);
> > +
> > + if (direction == DMA_MEM_TO_DEV)
> > + hw_node->saddr = sg_dma_address(sg);
> > + else
> > + hw_node->daddr = sg_dma_address(sg);
> > +
> > + hw_node->nbytes = sg_dma_len(sg);
> > + hw_node->generic.length = sg_dma_len(sg);
> > + }
> > +
> > + /* interrupt at end of last node */
> > + hw_node->control |= NODE_CTRL_INT_EON;
> > +
> > + return vchan_tx_prep(&fchan->vchan, &fdesc->vdesc, flags);
>
> bunch of this seems similar to cyclic case, can you create common setup
> routine for these, anyway cyclic is a special cases of slave_sg
In v4 I've made a st_fdma_prep_common() which abstracts out all the common
checks at the beginning of the *_prep*() functions.
In v3 fill_fw_node() is already (from one of your previous reviews)
abstracting out all the common parts from these loops. So everything
that is now left is actually differences between the two setups.
Is that Ok?
>
> > +
> > + ret = dma_cookie_status(chan, cookie, txstate);
> > + if (ret == DMA_COMPLETE)
> > + return ret;
> > +
> > + if (!txstate)
> > + return fchan->status;
>
> why channel status, query is for descriptor
Ok, will fix in v4.
>
> > +static int st_fdma_remove(struct platform_device *pdev)
> > +{
> > + struct st_fdma_dev *fdev = platform_get_drvdata(pdev);
> > +
> > + st_fdma_clk_disable(fdev);
>
> and you irq is still enabled and tasklets can be scheduled!!
>
Eeek! Very good point. Also looking at some other drivers we
should be doing a of_dma_controller_free() and
dma_async_device_unregister().
So something like this: -
st_fdma_disable(); /*disables irqs*/
of_dma_controller_free(pdev->dev.of_node);
dma_async_device_unregister(&priv->slave);
st_fdma_clk_disable(fdev);
regards,
Peter.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 53+ messages in thread* Re: [PATCH 03/18] dmaengine: st_fdma: Add STMicroelectronics FDMA engine driver support
2016-04-27 12:59 ` Peter Griffin
@ 2016-05-02 9:30 ` Vinod Koul
2016-05-09 17:30 ` Peter Griffin
0 siblings, 1 reply; 53+ messages in thread
From: Vinod Koul @ 2016-05-02 9:30 UTC (permalink / raw)
To: Peter Griffin
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
srinivas.kandagatla-Re5JQEeQqe8AvxtiuMwx3w,
maxime.coquelin-qxv4g6HH51o, patrice.chotard-qxv4g6HH51o,
lee.jones-QSEj5FYQhm4dnm+yROfE0A,
dmaengine-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
broonie-DgEjT+Ai2ygdnm+yROfE0A, ludovic.barre-qxv4g6HH51o
On Wed, Apr 27, 2016 at 01:59:23PM +0100, Peter Griffin wrote:
> > bunch of this seems similar to cyclic case, can you create common setup
> > routine for these, anyway cyclic is a special cases of slave_sg
>
> In v4 I've made a st_fdma_prep_common() which abstracts out all the common
> checks at the beginning of the *_prep*() functions.
>
> In v3 fill_fw_node() is already (from one of your previous reviews)
> abstracting out all the common parts from these loops. So everything
> that is now left is actually differences between the two setups.
>
> Is that Ok?
Sounds better
> > and you irq is still enabled and tasklets can be scheduled!!
> >
> Eeek! Very good point. Also looking at some other drivers we
> should be doing a of_dma_controller_free() and
> dma_async_device_unregister().
>
> So something like this: -
>
> st_fdma_disable(); /*disables irqs*/
> of_dma_controller_free(pdev->dev.of_node);
> dma_async_device_unregister(&priv->slave);
> st_fdma_clk_disable(fdev);
you can call devm_free_irq() explictyly, that will syncronize irq and
free it up. Also you should kill the tasklet afterwards.
--
~Vinod
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 03/18] dmaengine: st_fdma: Add STMicroelectronics FDMA engine driver support
2016-05-02 9:30 ` Vinod Koul
@ 2016-05-09 17:30 ` Peter Griffin
0 siblings, 0 replies; 53+ messages in thread
From: Peter Griffin @ 2016-05-09 17:30 UTC (permalink / raw)
To: Vinod Koul
Cc: devicetree, arnd, srinivas.kandagatla, patrice.chotard,
linux-kernel, broonie, ludovic.barre, dmaengine, lee.jones,
linux-arm-kernel, maxime.coquelin
Hi Vinod,
On Mon, 02 May 2016, Vinod Koul wrote:
> On Wed, Apr 27, 2016 at 01:59:23PM +0100, Peter Griffin wrote:
> > > bunch of this seems similar to cyclic case, can you create common setup
> > > routine for these, anyway cyclic is a special cases of slave_sg
> >
> > In v4 I've made a st_fdma_prep_common() which abstracts out all the common
> > checks at the beginning of the *_prep*() functions.
> >
> > In v3 fill_fw_node() is already (from one of your previous reviews)
> > abstracting out all the common parts from these loops. So everything
> > that is now left is actually differences between the two setups.
> >
> > Is that Ok?
>
> Sounds better
>
> > > and you irq is still enabled and tasklets can be scheduled!!
> > >
> > Eeek! Very good point. Also looking at some other drivers we
> > should be doing a of_dma_controller_free() and
> > dma_async_device_unregister().
> >
> > So something like this: -
> >
> > st_fdma_disable(); /*disables irqs*/
> > of_dma_controller_free(pdev->dev.of_node);
> > dma_async_device_unregister(&priv->slave);
> > st_fdma_clk_disable(fdev);
>
> you can call devm_free_irq() explictyly, that will syncronize irq and
> free it up.
Ok will do/
> Also you should kill the tasklet afterwards.
>
We aren't using a tasklet in this driver.
Peter.
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH 04/18] dmaengine: st_fdma: Add xp70 firmware loading mechanism.
2016-04-21 11:04 [PATCH 00/18] Add support for FDMA DMA controller found on STi chipsets Peter Griffin
` (2 preceding siblings ...)
2016-04-21 11:04 ` [PATCH 03/18] dmaengine: st_fdma: Add STMicroelectronics FDMA engine driver support Peter Griffin
@ 2016-04-21 11:04 ` Peter Griffin
[not found] ` <1461236675-10176-5-git-send-email-peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2016-04-21 11:04 ` [PATCH 05/18] dmaengine: st_fdma: Add fdma suspend and resume callbacks Peter Griffin
` (13 subsequent siblings)
17 siblings, 1 reply; 53+ messages in thread
From: Peter Griffin @ 2016-04-21 11:04 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, srinivas.kandagatla,
maxime.coquelin, patrice.chotard, vinod.koul
Cc: devicetree, arnd, peter.griffin, broonie, dmaengine, lee.jones,
ludovic.barre
This patch adds the code to load the xp70 fdma firmware
using the asynchronous request_firmware_nowait call
so as not to delay bootup of builtin code.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/dma/st_fdma.c | 196 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 196 insertions(+)
diff --git a/drivers/dma/st_fdma.c b/drivers/dma/st_fdma.c
index 9bf0100..5fcaf10 100644
--- a/drivers/dma/st_fdma.c
+++ b/drivers/dma/st_fdma.c
@@ -83,6 +83,162 @@ static struct st_fdma_desc *to_st_fdma_desc(struct virt_dma_desc *vd)
return container_of(vd, struct st_fdma_desc, vdesc);
}
+static void *st_fdma_seg_to_mem(struct st_fdma_dev *fdev, u64 da, int len)
+{
+ int i;
+ resource_size_t base = fdev->io_res->start;
+ const struct st_fdma_ram *fdma_mem = fdev->drvdata->fdma_mem;
+ void *ptr = NULL;
+
+ for (i = 0; i < fdev->drvdata->num_mem; i++) {
+ int mem_off = da - (base + fdma_mem[i].offset);
+
+ /* next mem if da is too small */
+ if (mem_off < 0)
+ continue;
+
+ /* next mem if da is too large */
+ if (mem_off + len > fdma_mem[i].size)
+ continue;
+
+ ptr = fdev->io_base + fdma_mem[i].offset + mem_off;
+ break;
+ }
+
+ return ptr;
+}
+
+static int
+st_fdma_elf_sanity_check(struct st_fdma_dev *fdev, const struct firmware *fw)
+{
+ const char *fw_name = fdev->fw_name;
+ struct elf32_hdr *ehdr;
+ char class;
+
+ if (!fw) {
+ dev_err(fdev->dev, "failed to load %s\n", fw_name);
+ return -EINVAL;
+ }
+
+ if (fw->size < sizeof(*ehdr)) {
+ dev_err(fdev->dev, "Image is too small\n");
+ return -EINVAL;
+ }
+
+ ehdr = (struct elf32_hdr *)fw->data;
+
+ /* We only support ELF32 at this point */
+ class = ehdr->e_ident[EI_CLASS];
+ if (class != ELFCLASS32) {
+ dev_err(fdev->dev, "Unsupported class: %d\n", class);
+ return -EINVAL;
+ }
+
+ if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB) {
+ dev_err(fdev->dev, "Unsupported firmware endianness"
+ "(%d) expected (%d)\n", ehdr->e_ident[EI_DATA],
+ ELFDATA2LSB);
+ return -EINVAL;
+ }
+
+ if (fw->size < ehdr->e_shoff + sizeof(struct elf32_shdr)) {
+ dev_err(fdev->dev, "Image is too small (%u)\n", fw->size);
+ return -EINVAL;
+ }
+
+ if (memcmp(ehdr->e_ident, ELFMAG, SELFMAG)) {
+ dev_err(fdev->dev, "Image is corrupted (bad magic)\n");
+ return -EINVAL;
+ }
+
+ if (ehdr->e_phnum != fdev->drvdata->num_mem) {
+ dev_err(fdev->dev, "spurious nb of segments (%d) expected (%d)"
+ "\n", ehdr->e_phnum, fdev->drvdata->num_mem);
+ return -EINVAL;
+ }
+
+ if (ehdr->e_type != ET_EXEC) {
+ dev_err(fdev->dev, "Unsupported ELF header type (%d) expected"
+ " (%d)\n", ehdr->e_type, ET_EXEC);
+ return -EINVAL;
+ }
+
+ if (ehdr->e_machine != EM_SLIM) {
+ dev_err(fdev->dev, "Unsupported ELF header machine (%d) "
+ "expected (%d)\n", ehdr->e_machine, EM_SLIM);
+ return -EINVAL;
+ }
+ if (ehdr->e_phoff > fw->size) {
+ dev_err(fdev->dev, "Firmware size is too small\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int
+st_fdma_elf_load_segments(struct st_fdma_dev *fdev, const struct firmware *fw)
+{
+ struct device *dev = fdev->dev;
+ struct elf32_hdr *ehdr;
+ struct elf32_phdr *phdr;
+ int i, mem_loaded = 0;
+ const u8 *elf_data = fw->data;
+
+ ehdr = (struct elf32_hdr *)elf_data;
+ phdr = (struct elf32_phdr *)(elf_data + ehdr->e_phoff);
+
+ /*
+ * go through the available ELF segments
+ * the program header's paddr member to contain device addresses.
+ * We then go through the physically contiguous memory regions which we
+ * allocated (and mapped) earlier on the probe,
+ * and "translate" device address to kernel addresses,
+ * so we can copy the segments where they are expected.
+ */
+ for (i = 0; i < ehdr->e_phnum; i++, phdr++) {
+ u32 da = phdr->p_paddr;
+ u32 memsz = phdr->p_memsz;
+ u32 filesz = phdr->p_filesz;
+ u32 offset = phdr->p_offset;
+ void *dst;
+
+ if (phdr->p_type != PT_LOAD)
+ continue;
+
+ dev_dbg(dev, "phdr: type %d da %#x ofst:%#x memsz %#x filesz %#x\n",
+ phdr->p_type, da, offset, memsz, filesz);
+
+ if (filesz > memsz) {
+ dev_err(dev, "bad phdr filesz 0x%x memsz 0x%x\n",
+ filesz, memsz);
+ break;
+ }
+
+ if (offset + filesz > fw->size) {
+ dev_err(dev, "truncated fw: need 0x%x avail 0x%zx\n",
+ offset + filesz, fw->size);
+ break;
+ }
+
+ dst = st_fdma_seg_to_mem(fdev, da, memsz);
+ if (!dst) {
+ dev_err(dev, "bad phdr da 0x%x mem 0x%x\n", da, memsz);
+ break;
+ }
+
+ if (phdr->p_filesz)
+ memcpy(dst, elf_data + phdr->p_offset, filesz);
+
+ if (memsz > filesz)
+ memset(dst + filesz, 0, memsz - filesz);
+
+ mem_loaded++;
+ }
+
+ return (mem_loaded != fdev->drvdata->num_mem) ? -EIO : 0;
+}
+
static void st_fdma_enable(struct st_fdma_dev *fdev)
{
unsigned long hw_id, hw_ver, fw_rev;
@@ -125,6 +281,37 @@ static int st_fdma_disable(struct st_fdma_dev *fdev)
return readl(fdev->io_base + FDMA_EN_OFST);
}
+static int st_fdma_get_fw(struct st_fdma_dev *fdev)
+{
+ const struct firmware *fw;
+ int ret;
+
+ atomic_set(&fdev->fw_loaded, 0);
+
+ dev_info(fdev->dev, "Loading firmware: %s\n", fdev->fw_name);
+
+ ret = request_firmware(&fw, fdev->fw_name, fdev->dev);
+ if (ret) {
+ dev_err(fdev->dev, "request_firmware err: %d\n", ret);
+ return ret;
+ }
+
+ ret = st_fdma_elf_sanity_check(fdev, fw);
+ if (ret)
+ goto out;
+
+ st_fdma_disable(fdev);
+ ret = st_fdma_elf_load_segments(fdev, fw);
+ if (ret)
+ goto out;
+
+ st_fdma_enable(fdev);
+ atomic_set(&fdev->fw_loaded, 1);
+out:
+ release_firmware(fw);
+ return ret;
+}
+
static int st_fdma_dreq_get(struct st_fdma_chan *fchan)
{
struct st_fdma_dev *fdev = fchan->fdev;
@@ -738,6 +925,15 @@ static int st_fdma_slave_config(struct dma_chan *chan,
struct dma_slave_config *slave_cfg)
{
struct st_fdma_chan *fchan = to_st_fdma_chan(chan);
+ int ret;
+
+ if (!atomic_read(&fchan->fdev->fw_loaded)) {
+ ret = st_fdma_get_fw(fchan->fdev);
+ if (ret)
+ dev_err(fchan->fdev->dev, "%s: fdma fw load failed\n"
+ , __func__);
+ }
+
memcpy(&fchan->scfg, slave_cfg, sizeof(fchan->scfg));
return 0;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 05/18] dmaengine: st_fdma: Add fdma suspend and resume callbacks.
2016-04-21 11:04 [PATCH 00/18] Add support for FDMA DMA controller found on STi chipsets Peter Griffin
` (3 preceding siblings ...)
2016-04-21 11:04 ` [PATCH 04/18] dmaengine: st_fdma: Add xp70 firmware loading mechanism Peter Griffin
@ 2016-04-21 11:04 ` Peter Griffin
2016-04-21 11:04 ` [PATCH 06/18] ARM: STi: DT: STiH407: Add FDMA driver dt nodes Peter Griffin
` (12 subsequent siblings)
17 siblings, 0 replies; 53+ messages in thread
From: Peter Griffin @ 2016-04-21 11:04 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, srinivas.kandagatla,
maxime.coquelin, patrice.chotard, vinod.koul
Cc: peter.griffin, lee.jones, dmaengine, devicetree, arnd, broonie,
ludovic.barre
This patch adds the functions to gate the xp70 clock on
suspend and resume.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/dma/st_fdma.c | 41 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/drivers/dma/st_fdma.c b/drivers/dma/st_fdma.c
index 5fcaf10..48a66c9 100644
--- a/drivers/dma/st_fdma.c
+++ b/drivers/dma/st_fdma.c
@@ -1132,10 +1132,51 @@ static int st_fdma_remove(struct platform_device *pdev)
return 0;
}
+#ifdef CONFIG_PM_SLEEP
+static int st_fdma_pm_suspend(struct device *dev)
+{
+ struct st_fdma_dev *fdev = dev_get_drvdata(dev);
+ int ret;
+
+ if (atomic_read(&fdev->fw_loaded)) {
+ ret = st_fdma_disable(fdev);
+ if (ret & FDMA_EN_RUN) {
+ dev_warn(fdev->dev, "Failed to disable channels");
+ return -EBUSY;
+ }
+ }
+
+ st_fdma_clk_disable(fdev);
+
+ return 0;
+}
+
+static int st_fdma_pm_resume(struct device *dev)
+{
+ struct st_fdma_dev *fdev = dev_get_drvdata(dev);
+ int ret;
+
+ ret = st_fdma_clk_enable(fdev);
+ if (ret) {
+ dev_err(fdev->dev, "Failed to enable clocks\n");
+ goto out;
+ }
+
+ ret = st_fdma_get_fw(fdev);
+out:
+ return ret;
+}
+#endif
+
+static const struct dev_pm_ops st_fdma_pm = {
+ SET_RUNTIME_PM_OPS(st_fdma_pm_suspend, st_fdma_pm_resume, NULL)
+};
+
static struct platform_driver st_fdma_platform_driver = {
.driver = {
.name = "st-fdma",
.of_match_table = st_fdma_match,
+ .pm = &st_fdma_pm,
},
.probe = st_fdma_probe,
.remove = st_fdma_remove,
--
1.9.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 06/18] ARM: STi: DT: STiH407: Add FDMA driver dt nodes.
2016-04-21 11:04 [PATCH 00/18] Add support for FDMA DMA controller found on STi chipsets Peter Griffin
` (4 preceding siblings ...)
2016-04-21 11:04 ` [PATCH 05/18] dmaengine: st_fdma: Add fdma suspend and resume callbacks Peter Griffin
@ 2016-04-21 11:04 ` Peter Griffin
[not found] ` <1461236675-10176-1-git-send-email-peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
` (11 subsequent siblings)
17 siblings, 0 replies; 53+ messages in thread
From: Peter Griffin @ 2016-04-21 11:04 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, srinivas.kandagatla,
maxime.coquelin, patrice.chotard, vinod.koul
Cc: devicetree, arnd, peter.griffin, broonie, dmaengine, lee.jones,
ludovic.barre
These nodes are required to get the fdma driver working
on STiH407 based silicon.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm/boot/dts/stih407-family.dtsi | 51 +++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 81f8121..a77008f 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -694,5 +694,56 @@
clocks = <&clk_sysin>;
status = "okay";
};
+
+ /* fdma audio */
+ fdma0: dma-controller@8e20000 {
+ compatible = "st,stih407-fdma-mpe31-11";
+ reg = <0x8e20000 0x20000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>;
+ dma-channels = <16>;
+ #dma-cells = <3>;
+ clocks = <&clk_s_c0_flexgen CLK_FDMA>,
+ <&clk_s_c0_flexgen CLK_EXT2F_A9>,
+ <&clk_s_c0_flexgen CLK_EXT2F_A9>,
+ <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "fdma_slim",
+ "fdma_hi",
+ "fdma_low",
+ "fdma_ic";
+ };
+
+ /* fdma app */
+ fdma1: dma-controller@8e40000 {
+ compatible = "st,stih407-fdma-mpe31-12";
+ reg = <0x8e40000 0x20000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>;
+ dma-channels = <16>;
+ #dma-cells = <3>;
+ clocks = <&clk_s_c0_flexgen CLK_FDMA>,
+ <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
+ <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
+ <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "fdma_slim",
+ "fdma_hi",
+ "fdma_low",
+ "fdma_ic";
+ };
+
+ /* fdma free running */
+ fdma2: dma-controller@8e60000 {
+ compatible = "st,stih407-fdma-mpe31-13";
+ reg = <0x8e60000 0x20000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_NONE>;
+ dma-channels = <16>;
+ #dma-cells = <3>;
+ clocks = <&clk_s_c0_flexgen CLK_FDMA>,
+ <&clk_s_c0_flexgen CLK_EXT2F_A9>,
+ <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
+ <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "fdma_slim",
+ "fdma_hi",
+ "fdma_low",
+ "fdma_ic";
+ };
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 53+ messages in thread[parent not found: <1461236675-10176-1-git-send-email-peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>]
* [PATCH 07/18] MAINTAINERS: Add FDMA driver files to STi section.
[not found] ` <1461236675-10176-1-git-send-email-peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
@ 2016-04-21 11:04 ` Peter Griffin
0 siblings, 0 replies; 53+ messages in thread
From: Peter Griffin @ 2016-04-21 11:04 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
srinivas.kandagatla-Re5JQEeQqe8AvxtiuMwx3w,
maxime.coquelin-qxv4g6HH51o, patrice.chotard-qxv4g6HH51o,
vinod.koul-ral2JQCrhuEAvxtiuMwx3w
Cc: peter.griffin-QSEj5FYQhm4dnm+yROfE0A,
lee.jones-QSEj5FYQhm4dnm+yROfE0A,
dmaengine-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
broonie-DgEjT+Ai2ygdnm+yROfE0A, ludovic.barre-qxv4g6HH51o
This patch adds the FDMA driver files to the STi
section of the maintainers file.
Signed-off-by: Peter Griffin <peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Acked-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 61a323a..c65d986 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1638,6 +1638,7 @@ F: arch/arm/boot/dts/sti*
F: drivers/char/hw_random/st-rng.c
F: drivers/clocksource/arm_global_timer.c
F: drivers/clocksource/clksrc_st_lpc.c
+F: drivers/dma/st_fdma*
F: drivers/i2c/busses/i2c-st.c
F: drivers/media/rc/st_rc.c
F: drivers/media/platform/sti/c8sectpfe/
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH 08/18] ARM: multi_v7_defconfig: Enable STi FDMA driver
2016-04-21 11:04 [PATCH 00/18] Add support for FDMA DMA controller found on STi chipsets Peter Griffin
` (6 preceding siblings ...)
[not found] ` <1461236675-10176-1-git-send-email-peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
@ 2016-04-21 11:04 ` Peter Griffin
2016-04-21 11:25 ` Arnd Bergmann
2016-04-21 11:04 ` [PATCH 09/18] ASoC: sti: Update DT example to match the driver code Peter Griffin
` (9 subsequent siblings)
17 siblings, 1 reply; 53+ messages in thread
From: Peter Griffin @ 2016-04-21 11:04 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, srinivas.kandagatla,
maxime.coquelin, patrice.chotard, vinod.koul
Cc: peter.griffin, lee.jones, dmaengine, devicetree, arnd, broonie,
ludovic.barre
This DMA controller is found on all STi chipsets.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 2823490..61008a0 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -727,6 +727,7 @@ CONFIG_DMA_OMAP=y
CONFIG_QCOM_BAM_DMA=y
CONFIG_XILINX_VDMA=y
CONFIG_DMA_SUN6I=y
+CONFIG_ST_FDMA=y
CONFIG_STAGING=y
CONFIG_SENSORS_ISL29018=y
CONFIG_SENSORS_ISL29028=y
--
1.9.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [PATCH 08/18] ARM: multi_v7_defconfig: Enable STi FDMA driver
2016-04-21 11:04 ` [PATCH 08/18] ARM: multi_v7_defconfig: Enable STi FDMA driver Peter Griffin
@ 2016-04-21 11:25 ` Arnd Bergmann
2016-04-26 10:42 ` Peter Griffin
0 siblings, 1 reply; 53+ messages in thread
From: Arnd Bergmann @ 2016-04-21 11:25 UTC (permalink / raw)
To: linux-arm-kernel
Cc: devicetree, vinod.koul, srinivas.kandagatla, patrice.chotard,
linux-kernel, Peter Griffin, broonie, dmaengine, lee.jones,
ludovic.barre, maxime.coquelin
On Thursday 21 April 2016 12:04:25 Peter Griffin wrote:
> This DMA controller is found on all STi chipsets.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Acked-by: Lee Jones <lee.jones@linaro.org>
> ---
> arch/arm/configs/multi_v7_defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
> index 2823490..61008a0 100644
> --- a/arch/arm/configs/multi_v7_defconfig
> +++ b/arch/arm/configs/multi_v7_defconfig
> @@ -727,6 +727,7 @@ CONFIG_DMA_OMAP=y
> CONFIG_QCOM_BAM_DMA=y
> CONFIG_XILINX_VDMA=y
> CONFIG_DMA_SUN6I=y
> +CONFIG_ST_FDMA=y
> CONFIG_STAGING=y
> CONFIG_SENSORS_ISL29018=y
> CONFIG_SENSORS_ISL29028=y
> --
Is this needed for booting? If not, make it a loadable module.
Arnd
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 08/18] ARM: multi_v7_defconfig: Enable STi FDMA driver
2016-04-21 11:25 ` Arnd Bergmann
@ 2016-04-26 10:42 ` Peter Griffin
0 siblings, 0 replies; 53+ messages in thread
From: Peter Griffin @ 2016-04-26 10:42 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
srinivas.kandagatla-Re5JQEeQqe8AvxtiuMwx3w,
maxime.coquelin-qxv4g6HH51o, patrice.chotard-qxv4g6HH51o,
vinod.koul-ral2JQCrhuEAvxtiuMwx3w,
devicetree-u79uwXL29TY76Z2rM5mHXA, broonie-DgEjT+Ai2ygdnm+yROfE0A,
dmaengine-u79uwXL29TY76Z2rM5mHXA,
lee.jones-QSEj5FYQhm4dnm+yROfE0A, ludovic.barre-qxv4g6HH51o
Hi Arnd,
On Thu, 21 Apr 2016, Arnd Bergmann wrote:
> On Thursday 21 April 2016 12:04:25 Peter Griffin wrote:
> > This DMA controller is found on all STi chipsets.
> >
> > Signed-off-by: Peter Griffin <peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> > Acked-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> > ---
> > arch/arm/configs/multi_v7_defconfig | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
> > index 2823490..61008a0 100644
> > --- a/arch/arm/configs/multi_v7_defconfig
> > +++ b/arch/arm/configs/multi_v7_defconfig
> > @@ -727,6 +727,7 @@ CONFIG_DMA_OMAP=y
> > CONFIG_QCOM_BAM_DMA=y
> > CONFIG_XILINX_VDMA=y
> > CONFIG_DMA_SUN6I=y
> > +CONFIG_ST_FDMA=y
> > CONFIG_STAGING=y
> > CONFIG_SENSORS_ISL29018=y
> > CONFIG_SENSORS_ISL29028=y
> > --
>
> Is this needed for booting? If not, make it a loadable module.
No it isn't required for booting. Will fix in v4.
Peter
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^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH 09/18] ASoC: sti: Update DT example to match the driver code
2016-04-21 11:04 [PATCH 00/18] Add support for FDMA DMA controller found on STi chipsets Peter Griffin
` (7 preceding siblings ...)
2016-04-21 11:04 ` [PATCH 08/18] ARM: multi_v7_defconfig: Enable STi FDMA driver Peter Griffin
@ 2016-04-21 11:04 ` Peter Griffin
2016-04-21 11:27 ` Arnd Bergmann
[not found] ` <1461236675-10176-10-git-send-email-peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2016-04-21 11:04 ` [PATCH 10/18] ASoC: sti: Update example to include assigned-clocks and mclk-fs Peter Griffin
` (8 subsequent siblings)
17 siblings, 2 replies; 53+ messages in thread
From: Peter Griffin @ 2016-04-21 11:04 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, srinivas.kandagatla,
maxime.coquelin, patrice.chotard, vinod.koul
Cc: devicetree, arnd, arnaud.pouliquen, peter.griffin, broonie,
dmaengine, lee.jones, ludovic.barre
uniperiph-id, version and mode are ST specific bindings and
need the 'st,' prefix. Update the examples, as otherwise copying
them yields a runtime error parsing the DT node.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Cc: arnaud.pouliquen@st.com
---
.../devicetree/bindings/sound/st,sti-asoc-card.txt | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt b/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt
index 028fa1c..ef2e0c6 100644
--- a/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt
+++ b/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt
@@ -67,9 +67,9 @@ Example:
dmas = <&fdma0 4 0 1>;
dai-name = "Uni Player #1 (DAC)";
dma-names = "tx";
- uniperiph-id = <2>;
- version = <5>;
- mode = "PCM";
+ st,uniperiph-id = <2>;
+ st,version = <5>;
+ st,mode = "PCM";
};
sti_uni_player3: sti-uni-player@3 {
@@ -83,9 +83,9 @@ Example:
dmas = <&fdma0 7 0 1>;
dma-names = "tx";
dai-name = "Uni Player #1 (PIO)";
- uniperiph-id = <3>;
- version = <5>;
- mode = "SPDIF";
+ st,uniperiph-id = <3>;
+ st,version = <5>;
+ st,mode = "SPDIF";
};
sti_uni_reader1: sti-uni-reader@1 {
@@ -98,7 +98,7 @@ Example:
dmas = <&fdma0 6 0 1>;
dma-names = "rx";
dai-name = "Uni Reader #1 (HDMI RX)";
- version = <3>;
+ st,version = <3>;
};
2) sti-sas-codec: internal audio codec IPs driver
--
1.9.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [PATCH 09/18] ASoC: sti: Update DT example to match the driver code
2016-04-21 11:04 ` [PATCH 09/18] ASoC: sti: Update DT example to match the driver code Peter Griffin
@ 2016-04-21 11:27 ` Arnd Bergmann
2016-04-26 10:11 ` Peter Griffin
[not found] ` <1461236675-10176-10-git-send-email-peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
1 sibling, 1 reply; 53+ messages in thread
From: Arnd Bergmann @ 2016-04-21 11:27 UTC (permalink / raw)
To: Peter Griffin
Cc: devicetree, vinod.koul, srinivas.kandagatla, arnaud.pouliquen,
patrice.chotard, linux-kernel, broonie, ludovic.barre, dmaengine,
lee.jones, linux-arm-kernel, maxime.coquelin
On Thursday 21 April 2016 12:04:26 Peter Griffin wrote:
> uniperiph-id, version and mode are ST specific bindings and
> need the 'st,' prefix. Update the examples, as otherwise copying
> them yields a runtime error parsing the DT node.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Cc: arnaud.pouliquen@st.com
> ---
> .../devicetree/bindings/sound/st,sti-asoc-card.txt | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt b/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt
> index 028fa1c..ef2e0c6 100644
> --- a/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt
> +++ b/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt
> @@ -67,9 +67,9 @@ Example:
> dmas = <&fdma0 4 0 1>;
> dai-name = "Uni Player #1 (DAC)";
> dma-names = "tx";
> - uniperiph-id = <2>;
> - version = <5>;
> - mode = "PCM";
> + st,uniperiph-id = <2>;
> + st,version = <5>;
> + st,mode = "PCM";
> };
You don't change the binding desciption here, only the example,
so they no longer match.
What is st,uniperiph-id needed for anyway? It's often an indication
that you are doing something wrong if you need this.
Arnd
^ permalink raw reply [flat|nested] 53+ messages in thread* Re: [PATCH 09/18] ASoC: sti: Update DT example to match the driver code
2016-04-21 11:27 ` Arnd Bergmann
@ 2016-04-26 10:11 ` Peter Griffin
2016-04-26 10:58 ` Arnd Bergmann
0 siblings, 1 reply; 53+ messages in thread
From: Peter Griffin @ 2016-04-26 10:11 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linux-arm-kernel, linux-kernel, srinivas.kandagatla,
maxime.coquelin, patrice.chotard, vinod.koul, lee.jones,
dmaengine, devicetree, broonie, ludovic.barre, arnaud.pouliquen
Hi Arnd,
On Thu, 21 Apr 2016, Arnd Bergmann wrote:
> On Thursday 21 April 2016 12:04:26 Peter Griffin wrote:
> > uniperiph-id, version and mode are ST specific bindings and
> > need the 'st,' prefix. Update the examples, as otherwise copying
> > them yields a runtime error parsing the DT node.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > Cc: arnaud.pouliquen@st.com
> > ---
> > .../devicetree/bindings/sound/st,sti-asoc-card.txt | 14 +++++++-------
> > 1 file changed, 7 insertions(+), 7 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt b/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt
> > index 028fa1c..ef2e0c6 100644
> > --- a/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt
> > +++ b/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt
> > @@ -67,9 +67,9 @@ Example:
> > dmas = <&fdma0 4 0 1>;
> > dai-name = "Uni Player #1 (DAC)";
> > dma-names = "tx";
> > - uniperiph-id = <2>;
> > - version = <5>;
> > - mode = "PCM";
> > + st,uniperiph-id = <2>;
> > + st,version = <5>;
> > + st,mode = "PCM";
> > };
>
> You don't change the binding desciption here, only the example,
> so they no longer match.
Whoops. Will fix that in v4.
>
> What is st,uniperiph-id needed for anyway? It's often an indication
> that you are doing something wrong if you need this.
>From looking at the code in sound/soc/sti/uniperif_player.c, there is
one sysconf register called "Audio glue config" which is shared by all
of the uniperif IP instances. This binding is being used to generate a
bitoffset into this shared register based on the instance of the IP.
I guess the alternative is to have an explosion of compatibles?
st,sti-uni-player-1
st,sti-uni-player-2
st,sti-uni-player-3
If not what would you recommend instead? :-)
I don't currently have access to the functional spec for this
IP block, but I have asked ST to send it to me to see if there is any
other way to derive this information (although I suspect there won't
be).
FYI I didn't actually write or upstream that driver. However fdma is
a depedency of the ASoC driver and it is required to get working audio
upstream. It's also worth pointing out that this ASoC driver has been
merged for a while, so I'm not sure what your opinion is of now changing
the DT bindings? Obviously it is currently not used by anyone upstream
due to the missing fdma depedency.
regards,
Peter.
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 09/18] ASoC: sti: Update DT example to match the driver code
2016-04-26 10:11 ` Peter Griffin
@ 2016-04-26 10:58 ` Arnd Bergmann
2016-04-26 11:15 ` Peter Griffin
0 siblings, 1 reply; 53+ messages in thread
From: Arnd Bergmann @ 2016-04-26 10:58 UTC (permalink / raw)
To: Peter Griffin
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
srinivas.kandagatla-Re5JQEeQqe8AvxtiuMwx3w,
maxime.coquelin-qxv4g6HH51o, patrice.chotard-qxv4g6HH51o,
vinod.koul-ral2JQCrhuEAvxtiuMwx3w,
lee.jones-QSEj5FYQhm4dnm+yROfE0A,
dmaengine-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, broonie-DgEjT+Ai2ygdnm+yROfE0A,
ludovic.barre-qxv4g6HH51o, arnaud.pouliquen-qxv4g6HH51o
On Tuesday 26 April 2016 11:11:36 Peter Griffin wrote:
> Hi Arnd,
>
> On Thu, 21 Apr 2016, Arnd Bergmann wrote:
>
> > On Thursday 21 April 2016 12:04:26 Peter Griffin wrote:
> > > uniperiph-id, version and mode are ST specific bindings and
> > > need the 'st,' prefix. Update the examples, as otherwise copying
> > > them yields a runtime error parsing the DT node.
> > >
> > > Signed-off-by: Peter Griffin <peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> > > Cc: arnaud.pouliquen-qxv4g6HH51o@public.gmane.org
> > > ---
> > > .../devicetree/bindings/sound/st,sti-asoc-card.txt | 14 +++++++-------
> > > 1 file changed, 7 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt b/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt
> > > index 028fa1c..ef2e0c6 100644
> > > --- a/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt
> > > +++ b/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt
> > > @@ -67,9 +67,9 @@ Example:
> > > dmas = <&fdma0 4 0 1>;
> > > dai-name = "Uni Player #1 (DAC)";
> > > dma-names = "tx";
> > > - uniperiph-id = <2>;
> > > - version = <5>;
> > > - mode = "PCM";
> > > + st,uniperiph-id = <2>;
> > > + st,version = <5>;
> > > + st,mode = "PCM";
> > > };
> >
> > You don't change the binding desciption here, only the example,
> > so they no longer match.
>
> Whoops. Will fix that in v4.
>
> >
> > What is st,uniperiph-id needed for anyway? It's often an indication
> > that you are doing something wrong if you need this.
>
> From looking at the code in sound/soc/sti/uniperif_player.c, there is
> one sysconf register called "Audio glue config" which is shared by all
> of the uniperif IP instances. This binding is being used to generate a
> bitoffset into this shared register based on the instance of the IP.
>
> I guess the alternative is to have an explosion of compatibles?
>
> st,sti-uni-player-1
> st,sti-uni-player-2
> st,sti-uni-player-3
>
That would certainly be worse: if the devices are actually identical,
they should have the same compatible string.
> If not what would you recommend instead? :-)
It's still not clear to me what that bit in the syscfg register
is for. Given the error message about "sti-audio-clk-glue",
I suspect that this is actually a clock controller and that
it should be using the clock binding with a separate driver
instead of manipulating the regmap directly from the audio driver.
Arnd
--
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^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 09/18] ASoC: sti: Update DT example to match the driver code
2016-04-26 10:58 ` Arnd Bergmann
@ 2016-04-26 11:15 ` Peter Griffin
2016-04-26 11:44 ` Arnd Bergmann
0 siblings, 1 reply; 53+ messages in thread
From: Peter Griffin @ 2016-04-26 11:15 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linux-arm-kernel, linux-kernel, srinivas.kandagatla,
maxime.coquelin, patrice.chotard, vinod.koul, lee.jones,
dmaengine, devicetree, broonie, ludovic.barre, arnaud.pouliquen
Hi Arnd,
On Tue, 26 Apr 2016, Arnd Bergmann wrote:
> On Tuesday 26 April 2016 11:11:36 Peter Griffin wrote:
> > Hi Arnd,
> >
> > On Thu, 21 Apr 2016, Arnd Bergmann wrote:
> >
> > > On Thursday 21 April 2016 12:04:26 Peter Griffin wrote:
> > > > uniperiph-id, version and mode are ST specific bindings and
> > > > need the 'st,' prefix. Update the examples, as otherwise copying
> > > > them yields a runtime error parsing the DT node.
> > > >
> > > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > > > Cc: arnaud.pouliquen@st.com
> > > > ---
> > > > .../devicetree/bindings/sound/st,sti-asoc-card.txt | 14 +++++++-------
> > > > 1 file changed, 7 insertions(+), 7 deletions(-)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt b/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt
> > > > index 028fa1c..ef2e0c6 100644
> > > > --- a/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt
> > > > +++ b/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt
> > > > @@ -67,9 +67,9 @@ Example:
> > > > dmas = <&fdma0 4 0 1>;
> > > > dai-name = "Uni Player #1 (DAC)";
> > > > dma-names = "tx";
> > > > - uniperiph-id = <2>;
> > > > - version = <5>;
> > > > - mode = "PCM";
> > > > + st,uniperiph-id = <2>;
> > > > + st,version = <5>;
> > > > + st,mode = "PCM";
> > > > };
> > >
> > > You don't change the binding desciption here, only the example,
> > > so they no longer match.
> >
> > Whoops. Will fix that in v4.
> >
> > >
> > > What is st,uniperiph-id needed for anyway? It's often an indication
> > > that you are doing something wrong if you need this.
> >
> > From looking at the code in sound/soc/sti/uniperif_player.c, there is
> > one sysconf register called "Audio glue config" which is shared by all
> > of the uniperif IP instances. This binding is being used to generate a
> > bitoffset into this shared register based on the instance of the IP.
> >
> > I guess the alternative is to have an explosion of compatibles?
> >
> > st,sti-uni-player-1
> > st,sti-uni-player-2
> > st,sti-uni-player-3
> >
>
> That would certainly be worse: if the devices are actually identical,
> they should have the same compatible string.
>
> > If not what would you recommend instead? :-)
>
> It's still not clear to me what that bit in the syscfg register
> is for. Given the error message about "sti-audio-clk-glue",
> I suspect that this is actually a clock controller and that
> it should be using the clock binding with a separate driver
> instead of manipulating the regmap directly from the audio driver.
Luckily I do have the datasheet for the audio-glue sysconf register.
It says: -
[11:8] PCM_CLK_SEL: Selects the frequency synthesizer clock or the external
PCM clock for each channel.
The driver only ever sets this to 1 which selects the frequency synthesizer
clock. So the bitfield of the register which the driver is using (PCM_CLK_SEL)
is a clock mux.
Peter.
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 09/18] ASoC: sti: Update DT example to match the driver code
2016-04-26 11:15 ` Peter Griffin
@ 2016-04-26 11:44 ` Arnd Bergmann
2016-05-04 7:52 ` Arnaud Pouliquen
0 siblings, 1 reply; 53+ messages in thread
From: Arnd Bergmann @ 2016-04-26 11:44 UTC (permalink / raw)
To: Peter Griffin
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
srinivas.kandagatla-Re5JQEeQqe8AvxtiuMwx3w,
maxime.coquelin-qxv4g6HH51o, patrice.chotard-qxv4g6HH51o,
vinod.koul-ral2JQCrhuEAvxtiuMwx3w,
lee.jones-QSEj5FYQhm4dnm+yROfE0A,
dmaengine-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, broonie-DgEjT+Ai2ygdnm+yROfE0A,
ludovic.barre-qxv4g6HH51o, arnaud.pouliquen-qxv4g6HH51o
On Tuesday 26 April 2016 12:15:32 Peter Griffin wrote:
> >
> > > If not what would you recommend instead?
> >
> > It's still not clear to me what that bit in the syscfg register
> > is for. Given the error message about "sti-audio-clk-glue",
> > I suspect that this is actually a clock controller and that
> > it should be using the clock binding with a separate driver
> > instead of manipulating the regmap directly from the audio driver.
>
> Luckily I do have the datasheet for the audio-glue sysconf register.
>
> It says: -
>
> [11:8] PCM_CLK_SEL: Selects the frequency synthesizer clock or the external
> PCM clock for each channel.
>
> The driver only ever sets this to 1 which selects the frequency synthesizer
> clock. So the bitfield of the register which the driver is using (PCM_CLK_SEL)
> is a clock mux.
Ok, that sounds like it could be either a really simple clock driver
with just a few lines, or integrated into an existing clock driver
if you already have one for this syscon node.
Arnd
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^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 09/18] ASoC: sti: Update DT example to match the driver code
2016-04-26 11:44 ` Arnd Bergmann
@ 2016-05-04 7:52 ` Arnaud Pouliquen
2016-05-04 9:05 ` Arnd Bergmann
0 siblings, 1 reply; 53+ messages in thread
From: Arnaud Pouliquen @ 2016-05-04 7:52 UTC (permalink / raw)
To: Arnd Bergmann, Peter Griffin
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
srinivas.kandagatla-Re5JQEeQqe8AvxtiuMwx3w,
maxime.coquelin-qxv4g6HH51o, patrice.chotard-qxv4g6HH51o,
vinod.koul-ral2JQCrhuEAvxtiuMwx3w,
lee.jones-QSEj5FYQhm4dnm+yROfE0A,
dmaengine-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, broonie-DgEjT+Ai2ygdnm+yROfE0A,
ludovic.barre-qxv4g6HH51o
hello Arnd, peter,
On 04/26/2016 01:44 PM, Arnd Bergmann wrote:
> On Tuesday 26 April 2016 12:15:32 Peter Griffin wrote:
>>>
>>>> If not what would you recommend instead?
>>>
>>> It's still not clear to me what that bit in the syscfg register
>>> is for. Given the error message about "sti-audio-clk-glue",
>>> I suspect that this is actually a clock controller and that
>>> it should be using the clock binding with a separate driver
>>> instead of manipulating the regmap directly from the audio driver.
>>
>> Luckily I do have the datasheet for the audio-glue sysconf register.
>>
>> It says: -
>>
>> [11:8] PCM_CLK_SEL: Selects the frequency synthesizer clock or the external
>> PCM clock for each channel.
>>
>> The driver only ever sets this to 1 which selects the frequency synthesizer
>> clock. So the bitfield of the register which the driver is using (PCM_CLK_SEL)
>> is a clock mux.
>
> Ok, that sounds like it could be either a really simple clock driver
> with just a few lines, or integrated into an existing clock driver
> if you already have one for this syscon node.
>
> Arnd
>
FYI, Name of this glue is related to the register name. But it does not
concern only clock...
This glue register is used to :
- select clock source ( clock framework or external clock from GPIO)
=> one bit field per IP instance (player->clk_sel)
- select uniperiph player IP instance for PCM out.
(http://www.spinics.net/lists/alsa-devel/msg49034.html)
Regards
Arnaud
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^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 09/18] ASoC: sti: Update DT example to match the driver code
2016-05-04 7:52 ` Arnaud Pouliquen
@ 2016-05-04 9:05 ` Arnd Bergmann
0 siblings, 0 replies; 53+ messages in thread
From: Arnd Bergmann @ 2016-05-04 9:05 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Arnaud Pouliquen, Peter Griffin, devicetree, vinod.koul,
srinivas.kandagatla, patrice.chotard, linux-kernel, broonie,
ludovic.barre, dmaengine, lee.jones, maxime.coquelin
On Wednesday 04 May 2016 09:52:19 Arnaud Pouliquen wrote:
> hello Arnd, peter,
>
> On 04/26/2016 01:44 PM, Arnd Bergmann wrote:
> > On Tuesday 26 April 2016 12:15:32 Peter Griffin wrote:
> >>>
> >>>> If not what would you recommend instead?
> >>>
> >>> It's still not clear to me what that bit in the syscfg register
> >>> is for. Given the error message about "sti-audio-clk-glue",
> >>> I suspect that this is actually a clock controller and that
> >>> it should be using the clock binding with a separate driver
> >>> instead of manipulating the regmap directly from the audio driver.
> >>
> >> Luckily I do have the datasheet for the audio-glue sysconf register.
> >>
> >> It says: -
> >>
> >> [11:8] PCM_CLK_SEL: Selects the frequency synthesizer clock or the external
> >> PCM clock for each channel.
> >>
> >> The driver only ever sets this to 1 which selects the frequency synthesizer
> >> clock. So the bitfield of the register which the driver is using (PCM_CLK_SEL)
> >> is a clock mux.
> >
> > Ok, that sounds like it could be either a really simple clock driver
> > with just a few lines, or integrated into an existing clock driver
> > if you already have one for this syscon node.
> >
> > Arnd
> >
> FYI, Name of this glue is related to the register name. But it does not
> concern only clock...
> This glue register is used to :
> - select clock source ( clock framework or external clock from GPIO)
> => one bit field per IP instance (player->clk_sel)
> - select uniperiph player IP instance for PCM out.
> (http://www.spinics.net/lists/alsa-devel/msg49034.html)
Ok, I see. This is of course again the STi platform being a bit different
from everyone else, and whatever we do to hide it won't give us a nice
abstraction. Having just a clock driver for the register won't do the
job here as you say, so I guess the original patch was already the
least awkward way to handle it.
Arnd
^ permalink raw reply [flat|nested] 53+ messages in thread
[parent not found: <1461236675-10176-10-git-send-email-peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>]
* Re: [PATCH 09/18] ASoC: sti: Update DT example to match the driver code
[not found] ` <1461236675-10176-10-git-send-email-peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
@ 2016-04-21 15:57 ` Mark Brown
[not found] ` <20160421155753.GS3217-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
0 siblings, 1 reply; 53+ messages in thread
From: Mark Brown @ 2016-04-21 15:57 UTC (permalink / raw)
To: Peter Griffin
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
srinivas.kandagatla-Re5JQEeQqe8AvxtiuMwx3w,
maxime.coquelin-qxv4g6HH51o, patrice.chotard-qxv4g6HH51o,
vinod.koul-ral2JQCrhuEAvxtiuMwx3w,
lee.jones-QSEj5FYQhm4dnm+yROfE0A,
dmaengine-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
ludovic.barre-qxv4g6HH51o, arnaud.pouliquen-qxv4g6HH51o
[-- Attachment #1: Type: text/plain, Size: 349 bytes --]
On Thu, Apr 21, 2016 at 12:04:26PM +0100, Peter Griffin wrote:
> uniperiph-id, version and mode are ST specific bindings and
> need the 'st,' prefix. Update the examples, as otherwise copying
> them yields a runtime error parsing the DT node.
I'm not sure what connection this or the other ASoC documentation update
have to the rest of the series?
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^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH 10/18] ASoC: sti: Update example to include assigned-clocks and mclk-fs
2016-04-21 11:04 [PATCH 00/18] Add support for FDMA DMA controller found on STi chipsets Peter Griffin
` (8 preceding siblings ...)
2016-04-21 11:04 ` [PATCH 09/18] ASoC: sti: Update DT example to match the driver code Peter Griffin
@ 2016-04-21 11:04 ` Peter Griffin
[not found] ` <1461236675-10176-11-git-send-email-peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2016-04-21 11:04 ` [PATCH 11/18] ARM: multi_v7_defconfig: Enable STi and simple-card drivers Peter Griffin
` (7 subsequent siblings)
17 siblings, 1 reply; 53+ messages in thread
From: Peter Griffin @ 2016-04-21 11:04 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, srinivas.kandagatla,
maxime.coquelin, patrice.chotard, vinod.koul
Cc: peter.griffin, lee.jones, dmaengine, devicetree, arnd, broonie,
ludovic.barre, arnaud.pouliquen
Update the examples, as otherwise driver errors with an incorrect
mclk ratio at runtime.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Cc: arnaud.pouliquen@st.com
---
Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt b/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt
index ef2e0c6..e6ef96a8 100644
--- a/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt
+++ b/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt
@@ -62,6 +62,9 @@ Example:
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
+ assigned-clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
+ assigned-clock-parents = <&clk_s_d0_quadfs 2>;
+ assigned-clock-rates = <50000000>;
reg = <0x8D82000 0x158>;
interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
dmas = <&fdma0 4 0 1>;
@@ -78,6 +81,9 @@ Example:
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
+ assigned-clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
+ assigned-clock-parents = <&clk_s_d0_quadfs 3>;
+ assigned-clock-rates = <50000000>;
reg = <0x8D85000 0x158>;
interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
dmas = <&fdma0 7 0 1>;
@@ -133,6 +139,7 @@ Example of audio card declaration:
/* DAC */
format = "i2s";
dai-tdm-slot-width = <32>;
+ mclk-fs = <256>;
cpu {
sound-dai = <&sti_uni_player2>;
};
@@ -144,6 +151,7 @@ Example of audio card declaration:
simple-audio-card,dai-link@1 {
/* SPDIF */
format = "left_j";
+ mclk-fs = <128>;
cpu {
sound-dai = <&sti_uni_player3>;
};
--
1.9.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 11/18] ARM: multi_v7_defconfig: Enable STi and simple-card drivers.
2016-04-21 11:04 [PATCH 00/18] Add support for FDMA DMA controller found on STi chipsets Peter Griffin
` (9 preceding siblings ...)
2016-04-21 11:04 ` [PATCH 10/18] ASoC: sti: Update example to include assigned-clocks and mclk-fs Peter Griffin
@ 2016-04-21 11:04 ` Peter Griffin
2016-04-21 11:04 ` [PATCH 12/18] ARM: DT: STiH407: Add i2s_out pinctrl configuration Peter Griffin
` (6 subsequent siblings)
17 siblings, 0 replies; 53+ messages in thread
From: Peter Griffin @ 2016-04-21 11:04 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, srinivas.kandagatla,
maxime.coquelin, patrice.chotard, vinod.koul
Cc: devicetree, arnd, arnaud.pouliquen, peter.griffin, broonie,
dmaengine, lee.jones, ludovic.barre
This patch enables the STi ALSA drivers found on STi platforms
as well as the simple-card driver which is a dependency to have
working sound.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Cc: arnaud.pouliquen@st.com
---
arch/arm/configs/multi_v7_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 61008a0..b391882 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -588,6 +588,9 @@ CONFIG_SND_SOC_AK4642=m
CONFIG_SND_SOC_SGTL5000=m
CONFIG_SND_SOC_SPDIF=m
CONFIG_SND_SOC_WM8978=m
+CONFIG_SND_SOC_STI=m
+CONFIG_SND_SOC_STI_SAS=m
+CONFIG_SND_SIMPLE_CARD=m
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_MVEBU=y
--
1.9.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 12/18] ARM: DT: STiH407: Add i2s_out pinctrl configuration
2016-04-21 11:04 [PATCH 00/18] Add support for FDMA DMA controller found on STi chipsets Peter Griffin
` (10 preceding siblings ...)
2016-04-21 11:04 ` [PATCH 11/18] ARM: multi_v7_defconfig: Enable STi and simple-card drivers Peter Griffin
@ 2016-04-21 11:04 ` Peter Griffin
2016-04-21 11:04 ` [PATCH 13/18] ARM: DT: STiH407: Add i2s_in " Peter Griffin
` (5 subsequent siblings)
17 siblings, 0 replies; 53+ messages in thread
From: Peter Griffin @ 2016-04-21 11:04 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, srinivas.kandagatla,
maxime.coquelin, patrice.chotard, vinod.koul
Cc: peter.griffin, lee.jones, dmaengine, devicetree, arnd, broonie,
ludovic.barre
This patch adds the pinctrl config for the i2s_out pins
used by the uniperif player IP.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm/boot/dts/stih407-pinctrl.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index a538ae5..0fb5c8a 100644
--- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -1067,6 +1067,29 @@
};
};
+ i2s_out {
+ pinctrl_i2s_8ch_out: i2s_8ch_out{
+ st,pins {
+ mclk = <&pio33 5 ALT1 OUT>;
+ lrclk = <&pio33 7 ALT1 OUT>;
+ sclk = <&pio33 6 ALT1 OUT>;
+ data0 = <&pio33 4 ALT1 OUT>;
+ data1 = <&pio34 0 ALT1 OUT>;
+ data2 = <&pio34 1 ALT1 OUT>;
+ data3 = <&pio34 2 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_i2s_2ch_out: i2s_2ch_out{
+ st,pins {
+ mclk = <&pio33 5 ALT1 OUT>;
+ lrclk = <&pio33 7 ALT1 OUT>;
+ sclk = <&pio33 6 ALT1 OUT>;
+ data0 = <&pio33 4 ALT1 OUT>;
+ };
+ };
+ };
+
serial3 {
pinctrl_serial3: serial3-0 {
st,pins {
--
1.9.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 13/18] ARM: DT: STiH407: Add i2s_in pinctrl configuration
2016-04-21 11:04 [PATCH 00/18] Add support for FDMA DMA controller found on STi chipsets Peter Griffin
` (11 preceding siblings ...)
2016-04-21 11:04 ` [PATCH 12/18] ARM: DT: STiH407: Add i2s_out pinctrl configuration Peter Griffin
@ 2016-04-21 11:04 ` Peter Griffin
2016-04-21 11:04 ` [PATCH 14/18] ARM: DT: STiH407: Add spdif_out pinctrl config Peter Griffin
` (4 subsequent siblings)
17 siblings, 0 replies; 53+ messages in thread
From: Peter Griffin @ 2016-04-21 11:04 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, srinivas.kandagatla,
maxime.coquelin, patrice.chotard, vinod.koul
Cc: peter.griffin, lee.jones, dmaengine, devicetree, arnd, broonie,
ludovic.barre
This patch adds the pinctrl config for the i2s_in pins
used by the uniperif reader IP.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm/boot/dts/stih407-pinctrl.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index 0fb5c8a..537db7e 100644
--- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -1090,6 +1090,30 @@
};
};
+ i2s_in {
+ pinctrl_i2s_8ch_in: i2s_8ch_in{
+ st,pins {
+ mclk = <&pio32 5 ALT1 IN>;
+ lrclk = <&pio32 7 ALT1 IN>;
+ sclk = <&pio32 6 ALT1 IN>;
+ data0 = <&pio32 4 ALT1 IN>;
+ data1 = <&pio33 0 ALT1 IN>;
+ data2 = <&pio33 1 ALT1 IN>;
+ data3 = <&pio33 2 ALT1 IN>;
+ data4 = <&pio33 3 ALT1 IN>;
+ };
+ };
+
+ pinctrl_i2s_2ch_in: i2s_2ch_in{
+ st,pins {
+ mclk = <&pio32 5 ALT1 IN>;
+ lrclk = <&pio32 7 ALT1 IN>;
+ sclk = <&pio32 6 ALT1 IN>;
+ data0 = <&pio32 4 ALT1 IN>;
+ };
+ };
+ };
+
serial3 {
pinctrl_serial3: serial3-0 {
st,pins {
--
1.9.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 14/18] ARM: DT: STiH407: Add spdif_out pinctrl config
2016-04-21 11:04 [PATCH 00/18] Add support for FDMA DMA controller found on STi chipsets Peter Griffin
` (12 preceding siblings ...)
2016-04-21 11:04 ` [PATCH 13/18] ARM: DT: STiH407: Add i2s_in " Peter Griffin
@ 2016-04-21 11:04 ` Peter Griffin
2016-04-21 11:04 ` [PATCH 15/18] ARM: STi: DT: STiH407: Add sti-sasg-codec dt node Peter Griffin
` (3 subsequent siblings)
17 siblings, 0 replies; 53+ messages in thread
From: Peter Griffin @ 2016-04-21 11:04 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, srinivas.kandagatla,
maxime.coquelin, patrice.chotard, vinod.koul
Cc: peter.griffin, lee.jones, dmaengine, devicetree, arnd, broonie,
ludovic.barre
This patch adds the pinctrl config for the spidf out
pins used by the sasg codec IP.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm/boot/dts/stih407-pinctrl.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index 537db7e..598dbab 100644
--- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -1114,6 +1114,14 @@
};
};
+ spdif_out {
+ pinctrl_spdif_out: spdif_out{
+ st,pins {
+ spdif_out = <&pio34 7 ALT1 OUT>;
+ };
+ };
+ };
+
serial3 {
pinctrl_serial3: serial3-0 {
st,pins {
--
1.9.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 15/18] ARM: STi: DT: STiH407: Add sti-sasg-codec dt node
2016-04-21 11:04 [PATCH 00/18] Add support for FDMA DMA controller found on STi chipsets Peter Griffin
` (13 preceding siblings ...)
2016-04-21 11:04 ` [PATCH 14/18] ARM: DT: STiH407: Add spdif_out pinctrl config Peter Griffin
@ 2016-04-21 11:04 ` Peter Griffin
2016-04-21 11:04 ` [PATCH 16/18] ARM: STi: DT: STiH407: Add uniperif player dt nodes Peter Griffin
` (2 subsequent siblings)
17 siblings, 0 replies; 53+ messages in thread
From: Peter Griffin @ 2016-04-21 11:04 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, srinivas.kandagatla,
maxime.coquelin, patrice.chotard, vinod.koul
Cc: peter.griffin, lee.jones, dmaengine, devicetree, arnd, broonie,
ludovic.barre
This patch adds the dt node for the internal audio
codec IP.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm/boot/dts/stih407-family.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index a77008f..740c443 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -745,5 +745,14 @@
"fdma_low",
"fdma_ic";
};
+
+ sti_sasg_codec: sti-sasg-codec {
+ compatible = "st,stih407-sas-codec";
+ #sound-dai-cells = <1>;
+ status = "okay";
+ st,syscfg = <&syscfg_core>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spdif_out >;
+ };
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 16/18] ARM: STi: DT: STiH407: Add uniperif player dt nodes
2016-04-21 11:04 [PATCH 00/18] Add support for FDMA DMA controller found on STi chipsets Peter Griffin
` (14 preceding siblings ...)
2016-04-21 11:04 ` [PATCH 15/18] ARM: STi: DT: STiH407: Add sti-sasg-codec dt node Peter Griffin
@ 2016-04-21 11:04 ` Peter Griffin
2016-04-21 11:04 ` [PATCH 17/18] ARM: STi: DT: STiH407: Add uniperif reader " Peter Griffin
2016-04-21 11:04 ` [PATCH 18/18] ARM: DT: STi: stihxxx-b2120: Add DT nodes for STi audio card Peter Griffin
17 siblings, 0 replies; 53+ messages in thread
From: Peter Griffin @ 2016-04-21 11:04 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, srinivas.kandagatla,
maxime.coquelin, patrice.chotard, vinod.koul
Cc: peter.griffin, lee.jones, dmaengine, devicetree, arnd, broonie,
ludovic.barre
This patch adds the DT nodes for the uniperif player
IP blocks found on STiH407 family silicon.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm/boot/dts/stih407-family.dtsi | 76 +++++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 740c443..af184c4 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -754,5 +754,81 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif_out >;
};
+
+ sti_uni_player0: sti-uni-player@0 {
+ compatible = "st,sti-uni-player";
+ status = "disabled";
+ #sound-dai-cells = <0>;
+ st,syscfg = <&syscfg_core>;
+ clocks = <&clk_s_d0_flexgen CLK_PCM_0>;
+ assigned-clocks = <&clk_s_d0_flexgen CLK_PCM_0>;
+ assigned-clock-parents = <&clk_s_d0_quadfs 0>;
+ assigned-clock-rates = <50000000>;
+ reg = <0x8D80000 0x158>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>;
+ dmas = <&fdma0 2 0 1>;
+ dai-name = "Uni Player #0 (HDMI)";
+ dma-names = "tx";
+ st,uniperiph-id = <0>;
+ st,version = <5>;
+ st,mode = "HDMI";
+ };
+
+ sti_uni_player1: sti-uni-player@1 {
+ compatible = "st,sti-uni-player";
+ status = "disabled";
+ #sound-dai-cells = <0>;
+ st,syscfg = <&syscfg_core>;
+ clocks = <&clk_s_d0_flexgen CLK_PCM_1>;
+ assigned-clocks = <&clk_s_d0_flexgen CLK_PCM_1>;
+ assigned-clock-parents = <&clk_s_d0_quadfs 1>;
+ assigned-clock-rates = <50000000>;
+ reg = <0x8D81000 0x158>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
+ dmas = <&fdma0 3 0 1>;
+ dai-name = "Uni Player #1 (PIO)";
+ dma-names = "tx";
+ st,uniperiph-id = <1>;
+ st,version = <5>;
+ st,mode = "PCM";
+ };
+
+ sti_uni_player2: sti-uni-player@2 {
+ compatible = "st,sti-uni-player";
+ status = "disabled";
+ #sound-dai-cells = <0>;
+ st,syscfg = <&syscfg_core>;
+ clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
+ assigned-clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
+ assigned-clock-parents = <&clk_s_d0_quadfs 2>;
+ assigned-clock-rates = <50000000>;
+ reg = <0x8D82000 0x158>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
+ dmas = <&fdma0 4 0 1>;
+ dai-name = "Uni Player #1 (DAC)";
+ dma-names = "tx";
+ st,uniperiph-id = <2>;
+ st,version = <5>;
+ st,mode = "PCM";
+ };
+
+ sti_uni_player3: sti-uni-player@3 {
+ compatible = "st,sti-uni-player";
+ status = "disabled";
+ #sound-dai-cells = <0>;
+ st,syscfg = <&syscfg_core>;
+ clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
+ assigned-clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
+ assigned-clock-parents = <&clk_s_d0_quadfs 3>;
+ assigned-clock-rates = <50000000>;
+ reg = <0x8D85000 0x158>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
+ dmas = <&fdma0 7 0 1>;
+ dma-names = "tx";
+ dai-name = "Uni Player #1 (PIO)";
+ st,uniperiph-id = <3>;
+ st,version = <5>;
+ st,mode = "SPDIF";
+ };
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 17/18] ARM: STi: DT: STiH407: Add uniperif reader dt nodes
2016-04-21 11:04 [PATCH 00/18] Add support for FDMA DMA controller found on STi chipsets Peter Griffin
` (15 preceding siblings ...)
2016-04-21 11:04 ` [PATCH 16/18] ARM: STi: DT: STiH407: Add uniperif player dt nodes Peter Griffin
@ 2016-04-21 11:04 ` Peter Griffin
2016-04-21 11:04 ` [PATCH 18/18] ARM: DT: STi: stihxxx-b2120: Add DT nodes for STi audio card Peter Griffin
17 siblings, 0 replies; 53+ messages in thread
From: Peter Griffin @ 2016-04-21 11:04 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, srinivas.kandagatla,
maxime.coquelin, patrice.chotard, vinod.koul
Cc: peter.griffin, lee.jones, dmaengine, devicetree, arnd, broonie,
ludovic.barre
This patch adds the DT node for the uniperif reader
IP block found on STiH407 family silicon.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm/boot/dts/stih407-family.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index af184c4..9a27354 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -830,5 +830,33 @@
st,version = <5>;
st,mode = "SPDIF";
};
+
+ sti_uni_reader0: sti-uni-reader@0 {
+ compatible = "st,sti-uni-reader";
+ status = "disabled";
+ #sound-dai-cells = <0>;
+ st,syscfg = <&syscfg_core>;
+ reg = <0x8D83000 0x158>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>;
+ dmas = <&fdma0 5 0 1>;
+ dma-names = "rx";
+ dai-name = "Uni Reader #0 (PCM IN)";
+ st,version = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2s_8ch_in>;
+ };
+
+ sti_uni_reader1: sti-uni-reader@1 {
+ compatible = "st,sti-uni-reader";
+ status = "disabled";
+ #sound-dai-cells = <0>;
+ st,syscfg = <&syscfg_core>;
+ reg = <0x8D84000 0x158>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_NONE>;
+ dmas = <&fdma0 6 0 1>;
+ dma-names = "rx";
+ dai-name = "Uni Reader #1 (HDMI RX)";
+ st,version = <3>;
+ };
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 18/18] ARM: DT: STi: stihxxx-b2120: Add DT nodes for STi audio card
2016-04-21 11:04 [PATCH 00/18] Add support for FDMA DMA controller found on STi chipsets Peter Griffin
` (16 preceding siblings ...)
2016-04-21 11:04 ` [PATCH 17/18] ARM: STi: DT: STiH407: Add uniperif reader " Peter Griffin
@ 2016-04-21 11:04 ` Peter Griffin
17 siblings, 0 replies; 53+ messages in thread
From: Peter Griffin @ 2016-04-21 11:04 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, srinivas.kandagatla,
maxime.coquelin, patrice.chotard, vinod.koul
Cc: peter.griffin, lee.jones, dmaengine, devicetree, arnd, broonie,
ludovic.barre
This patch enables the uniperif players 2 & 3 for b2120 boards
and also adds the "simple-audio-card" device node to interconnect
the SoC sound device and the codec.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm/boot/dts/stihxxx-b2120.dtsi | 40 ++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
index 133375b..f50d293 100644
--- a/arch/arm/boot/dts/stihxxx-b2120.dtsi
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -135,5 +135,45 @@
dvb-card = <STV0367_TDA18212_NIMA_1>;
};
};
+
+ sti_uni_player2: sti-uni-player@2 {
+ status = "okay";
+ };
+
+ sti_uni_player3: sti-uni-player@3 {
+ status = "okay";
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "sti audio card";
+ status = "okay";
+
+ simple-audio-card,dai-link@0 {
+ /* DAC */
+ format = "i2s";
+ dai-tdm-slot-width = <32>;
+ mclk-fs = <256>;
+ cpu {
+ sound-dai = <&sti_uni_player2>;
+ };
+
+ codec {
+ sound-dai = <&sti_sasg_codec 1>;
+ };
+ };
+ simple-audio-card,dai-link@1 {
+ /* SPDIF */
+ format = "left_j";
+ mclk-fs = <128>;
+ cpu {
+ sound-dai = <&sti_uni_player3>;
+ };
+
+ codec {
+ sound-dai = <&sti_sasg_codec 0>;
+ };
+ };
+ };
};
};
--
1.9.1
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