From: Vignesh R <vigneshr-l0cyMroinI0@public.gmane.org>
To: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>,
"linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
<linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
Cc: Graham Moore
<grmoore-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>,
Alan Tull
<atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>,
Brian Norris
<computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
David Woodhouse <dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>,
Dinh Nguyen
<dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>,
Yves Vandervennet
<yvanderv-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>,
"devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Subject: Re: [PATCH V12 2/2] mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller
Date: Tue, 14 Jun 2016 10:40:10 +0530 [thread overview]
Message-ID: <575F91B2.7010304@ti.com> (raw)
In-Reply-To: <1465000774-7762-2-git-send-email-marex-ynQEQJNshbs@public.gmane.org>
Hi,
On Saturday 04 June 2016 06:09 AM, Marek Vasut wrote:
[...]
> +
> +static int cqspi_indirect_read_execute(struct spi_nor *nor,
> + u8 *rxbuf, const unsigned n_rx)
> +{
> + struct cqspi_flash_pdata *f_pdata = nor->priv;
> + struct cqspi_st *cqspi = f_pdata->cqspi;
> + void __iomem *reg_base = cqspi->iobase;
> + void __iomem *ahb_base = cqspi->ahb_base;
> + unsigned int remaining = n_rx;
> + unsigned int bytes_to_read = 0;
> + int ret = 0;
> +
> + writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
> +
> + /* Clear all interrupts. */
> + writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
> +
> + writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
> +
> + reinit_completion(&cqspi->transfer_complete);
> + writel(CQSPI_REG_INDIRECTRD_START_MASK,
> + reg_base + CQSPI_REG_INDIRECTRD);
> +
> + while (remaining > 0) {
> + ret = wait_for_completion_timeout(&cqspi->transfer_complete,
> + msecs_to_jiffies
> + (CQSPI_READ_TIMEOUT_MS));
> +
> + bytes_to_read = cqspi_get_rd_sram_level(cqspi);
> +
> + if (!ret && bytes_to_read == 0) {
> + dev_err(nor->dev, "Indirect read timeout, no bytes\n");
> + ret = -ETIMEDOUT;
> + goto failrd;
> + }
> +
> + while (bytes_to_read != 0) {
> + bytes_to_read *= cqspi->fifo_width;
> + bytes_to_read = bytes_to_read > remaining ?
> + remaining : bytes_to_read;
> + readsl(ahb_base, rxbuf, DIV_ROUND_UP(bytes_to_read, 4));
> + rxbuf += bytes_to_read;
> + remaining -= bytes_to_read;
> + bytes_to_read = cqspi_get_rd_sram_level(cqspi);
> + }
> +
> + if (remaining > 0)
> + reinit_completion(&cqspi->transfer_complete);
> + }
> +
> + /* Check indirect done status */
> + ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
> + CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
> +
I was wondering if its better to use direct access mode[1]. With this
mode there is no need to wait for IRQ or monitor sdram level. By setting
up QSPI in direct access mode, this entire function can be replaced by:
memcpy(buf, cqspi->ahb_base + from, n_rx)
IMO, this might give better throughput. Have tested this mode?
[1] https://documentation.altera.com/#/00038604-AA$AA00045811
--
Regards
Vignesh
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next prev parent reply other threads:[~2016-06-14 5:10 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-04 0:39 [PATCH V8 1/2] mtd: spi-nor: Bindings for Cadence Quad SPI Flash Controller driver Marek Vasut
[not found] ` <1465000774-7762-1-git-send-email-marex-ynQEQJNshbs@public.gmane.org>
2016-06-04 0:39 ` [PATCH V12 2/2] mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller Marek Vasut
[not found] ` <1465000774-7762-2-git-send-email-marex-ynQEQJNshbs@public.gmane.org>
2016-06-14 5:10 ` Vignesh R [this message]
2016-06-14 12:59 ` Marek Vasut
[not found] ` <575FFF97.7040104-ynQEQJNshbs@public.gmane.org>
2016-06-16 6:43 ` Vignesh R
[not found] ` <57624A98.4060308-l0cyMroinI0@public.gmane.org>
2016-06-16 13:21 ` Marek Vasut
[not found] ` <5762A7E6.8000109-ynQEQJNshbs@public.gmane.org>
2016-06-17 4:43 ` Vignesh R
[not found] ` <57637FF1.9030802-l0cyMroinI0@public.gmane.org>
2016-06-17 9:09 ` Marek Vasut
2016-07-18 0:52 ` Brian Norris
[not found] ` <20160718005238.GA80196-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
2016-07-18 9:35 ` Marek Vasut
[not found] ` <be1a637c-7d86-df4e-0d47-8516ec639974-ynQEQJNshbs@public.gmane.org>
2016-07-18 16:58 ` Brian Norris
2016-07-18 17:02 ` Brian Norris
2016-06-07 14:00 ` [PATCH V8 1/2] mtd: spi-nor: Bindings for Cadence Quad SPI Flash Controller driver Rob Herring
2016-07-18 17:00 ` Brian Norris
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