Re: [PATCH V12 2/2] mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller

[Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>]

On 06/17/2016 06:43 AM, Vignesh R wrote:
> 
> 
> On Thursday 16 June 2016 06:51 PM, Marek Vasut wrote:
>> On 06/16/2016 08:43 AM, Vignesh R wrote:
> [...]
>>>> - I didn't find any way to find when all the data in the current 1 MiB
>>>>   block were written and you can remap another 1 MiB block in place.
>>>
>>> I believe this constraint only applies if enahbremap bit is set in cfg
>>> register, if not, then the entire memory map can be accessed.
>>
>> And where is that memory window accessible then, at which address ?
>> The SoCFPGA peripherals are stuffed in some 12 MiB of the address
>> space, the rest is bootrom/sram/ram and the FPGA bridges, so I find
>> it hard to believe you can place ie. 128 MiB SPI NOR mapping somewhere
>> in there.
>>
>> My impression is that in direct mode, the qspi will always overlay the
>> address 0x0 on socfpga , but that might be configurable , I'm not sure.
>>
> 
> Ah, socfgpa provides just 1MB window to access QSPI_DATA area. So direct
> mode may not be practical as it will require remapping.
> But, on TI EVM, QSPI_DATA area is 64MB in size, so looks like direct
> mode(when added) needs to be tied to TI specific compatible.
> 

Ah, so that explains it. Thanks for looking into it.

Still, keep in mind there are 128 MiB devices (N25Q00AA for example), so
even with the 64 MiB data area, it won't be entirely seamless.

-- 
Best regards,
Marek Vasut
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