Re: [RFC PATCH 11/13] arm64: tegra: Add SOR power-domain node

From: Jon Hunter <jonathanh@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	Alexandre Courbot <gnurou@gmail.com>,
	Wolfram Sang <wsa@the-dreams.de>,
	Stephen Warren <swarren@wwwdotorg.org>,
	dri-devel@lists.freedesktop.org, linux-gpio@vger.kernel.org,
	devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	linux-i2c@vger.kernel.org, linux-tegra@vger.kernel.org
Subject: Re: [RFC PATCH 11/13] arm64: tegra: Add SOR power-domain node
Date: Mon, 20 Jun 2016 10:20:45 +0100	[thread overview]
Message-ID: <5767B56D.7060901@nvidia.com> (raw)
In-Reply-To: <20160617164446.GK27475@ulmo.ba.sec>

On 17/06/16 17:44, Thierry Reding wrote:
> * PGP Signed by an unknown key
> 
> On Fri, Jun 17, 2016 at 01:03:45PM +0100, Jon Hunter wrote:
>> Add node for SOR power-domain for Tegra210 and populate the SOR
>> power-domain phandle for SOR and DPAUX nodes that are dependent
>> on this power-domain.
>>
>> Please note that although neither the SOR or DPAUX drivers currently
>> support runtime power-management, by populating the power-domain node
>> the SOR power-domain will be turned on before probing SOR or DPAUX
>> devices and kept on while the devices are bound.
>>
>> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
>> ---
>>  arch/arm64/boot/dts/nvidia/tegra210.dtsi | 18 ++++++++++++++++++
>>  1 file changed, 18 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
>> index ebf44f4059f8..94f780b43037 100644
>> --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
>> +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
>> @@ -34,6 +34,7 @@
>>  			clock-names = "dpaux", "parent";
>>  			resets = <&tegra_car 207>;
>>  			reset-names = "dpaux";
>> +			power-domains = <&pd_sor>;
>>  			status = "disabled";
>>  		};
>>  
>> @@ -154,6 +155,7 @@
>>  			clock-names = "sor", "parent", "dp", "safe";
>>  			resets = <&tegra_car 182>;
>>  			reset-names = "sor";
>> +			power-domains = <&pd_sor>;
>>  			status = "disabled";
>>  		};
>>  
>> @@ -168,6 +170,7 @@
>>  			clock-names = "sor", "parent", "dp", "safe";
>>  			resets = <&tegra_car 183>;
>>  			reset-names = "sor";
>> +			power-domains = <&pd_sor>;
>>  			status = "disabled";
>>  		};
>>  
>> @@ -180,6 +183,7 @@
>>  			clock-names = "dpaux", "parent";
>>  			resets = <&tegra_car 181>;
>>  			reset-names = "dpaux";
>> +			power-domains = <&pd_sor>;
>>  			status = "disabled";
>>  		};
>>  
>> @@ -592,6 +596,20 @@
>>  				resets = <&tegra_car 198>;
>>  				#power-domain-cells = <0>;
>>  			};
>> +
>> +			pd_sor: sor {
>> +				clocks = <&tegra_car TEGRA210_CLK_SOR0>,
>> +					 <&tegra_car TEGRA210_CLK_DSIA>,
>> +					 <&tegra_car TEGRA210_CLK_DSIB>,
>> +					 <&tegra_car TEGRA210_CLK_MIPI_CAL>,
> 
> Does this mean that all of these clocks will be running while the SOR
> partition is enabled? Seems like a waste because we rarely need MIPI_CAL
> and DSIA and DSIB are completely unused on boards that for example have
> only an HDMI output.
> 
> I vaguely remember the power domain driver only making sure these are
> enabled during the partition power transitions, so perhaps my concerns
> aren't justified?

Right, these are only enabled during the transition of the partition. So
the SOR driver still needs to enable the clocks it needs.

Cheers
Jon

-- 
nvpublic
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