From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jon Hunter Subject: Re: [RFC PATCH 12/13] arm64: tegra: Add sor-safe clock to DPAUX binding Date: Mon, 20 Jun 2016 10:23:38 +0100 Message-ID: <5767B61A.3090102@nvidia.com> References: <1466165027-17917-1-git-send-email-jonathanh@nvidia.com> <1466165027-17917-13-git-send-email-jonathanh@nvidia.com> <20160617164746.GM27475@ulmo.ba.sec> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20160617164746.GM27475@ulmo.ba.sec> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Thierry Reding Cc: Mark Rutland , Alexandre Courbot , Wolfram Sang , Stephen Warren , dri-devel@lists.freedesktop.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , linux-i2c@vger.kernel.org, linux-tegra@vger.kernel.org List-Id: devicetree@vger.kernel.org Ck9uIDE3LzA2LzE2IDE3OjQ3LCBUaGllcnJ5IFJlZGluZyB3cm90ZToKPiAqIFBHUCBTaWduZWQg YnkgYW4gdW5rbm93biBrZXkKPiAKPiBPbiBGcmksIEp1biAxNywgMjAxNiBhdCAwMTowMzo0NlBN ICswMTAwLCBKb24gSHVudGVyIHdyb3RlOgo+PiBQb3B1bGF0ZSB0aGUgJ3Nvci1zYWZlJyBjbG9j ayBmb3IgRFBBVVggZGV2aWNlcyBvbiBUZWdyYTIxMCB0aGF0IHJlcXVpcmUKPj4gdGhpcyBjbG9j ayBmb3Igb3BlcmF0aW9uLiBVcGRhdGUgdGhlIGNvbXBhdGFiaWxpdHkgc3RyaW5nIGZvciB0aGUg RFBBVVgKPj4gaW5zdGFuY2UgYXQgYWRkcmVzcyAweDU0NWMwMDAwIHRvIGJlICJudmlkaWEsdGVn cmEyMTAtZHBhdXgiIHRvIGVuc3VyZQo+PiB0aGF0IHRoZSAnc29yLXNhZmUnIGNsb2NrIGlzIGVu YWJsZWQgZm9yIHRoaXMgZGV2aWNlLgo+IAo+IERvZXMgdGhlIHNlY29uZCBEUEFVWCBuZWVkIHRo aXMsIHRvbz8gSSBoYXZlIGEgdmFndWUgcmVjb2xsZWN0aW9uIHRoYXQKPiB0aGV5IHdlcmUgYm90 aCBzbGlnaHRseSBkaWZmZXJlbnQuCgpJIGhhdmUgYXNzdW1lZCBzbywgYnV0IEkgYW0gY2hlY2tp bmcgd2l0aCB0aGUgaC93IGZvbGtzIG9uIHRoaXMuIFJpZ2h0Cm5vdyB0aGUgVFJNIG9ubHkgZGVz Y3JpYmVzIHRoZSBwcm9jZWR1cmUgZm9yIGNvbmZpZ3VyaW5nIHRoZSBEUEFVWCBwYWRzCmZvciBp MmM2LiBJIGFtIGFsc28gYXNraW5nIGFib3V0IHNoYXJpbmcgdGhlIERQQVVYMSBwYWRzIHdpdGgg aTJjNC4KCkNoZWVycwpKb24KCi0tIApudnB1YmxpYwpfX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBs aXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1h bi9saXN0aW5mby9kcmktZGV2ZWwK