From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Subject: Re: [PATCH] ARM: tegra: add DT binding for Tegra186 BPMP I2C Date: Mon, 18 Jul 2016 10:16:27 -0600 Message-ID: <578D00DB.4080307@wwwdotorg.org> References: <20160707193711.5891-1-swarren@wwwdotorg.org> <20160716210728.GA22144@rob-hp-laptop> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20160716210728.GA22144@rob-hp-laptop> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Rob Herring Cc: Thierry Reding , Mark Rutland , Wolfram Sang , Alexandre Courbot , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Stephen Warren List-Id: devicetree@vger.kernel.org On 07/16/2016 03:07 PM, Rob Herring wrote: > On Thu, Jul 07, 2016 at 01:37:11PM -0600, Stephen Warren wrote: >> From: Stephen Warren >> >> In Tegra186, the BPMP (Boot and Power Management Processor) owns certain >> HW devices, such as the I2C controller for the power management I2C bus. >> Software running on other CPUs must perform IPC to the BPMP in order to >> execute transactions on that I2C bus. This binding describes an I2C bus >> that is accessed in such a fashion. >> >> Signed-off-by: Stephen Warren >> --- >> .../bindings/i2c/nvidia,tegra186-bpmp-i2c.txt | 35 ++++++++++++++++++++++ >> 1 file changed, 35 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt >> >> diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt >> new file mode 100644 >> index 000000000000..eb9f70723ab7 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt >> @@ -0,0 +1,35 @@ >> +NVIDIA Tegra186 BPMP I2C controller >> + >> +In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW >> +devices, such as the I2C controller for the power management I2C bus. Software >> +running on other CPUs must perform IPC to the BPMP in order to execute >> +transactions on that I2C bus. This binding describes an I2C bus that is >> +accessed in such a fashion. >> + >> +Required properties: >> +- compatible: >> + Array of strings. >> + One of: >> + - "nvidia,tegra186-bpmp-i2c". >> +- address-cells: Address cells for I2C device address. >> + Single-cell integer. >> + Must be <1>. >> +- size-cells: >> + Single-cell integer. >> + Must be <0>. >> +- nvidia,bpmp: >> + The phandle to the BPMP device. > > Any reason to not make this a sub-node of the BPMP device? That would be possible too. My thought process was along the lines of: The system has an I2C bus, which deserves a DT node. That fact seemed more important than the access mechanism; the fact it's accessed via BPMP rather than direct register access felt a bit more like an implementation detail. Still, I suppose we could flip it around and store the node underneath the BPMP if you want; let me know.