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Mon, 24 Aug 2026 01:56:12 -0700 (PDT) X-Received: by 2002:a05:6102:6893:b0:6d1:8f7:18a5 with SMTP id ada2fe7eead31-77a6433632emr3278073137.1.1787561772378; Mon, 24 Aug 2026 01:56:12 -0700 (PDT) Received: from [192.168.120.193] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6a59e1ae4efsm6945619a12.21.2026.08.24.01.56.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Aug 2026 01:56:11 -0700 (PDT) Message-ID: <57c9495a-45de-43d0-8ab3-4dc8f42712c5@oss.qualcomm.com> Date: Mon, 24 Aug 2026 10:56:07 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 13/13] arm64: dts: qcom: Add SM7250 devicetree file To: Sreeshankar K , robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, tglx@kernel.org, ulfh@kernel.org Cc: bmasney@redhat.com, radu@rendec.net, abel.vesa@oss.qualcomm.com, lpieralisi@kernel.org, quic_tdas@quicinc.com, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org References: <20260821154030.2514-1-sreeshankar0910@gmail.com> <20260821154030.2514-14-sreeshankar0910@gmail.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260821154030.2514-14-sreeshankar0910@gmail.com> Content-Type: text/plain; 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> + domain-idle-states = <&cluster_sleep_pc > + &cluster_sleep_cx > + &cluster_sleep_aoss>; nit: <&foo>, <&bar>, ... (compiles to the same bytecode) [...] > + soc: soc@0 { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0 0 0 0 0x10 0>; > + dma-ranges = <0 0 0 0 0x10 0>; > + compatible = "simple-bus"; compatible should come first > + > + gcc: clock-controller@100000 { > + compatible = "qcom,sm7250-gcc"; > + reg = <0x0 0x00100000 0x0 0x1f0000>; > + clock-names = "bi_tcxo", > + "bi_tcxo_ao", > + "sleep_clk"; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&rpmhcc RPMH_CXO_CLK_A>, > + <&sleep_clk>; > + power-domains = <&rpmhpd RPMHPD_CX>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > + qupv3_id_1: geniqup@9c0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0x0 0x009c0000 0x0 0x6000>; > + clock-names = "m-ahb", "s-ahb"; > + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + status = "disabled"; I think this wrapper can be enabled globally > + > + uart2: serial@988000 { > + compatible = "qcom,geni-debug-uart"; > + reg = <0 0x00988000 0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; > + interrupts = ; > + status = "disabled"; > + }; > + }; > + > + intc: interrupt-controller@17a00000 { > + compatible = "arm,gic-v3"; > + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ > + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ > + #interrupt-cells = <3>; > + interrupt-controller; > + interrupts = ; > + }; > + > + pdc: interrupt-controller@b220000 { > + compatible = "qcom,sm7250-pdc", "qcom,pdc"; > + reg = <0 0xb220000 0 0x30000>, <0 0x17c000f0 0 0x60>; > + qcom,pdc-ranges = <0 480 42>, <42 612 28>, > + <70 63 1>, <71 640 15>, <86 522 52>; 1 a line, please > + #interrupt-cells = <2>; > + interrupt-parent = <&intc>; > + interrupt-controller; > + }; > + > + spmi_bus: spmi@c440000 { > + compatible = "qcom,spmi-pmic-arb"; > + reg = <0x0 0x0c440000 0x0 0x0001100>, > + <0x0 0x0c600000 0x0 0x2000000>, > + <0x0 0x0e600000 0x0 0x0100000>, > + <0x0 0x0e700000 0x0 0x00a0000>, > + <0x0 0x0c40a000 0x0 0x0026000>; > + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; and here [...] > + apps_rsc: rsc@18200000 { > + compatible = "qcom,rpmh-rsc"; > + reg = <0x0 0x18200000 0x0 0x10000>, > + <0x0 0x18210000 0x0 0x10000>, > + <0x0 0x18220000 0x0 0x10000>; > + reg-names = "drv-0", "drv-1", "drv-2"; and here [...] > + cpufreq_hw: cpufreq@18323000 { > + compatible = "qcom,sm7250-cpufreq-hw", "qcom,cpufreq-hw"; > + reg = <0 0x18323000 0 0x1000>, > + <0 0x18325800 0 0x1000>, > + <0 0x18327800 0 0x1000>; > + reg-names = "freq-domain0", "freq-domain1", > + "freq-domain2"; and here > + > + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; > + clock-names = "xo", "alternate"; > + #freq-domain-cells = <1>; > + #clock-cells = <1>; > + }; > + > + tcsr_mutex: hwlock@1f40000 { > + compatible = "qcom,tcsr-mutex"; > + reg = <0x0 0x01f40000 0x0 0x40000>; > + #hwlock-cells = <1>; > + }; > + > + timer@17c20000 { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + compatible = "arm,armv7-timer-mem"; Compatible should come as the first property > + reg = <0x0 0x17c20000 0x0 0x1000>; > + clock-frequency = <19200000>; This line should not be necessary Konrad