* [PATCH 1/2] ARM: dts: Fix SPI node for Arria10
@ 2018-05-29 18:08 thor.thayer
2018-05-29 18:08 ` [PATCH 2/2] ARM: dts: Add SPI0 " thor.thayer
2018-06-21 18:27 ` [PATCH 1/2] ARM: dts: Fix SPI " Thor Thayer
0 siblings, 2 replies; 4+ messages in thread
From: thor.thayer @ 2018-05-29 18:08 UTC (permalink / raw)
To: dinguyen; +Cc: robh+dt, mark.rutland, devicetree, Thor Thayer, stable
From: Thor Thayer <thor.thayer@linux.intel.com>
Remove the unused bus-num node and change num-chipselect
to num-cs to match SPI bindings.
Fixes: f2d6f8f817814 ("ARM: dts: socfpga: Add SPI Master1 for Arria10 SR chip")
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Cc: stable@vger.kernel.org
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index bead79e4b2aa..9138f834bad4 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -593,8 +593,7 @@
#size-cells = <0>;
reg = <0xffda5000 0x100>;
interrupts = <0 102 4>;
- num-chipselect = <4>;
- bus-num = <0>;
+ num-cs = <4>;
/*32bit_access;*/
tx-dma-channel = <&pdma 16>;
rx-dma-channel = <&pdma 17>;
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] ARM: dts: Add SPI0 node for Arria10
2018-05-29 18:08 [PATCH 1/2] ARM: dts: Fix SPI node for Arria10 thor.thayer
@ 2018-05-29 18:08 ` thor.thayer
2018-06-21 18:27 ` [PATCH 1/2] ARM: dts: Fix SPI " Thor Thayer
1 sibling, 0 replies; 4+ messages in thread
From: thor.thayer @ 2018-05-29 18:08 UTC (permalink / raw)
To: dinguyen; +Cc: robh+dt, mark.rutland, devicetree, Thor Thayer
From: Thor Thayer <thor.thayer@linux.intel.com>
Add the SPI0 node for Arria10.
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 9138f834bad4..ee9a5fc616a8 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -587,6 +587,18 @@
status = "disabled";
};
+ spi0: spi@ffda4000 {
+ compatible = "snps,dw-apb-ssi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xffda4000 0x100>;
+ interrupts = <0 101 4>;
+ num-cs = <4>;
+ /*32bit_access;*/
+ clocks = <&spi_m_clk>;
+ status = "disabled";
+ };
+
spi1: spi@ffda5000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] ARM: dts: Fix SPI node for Arria10
2018-05-29 18:08 [PATCH 1/2] ARM: dts: Fix SPI node for Arria10 thor.thayer
2018-05-29 18:08 ` [PATCH 2/2] ARM: dts: Add SPI0 " thor.thayer
@ 2018-06-21 18:27 ` Thor Thayer
2018-06-22 18:54 ` Dinh Nguyen
1 sibling, 1 reply; 4+ messages in thread
From: Thor Thayer @ 2018-06-21 18:27 UTC (permalink / raw)
To: dinguyen; +Cc: robh+dt, mark.rutland, devicetree, stable
Hi Dinh,
On 05/29/2018 01:08 PM, thor.thayer@linux.intel.com wrote:
> From: Thor Thayer <thor.thayer@linux.intel.com>
>
> Remove the unused bus-num node and change num-chipselect
> to num-cs to match SPI bindings.
>
> Fixes: f2d6f8f817814 ("ARM: dts: socfpga: Add SPI Master1 for Arria10 SR chip")
> Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
> Cc: stable@vger.kernel.org
> ---
> arch/arm/boot/dts/socfpga_arria10.dtsi | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
> index bead79e4b2aa..9138f834bad4 100644
> --- a/arch/arm/boot/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
> @@ -593,8 +593,7 @@
> #size-cells = <0>;
> reg = <0xffda5000 0x100>;
> interrupts = <0 102 4>;
> - num-chipselect = <4>;
> - bus-num = <0>;
> + num-cs = <4>;
> /*32bit_access;*/
> tx-dma-channel = <&pdma 16>;
> rx-dma-channel = <&pdma 17>;
>
Any update on this patch?
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] ARM: dts: Fix SPI node for Arria10
2018-06-21 18:27 ` [PATCH 1/2] ARM: dts: Fix SPI " Thor Thayer
@ 2018-06-22 18:54 ` Dinh Nguyen
0 siblings, 0 replies; 4+ messages in thread
From: Dinh Nguyen @ 2018-06-22 18:54 UTC (permalink / raw)
To: thor.thayer; +Cc: robh+dt, mark.rutland, devicetree, stable
On 06/21/2018 01:27 PM, Thor Thayer wrote:
> Hi Dinh,
>
> On 05/29/2018 01:08 PM, thor.thayer@linux.intel.com wrote:
>> From: Thor Thayer <thor.thayer@linux.intel.com>
>>
>> Remove the unused bus-num node and change num-chipselect
>> to num-cs to match SPI bindings.
>>
>> Fixes: f2d6f8f817814 ("ARM: dts: socfpga: Add SPI Master1 for Arria10
>> SR chip")
>> Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
>> Cc: stable@vger.kernel.org
>> ---
>> arch/arm/boot/dts/socfpga_arria10.dtsi | 3 +--
>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi
>> b/arch/arm/boot/dts/socfpga_arria10.dtsi
>> index bead79e4b2aa..9138f834bad4 100644
>> --- a/arch/arm/boot/dts/socfpga_arria10.dtsi
>> +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
>> @@ -593,8 +593,7 @@
>> #size-cells = <0>;
>> reg = <0xffda5000 0x100>;
>> interrupts = <0 102 4>;
>> - num-chipselect = <4>;
>> - bus-num = <0>;
>> + num-cs = <4>;
>> /*32bit_access;*/
>> tx-dma-channel = <&pdma 16>;
>> rx-dma-channel = <&pdma 17>;
>>
> Any update on this patch?
I've applied both patches.
Thanks,
Dinh
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-06-22 18:54 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-05-29 18:08 [PATCH 1/2] ARM: dts: Fix SPI node for Arria10 thor.thayer
2018-05-29 18:08 ` [PATCH 2/2] ARM: dts: Add SPI0 " thor.thayer
2018-06-21 18:27 ` [PATCH 1/2] ARM: dts: Fix SPI " Thor Thayer
2018-06-22 18:54 ` Dinh Nguyen
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).