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AJvYcCVisJno+v0VtiCFGLa/db9hVPBNVSKPyfHaUvNpq6hTNuOHjfuOBCJ7Xx4Y695KqxNaByVEmHEB4jpTKdK+O+CWueqfJLEtCptwiQ== X-Gm-Message-State: AOJu0Yyyzba7sFVuJTBptFrXkGEgFko/E+KHHWgKsRZ5bRuRIJSY79c7 zmO+kvJzYlX6nTHUCw1WnvnzCwe37MsLioknq1tTO4nK/xwgZ+2Mc1VD+NqgbEk= X-Google-Smtp-Source: AGHT+IHvPxH1nBAWvxsjHSCNyZ9t61rhyU1cxyB6YJQEzy0OWWC+/dfZi6vmuDEorYBOF0SyCrzU7w== X-Received: by 2002:a2e:3c16:0:b0:2ec:4d48:75f3 with SMTP id 38308e7fff4ca-2eeb3198617mr74112911fa.45.1720796091727; Fri, 12 Jul 2024 07:54:51 -0700 (PDT) Received: from draszik.lan ([80.111.64.44]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-367cde8491dsm10421734f8f.45.2024.07.12.07.54.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Jul 2024 07:54:51 -0700 (PDT) Message-ID: <58e355454db3670157645c0b6e727d8058ef0324.camel@linaro.org> Subject: Re: [PATCH v3 1/2] dt-bindings: serial: samsung: fix maxItems for gs101 & document earlycon requirements From: =?ISO-8859-1?Q?Andr=E9?= Draszik To: Rob Herring Cc: Greg Kroah-Hartman , Jiri Slaby , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Sam Protsenko , Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Date: Fri, 12 Jul 2024 15:54:50 +0100 In-Reply-To: <20240711212359.GA3023490-robh@kernel.org> References: <20240710-gs101-non-essential-clocks-2-v3-0-5dcb8d040d1c@linaro.org> <20240710-gs101-non-essential-clocks-2-v3-1-5dcb8d040d1c@linaro.org> <20240711212359.GA3023490-robh@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.50.3-1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Rob, On Thu, 2024-07-11 at 15:23 -0600, Rob Herring wrote: > On Thu, Jul 11, 2024 at 05:09:50PM +0100, Andr=C3=A9 Draszik wrote: > > Hi Rob, > >=20 > > On Thu, 2024-07-11 at 09:51 -0600, Rob Herring wrote: > > > On Wed, Jul 10, 2024 at 7:29=E2=80=AFAM Andr=C3=A9 Draszik wrote: > > > > --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml > > > > +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml > > > > @@ -145,6 +145,20 @@ allOf: > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - samsung,uart-fif= osize > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 properties: > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 reg-io-width: fals= e > > >=20 > > > blank line between properties > >=20 > > Do mean before clocks: below and before clock-names: below?=20 >=20 > Yes. >=20 > > We don't do that normally, > > at least none of the bindings I looked at do that. Or did I misundersta= nd? >=20 > That style is pretty universal. If in doubt, look at example-schema.yaml= =20 > for best practices. The exception is only for cases like this: >=20 > =C2=A0 foo: true > =C2=A0 bar: true example-schema.yaml doesn't have an example for that, so I suspect that's w= hy many (Samsung?) bindings ended up without the blank line. I have fixed it f= or this schema in the next version in https://lore.kernel.org/all/20240712-gs101-uart-binding-v4-1-24e9f8d4bdcb@l= inaro.org/ > > >=20 > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 maxItems: 2 > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 clock-names: > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 items: > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= - const: uart > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= - const: clk_uart_baud0 > > >=20 > > > Which clock is pclk and ipclk? > >=20 > > uart is pclk, clk_uart_baud0 is ipclk. > >=20 > > > 'baud' would be sufficient for the > > > name. 'clk_' and 'uart' are redundant because it's all clocks and the= y > > > are all for the uart. > >=20 > > TBH, this patch is just following the existing style & names as already= exist for > > various other SoCs in this same file. Furthermore, up until this patch = the default > > from this file applies, which is: > >=20 > > =C2=A0 clock-names: > > =C2=A0=C2=A0=C2=A0 description: N =3D 0 is allowed for SoCs without int= ernal baud clock mux. > > =C2=A0=C2=A0=C2=A0 minItems: 2 > > =C2=A0=C2=A0=C2=A0 items: > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - const: uart > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - pattern: '^clk_uart_baud[0-3]$' > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - pattern: '^clk_uart_baud[0-3]$' > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - pattern: '^clk_uart_baud[0-3]$' > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - pattern: '^clk_uart_baud[0-3]$' >=20 > Then don't duplicate it. Ideally, the names are defined at the top level= =20 > and the conditional schema just limits the number of clocks, and this is= =20 > an example of why we want it that way. I have no context to see if this= =20 > is consistent or not. I've fixed it in https://lore.kernel.org/all/20240712-gs101-uart-binding-v4= -1-24e9f8d4bdcb@linaro.org/ Hopefully you'll that's more acceptable :-) Cheers, Andre'