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From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Johan Hovold <johan@kernel.org>
Cc: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Jingoo Han <jingoohan1@gmail.com>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Stanimir Varbanov <svarbanov@mm-sol.com>,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
	Vinod Koul <vkoul@kernel.org>,
	linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, Rob Herring <robh@kernel.org>,
	Johan Hovold <johan+linaro@kernel.org>
Subject: Re: [PATCH v13 4/7] PCI: dwc: Handle MSIs routed to multiple GIC interrupts
Date: Wed, 8 Jun 2022 11:58:46 +0300	[thread overview]
Message-ID: <58f1282d-3c13-59b3-84e6-0cf39f846dd1@linaro.org> (raw)
In-Reply-To: <Yp4q5S7WIYbYEdHc@hovoldconsulting.com>

On 06/06/2022 19:27, Johan Hovold wrote:
> On Fri, Jun 03, 2022 at 10:41:34AM +0300, Dmitry Baryshkov wrote:
>> On some of Qualcomm platforms each group of 32 MSI vectors is routed to the
>> separate GIC interrupt. Implement support for such configurations by
>> parsing "msi0" ... "msiN" interrupts and attaching them to the chained
>> handler.
>>
>> Note, that if DT doesn't list an array of MSI interrupts and uses single
>> "msi" IRQ, the driver will limit the amount of supported MSI vectors
>> accordingly (to 32).
>>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>>   .../pci/controller/dwc/pcie-designware-host.c | 63 +++++++++++++++++--
>>   1 file changed, 59 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
>> index 85c1160792e1..d1f9e20df903 100644
>> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
>> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
>> @@ -289,6 +289,46 @@ static void dw_pcie_msi_init(struct pcie_port *pp)
>>   	dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
>>   }
>>   
>> +static int dw_pcie_parse_split_msi_irq(struct pcie_port *pp)
>> +{
>> +	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> +	struct device *dev = pci->dev;
>> +	struct platform_device *pdev = to_platform_device(dev);
>> +	int irq;
>> +	u32 ctrl, max_vectors;
>> +
>> +	/* Parse as many IRQs as described in the devicetree. */
>> +	for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {
>> +		char *msi_name = "msiX";
>> +
>> +		msi_name[3] = '0' + ctrl;
> 
> This oopses here as the string constant is read only:
> 
> 	[   19.787973] Unable to handle kernel write to read-only memory at virtual address ffffaa14f831afd3
> 
> Did you not test the series before posting?

Interesting enough the posted series works for me. Maybe I have a 
different set of debugging options. But thanks for spotting this. I'll 
post v14.

> 
> You need to define msi_name as:
> 
> 	char msi_name[] = "msiX";
> 
>> +		irq = platform_get_irq_byname_optional(pdev, msi_name);
>> +		if (irq == -ENXIO)
>> +			break;
>> +		if (irq < 0)
>> +			return dev_err_probe(dev, irq,
>> +					     "Failed to parse MSI IRQ '%s'\n",
>> +					     msi_name);
>> +
>> +		pp->msi_irq[ctrl] = irq;
>> +	}
> 
> Johan


-- 
With best wishes
Dmitry

  reply	other threads:[~2022-06-08  9:36 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-03  7:41 [PATCH v13 0/7] PCI: dwc: Fix higher MSI vectors handling Dmitry Baryshkov
2022-06-03  7:41 ` [PATCH v13 1/7] PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi() Dmitry Baryshkov
2022-06-03  7:41 ` [PATCH v13 2/7] PCI: dwc: Convert msi_irq to the array Dmitry Baryshkov
2022-06-03  7:41 ` [PATCH v13 3/7] PCI: dwc: split MSI IRQ parsing/allocation to a separate function Dmitry Baryshkov
2022-06-03  7:41 ` [PATCH v13 4/7] PCI: dwc: Handle MSIs routed to multiple GIC interrupts Dmitry Baryshkov
2022-06-06 16:27   ` Johan Hovold
2022-06-08  8:58     ` Dmitry Baryshkov [this message]
2022-06-03  7:41 ` [PATCH v13 5/7] dt-bindings: PCI: qcom: Support additional MSI interrupts Dmitry Baryshkov
2022-06-03  7:41 ` [PATCH v13 6/7] arm64: dts: qcom: sm8250: provide " Dmitry Baryshkov
2022-06-03  7:41 ` [PATCH v13 7/7] PCI: qcom: Revert "PCI: qcom: Add support for handling MSIs from 8 endpoints" Dmitry Baryshkov

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