From: "Jernej Škrabec" <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
To: Maxime Ripard <maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org>
Cc: wens-jdAy2FN1RRM@public.gmane.org,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
Subject: Re: [PATCH 05/15] drm/sun4i: Add TCON TOP driver
Date: Mon, 21 May 2018 17:15:15 +0200 [thread overview]
Message-ID: <5965231.6ucpJrPIQ5@jernej-laptop> (raw)
In-Reply-To: <20180521080517.3qmlfajqpn4uw7jv@flea>
Hi,
Dne ponedeljek, 21. maj 2018 ob 10:05:17 CEST je Maxime Ripard napisal(a):
> On Sat, May 19, 2018 at 08:31:17PM +0200, Jernej Skrabec wrote:
> > As already described in DT binding, TCON TOP is responsible for
> > configuring display pipeline. In this initial driver focus is on HDMI
> > pipeline, so TVE and LCD configuration is not implemented.
> >
> > Implemented features:
> > - HDMI source selection
> > - clock driver (TCON and DSI gating)
> > - connecting mixers and TCONS
> >
> > Something similar also existed in previous SoCs, except that it was part
> > of first TCON.
> >
> > Signed-off-by: Jernej Skrabec <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
> > ---
> >
> > drivers/gpu/drm/sun4i/Makefile | 3 +-
> > drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 256 +++++++++++++++++++++
> > drivers/gpu/drm/sun4i/sun8i_tcon_top.h | 20 ++
> > include/dt-bindings/clock/sun8i-tcon-top.h | 11 +
> > 4 files changed, 289 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > create mode 100644 drivers/gpu/drm/sun4i/sun8i_tcon_top.h
> > create mode 100644 include/dt-bindings/clock/sun8i-tcon-top.h
> >
> > diff --git a/drivers/gpu/drm/sun4i/Makefile
> > b/drivers/gpu/drm/sun4i/Makefile index 2589f4acd5ae..09fbfd6304ba 100644
> > --- a/drivers/gpu/drm/sun4i/Makefile
> > +++ b/drivers/gpu/drm/sun4i/Makefile
> > @@ -16,7 +16,8 @@ sun8i-drm-hdmi-y += sun8i_hdmi_phy_clk.o
> >
> > sun8i-mixer-y += sun8i_mixer.o sun8i_ui_layer.o \
> >
> > sun8i_vi_layer.o sun8i_ui_scaler.o \
> >
> > - sun8i_vi_scaler.o sun8i_csc.o
> > + sun8i_vi_scaler.o sun8i_csc.o \
> > + sun8i_tcon_top.o
> >
> > sun4i-tcon-y += sun4i_crtc.o
> > sun4i-tcon-y += sun4i_dotclock.o
> >
> > diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c new file mode 100644
> > index 000000000000..075a356a6dfa
> > --- /dev/null
> > +++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > @@ -0,0 +1,256 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/* Copyright (c) 2018 Jernej Skrabec <jernej.skrabec-gGgVlfcn5nU@public.gmane.org> */
> > +
> > +#include <drm/drmP.h>
> > +
> > +#include <dt-bindings/clock/sun8i-tcon-top.h>
> > +
> > +#include <linux/bitfield.h>
> > +#include <linux/clk.h>
> > +#include <linux/clk-provider.h>
> > +#include <linux/module.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/reset.h>
> > +#include <linux/spinlock.h>
> > +
> > +#include "sun8i_tcon_top.h"
> > +
> > +#define TCON_TOP_PORT_SEL_REG 0x1C
> > +#define TCON_TOP_PORT_DE0_MSK GENMASK(1, 0)
> > +#define TCON_TOP_PORT_DE1_MSK GENMASK(5, 4)
> > +#define TCON_TOP_PORT_TCON_LCD0 0
> > +#define TCON_TOP_PORT_TCON_LCD1 1
> > +#define TCON_TOP_PORT_TCON_TV0 2
> > +#define TCON_TOP_PORT_TCON_TV1 3
> > +
> > +#define TCON_TOP_GATE_SRC_REG 0x20
> > +#define TCON_TOP_HDMI_SRC_MSK GENMASK(29, 28)
> > +#define TCON_TOP_HDMI_SRC_NONE 0
> > +#define TCON_TOP_HDMI_SRC_TCON_TV0 1
> > +#define TCON_TOP_HDMI_SRC_TCON_TV1 2
> > +#define TCON_TOP_TCON_TV1_GATE 24
> > +#define TCON_TOP_TCON_TV0_GATE 20
> > +#define TCON_TOP_TCON_DSI_GATE 16
> > +
> > +#define CLK_NUM 3
> > +
> > +struct sun8i_tcon_top {
> > + struct clk *bus;
> > + void __iomem *regs;
> > + struct reset_control *rst;
> > +
> > + /*
> > + * spinlock is used for locking access to registers from different
> > + * places - tcon driver and clk subsystem.
> > + */
> > + spinlock_t reg_lock;
> > +};
> > +
> > +struct sun8i_tcon_top_gate {
> > + const char *name;
> > + u8 bit;
> > + int index;
> > +};
> > +
> > +static const struct sun8i_tcon_top_gate gates[] = {
> > + {"bus-tcon-top-dsi", TCON_TOP_TCON_DSI_GATE, CLK_BUS_TCON_TOP_DSI},
> > + {"bus-tcon-top-tv0", TCON_TOP_TCON_TV0_GATE, CLK_BUS_TCON_TOP_TV0},
> > + {"bus-tcon-top-tv1", TCON_TOP_TCON_TV1_GATE, CLK_BUS_TCON_TOP_TV1},
> > +};
> > +
> > +void sun8i_tcon_top_set_hdmi_src(struct sun8i_tcon_top *tcon_top, int
> > tcon) +{
> > + unsigned long flags;
> > + u32 val;
> > +
> > + if (tcon > 1) {
> > + DRM_ERROR("TCON index is too high!\n");
> > + return;
> > + }
> > +
> > + spin_lock_irqsave(&tcon_top->reg_lock, flags);
> > +
> > + val = readl(tcon_top->regs + TCON_TOP_GATE_SRC_REG);
> > + val &= ~TCON_TOP_HDMI_SRC_MSK;
> > + val |= FIELD_PREP(TCON_TOP_HDMI_SRC_MSK,
> > + TCON_TOP_HDMI_SRC_TCON_TV0 + tcon);
> > + writel(val, tcon_top->regs + TCON_TOP_GATE_SRC_REG);
> > +
> > + spin_unlock_irqrestore(&tcon_top->reg_lock, flags);
> > +}
> > +
> > +void sun8i_tcon_top_de_config(struct sun8i_tcon_top *tcon_top,
> > + int mixer, enum tcon_type tcon_type, int tcon)
> > +{
> > + unsigned long flags;
> > + u32 val, reg;
> > +
> > + if (mixer > 1) {
> > + DRM_ERROR("Mixer index is too high!\n");
> > + return;
> > + }
> > +
> > + if (tcon > 1) {
> > + DRM_ERROR("TCON index is too high!\n");
> > + return;
> > + }
> > +
> > + switch (tcon_type) {
> > + case tcon_type_lcd:
> > + val = TCON_TOP_PORT_TCON_LCD0 + tcon;
> > + break;
> > + case tcon_type_tv:
> > + val = TCON_TOP_PORT_TCON_TV0 + tcon;
> > + break;
> > + default:
> > + DRM_ERROR("Invalid TCON type!\n");
> > + return;
> > + }
> > +
> > + spin_lock_irqsave(&tcon_top->reg_lock, flags);
> > +
> > + reg = readl(tcon_top->regs + TCON_TOP_PORT_SEL_REG);
> > + if (mixer == 0) {
> > + reg &= ~TCON_TOP_PORT_DE0_MSK;
> > + reg |= FIELD_PREP(TCON_TOP_PORT_DE0_MSK, val);
> > + } else {
> > + reg &= ~TCON_TOP_PORT_DE1_MSK;
> > + reg |= FIELD_PREP(TCON_TOP_PORT_DE1_MSK, val);
> > + }
> > + writel(reg, tcon_top->regs + TCON_TOP_PORT_SEL_REG);
> > +
> > + spin_unlock_irqrestore(&tcon_top->reg_lock, flags);
> > +}
> > +
> > +static int sun8i_tcon_top_probe(struct platform_device *pdev)
> > +{
> > + struct clk_hw_onecell_data *clk_data;
> > + struct sun8i_tcon_top *tcon_top;
> > + struct device *dev = &pdev->dev;
> > + struct resource *res;
> > + int ret, i;
> > +
> > + tcon_top = devm_kzalloc(dev, sizeof(*tcon_top), GFP_KERNEL);
> > + if (!tcon_top)
> > + return -ENOMEM;
> > +
> > + clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data) +
> > + sizeof(*clk_data->hws) * CLK_NUM,
> > + GFP_KERNEL);
> > + if (!clk_data)
> > + return -ENOMEM;
> > +
> > + spin_lock_init(&tcon_top->reg_lock);
> > +
> > + tcon_top->rst = devm_reset_control_get(dev, "rst");
> > + if (IS_ERR(tcon_top->rst)) {
> > + dev_err(dev, "Couldn't get our reset line\n");
> > + return PTR_ERR(tcon_top->rst);
> > + }
> > +
> > + tcon_top->bus = devm_clk_get(dev, "bus");
> > + if (IS_ERR(tcon_top->bus)) {
> > + dev_err(dev, "Couldn't get the bus clock\n");
> > + return PTR_ERR(tcon_top->bus);
> > + }
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + tcon_top->regs = devm_ioremap_resource(dev, res);
> > + if (IS_ERR(tcon_top->regs))
> > + return PTR_ERR(tcon_top->regs);
> > +
> > + ret = reset_control_deassert(tcon_top->rst);
> > + if (ret) {
> > + dev_err(dev, "Could not deassert ctrl reset control\n");
> > + return ret;
> > + }
> > +
> > + ret = clk_prepare_enable(tcon_top->bus);
> > + if (ret) {
> > + dev_err(dev, "Could not enable bus clock\n");
> > + goto err_assert_reset;
> > + }
> > +
> > + /*
> > + * Default register values might have some reserved bits set, which
> > + * prevents TCON TOP from working properly. Set them to 0 here.
> > + */
> > + writel(0, tcon_top->regs + TCON_TOP_PORT_SEL_REG);
> > + writel(0, tcon_top->regs + TCON_TOP_GATE_SRC_REG);
> > +
> > + for (i = 0; i < CLK_NUM; i++) {
> > + const char *parent_name = "bus-tcon-top";
>
> I guess retrieving the parent's clock name at runtime would be more
> flexible.
>
It is, but will it ever be anything else?
> > + struct clk_init_data init;
> > + struct clk_gate *gate;
> > +
> > + gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
> > + if (!gate) {
> > + ret = -ENOMEM;
> > + goto err_disable_clock;
> > + }
> > +
> > + init.name = gates[i].name;
> > + init.ops = &clk_gate_ops;
> > + init.flags = CLK_IS_BASIC;
> > + init.parent_names = &parent_name;
> > + init.num_parents = 1;
> > +
> > + gate->reg = tcon_top->regs + TCON_TOP_GATE_SRC_REG;
> > + gate->bit_idx = gates[i].bit;
> > + gate->lock = &tcon_top->reg_lock;
> > + gate->hw.init = &init;
> > +
> > + ret = devm_clk_hw_register(dev, &gate->hw);
> > + if (ret)
> > + goto err_disable_clock;
>
> Isn't it what clk_hw_register_gate is doing?
>
Almost, but not exactly. My goal was to use devm_* functions, so there is no
need to do any special cleanup.
> > + clk_data->hws[gates[i].index] = &gate->hw;
> > + }
> > +
> > + clk_data->num = CLK_NUM;
> > +
> > + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
clk_data);
> > + if (ret)
> > + goto err_disable_clock;
> > +
> > + platform_set_drvdata(pdev, tcon_top);
> > +
> > + return 0;
> > +
> > +err_disable_clock:
> > + clk_disable_unprepare(tcon_top->bus);
> > +err_assert_reset:
> > + reset_control_assert(tcon_top->rst);
> > +
> > + return ret;
> > +}
> > +
> > +static int sun8i_tcon_top_remove(struct platform_device *pdev)
> > +{
> > + struct sun8i_tcon_top *tcon_top = platform_get_drvdata(pdev);
> > +
> > + clk_disable_unprepare(tcon_top->bus);
> > + reset_control_assert(tcon_top->rst);
> > +
> > + return 0;
> > +}
> > +
> > +const struct of_device_id sun8i_tcon_top_of_table[] = {
> > + { .compatible = "allwinner,sun8i-r40-tcon-top" },
> > + { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, sun8i_tcon_top_of_table);
> > +
> > +static struct platform_driver sun8i_tcon_top_platform_driver = {
> > + .probe = sun8i_tcon_top_probe,
> > + .remove = sun8i_tcon_top_remove,
> > + .driver = {
> > + .name = "sun8i-tcon-top",
> > + .of_match_table = sun8i_tcon_top_of_table,
> > + },
> > +};
> > +module_platform_driver(sun8i_tcon_top_platform_driver);
> > +
> > +MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>");
> > +MODULE_DESCRIPTION("Allwinner R40 TCON TOP driver");
> > +MODULE_LICENSE("GPL");
> > diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.h
> > b/drivers/gpu/drm/sun4i/sun8i_tcon_top.h new file mode 100644
> > index 000000000000..19126e07d2a6
> > --- /dev/null
> > +++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.h
> > @@ -0,0 +1,20 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/* Copyright (c) 2018 Jernej Skrabec <jernej.skrabec-gGgVlfcn5nU@public.gmane.org> */
> > +
> > +#ifndef _SUN8I_TCON_TOP_H_
> > +#define _SUN8I_TCON_TOP_H_
> > +
> > +#include <linux/device.h>
> > +
> > +struct sun8i_tcon_top;
> > +
> > +enum tcon_type {
> > + tcon_type_lcd,
> > + tcon_type_tv,
>
> The usual practice is to have the enum values upper-case.
Ok.
Best regards,
Jernej
next prev parent reply other threads:[~2018-05-21 15:15 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-19 18:31 [PATCH 00/15] Add support for R40 HDMI pipeline Jernej Skrabec
2018-05-19 18:31 ` [PATCH 04/15] dt-bindings: display: sunxi-drm: Add TCON TOP description Jernej Skrabec
[not found] ` <20180519183127.2718-5-jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
2018-05-21 8:01 ` Maxime Ripard
2018-05-21 15:10 ` Jernej Škrabec
[not found] ` <20180519183127.2718-1-jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
2018-05-19 18:31 ` [PATCH 01/15] clk: sunxi-ng: r40: Add minimal rate for video PLLs Jernej Skrabec
2018-05-19 18:31 ` [PATCH 02/15] clk: sunxi-ng: r40: Allow setting parent rate to display related clocks Jernej Skrabec
2018-05-19 18:31 ` [PATCH 03/15] clk: sunxi-ng: r40: Export video PLLs Jernej Skrabec
[not found] ` <20180519183127.2718-4-jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
2018-05-23 18:20 ` Rob Herring
2018-05-19 18:31 ` [PATCH 05/15] drm/sun4i: Add TCON TOP driver Jernej Skrabec
[not found] ` <20180519183127.2718-6-jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
2018-05-21 8:05 ` Maxime Ripard
2018-05-21 15:15 ` Jernej Škrabec [this message]
2018-05-24 8:43 ` Maxime Ripard
2018-05-24 20:33 ` Jernej Škrabec
2018-05-22 2:25 ` kbuild test robot
2018-05-23 18:23 ` Rob Herring
2018-05-19 18:31 ` [PATCH 06/15] drm/sun4i: tcon: Add support for tcon-top Jernej Skrabec
2018-05-21 8:07 ` Maxime Ripard
2018-05-21 17:27 ` Jernej Škrabec
2018-05-24 8:50 ` Maxime Ripard
2018-05-24 22:01 ` Chen-Yu Tsai
[not found] ` <CAGb2v65whE-qW++cg+gu_o2O1dDdCWkumQB41nt3Aqa75Wp3dg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-05-31 9:21 ` Maxime Ripard
[not found] ` <20180531092133.3gqepoabvuruiztz-YififvaboMKzQB+pC5nmwQ@public.gmane.org>
2018-05-31 17:54 ` Jernej Škrabec
2018-06-01 15:29 ` Maxime Ripard
2018-06-01 16:19 ` Chen-Yu Tsai
[not found] ` <CAGb2v667pdjfHXYpBk1ER5sC8vgpcaOFKEbEByWoD1zh9Z0cyg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-06-04 11:50 ` Maxime Ripard
2018-06-04 15:09 ` Jernej Škrabec
2018-06-04 16:23 ` Maxime Ripard
2018-06-06 22:30 ` Jernej Škrabec
2018-06-08 5:17 ` Jernej Škrabec
2018-05-19 18:31 ` [PATCH 07/15] dt-bindings: display: sun4i-drm: Add R40 HDMI pipeline Jernej Skrabec
[not found] ` <20180519183127.2718-8-jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
2018-05-20 1:50 ` Julian Calaby
2018-05-19 18:31 ` [PATCH 08/15] drm/sun4i: DE2 mixer: Add index quirk Jernej Skrabec
2018-05-19 18:31 ` [PATCH 09/15] drm/sun4i: Add support for R40 mixers Jernej Skrabec
2018-05-19 18:31 ` [PATCH 10/15] drm/sun4i: Add support for R40 TV TCONs Jernej Skrabec
[not found] ` <20180519183127.2718-11-jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
2018-05-20 1:57 ` Julian Calaby
[not found] ` <CAGRGNgWumzhiiwJenOXRuRN0i-_2uY=YR5L+9m70HW2ibF=C7w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-05-20 2:09 ` Julian Calaby
[not found] ` <CAGRGNgXbKGhnern4=_W9W5dKM54H5B1dnAD7up-23rUAMWWCSw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-05-20 7:30 ` Jernej Škrabec
2018-05-19 18:31 ` [PATCH 11/15] drm/sun4i: DW HDMI PHY: Add support for second PLL Jernej Skrabec
2018-05-19 18:31 ` [PATCH 12/15] drm/sun4i: Add support for second clock parent to DW HDMI PHY clk driver Jernej Skrabec
[not found] ` <20180519183127.2718-13-jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
2018-05-21 7:47 ` kbuild test robot
2018-05-21 8:12 ` Maxime Ripard
2018-05-21 15:02 ` Jernej Škrabec
2018-05-24 8:27 ` Maxime Ripard
2018-05-19 18:31 ` [PATCH 13/15] drm/sun4i: Add support for A64 HDMI PHY Jernej Skrabec
2018-05-19 18:31 ` [PATCH 14/15] ARM: dts: sun8i: r40: Add HDMI pipeline Jernej Skrabec
2018-05-19 18:31 ` [PATCH 15/15] ARM: dts: sun8i: r40: Enable HDMI output on BananaPi M2 Ultra Jernej Skrabec
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