From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2120FC00A89 for ; Mon, 2 Nov 2020 13:01:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CDE9E223BE for ; Mon, 2 Nov 2020 13:01:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728719AbgKBNBi (ORCPT ); Mon, 2 Nov 2020 08:01:38 -0500 Received: from foss.arm.com ([217.140.110.172]:59220 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728687AbgKBNBi (ORCPT ); Mon, 2 Nov 2020 08:01:38 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9FA7930E; Mon, 2 Nov 2020 05:01:37 -0800 (PST) Received: from [10.57.54.223] (unknown [10.57.54.223]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 886703F66E; Mon, 2 Nov 2020 05:01:36 -0800 (PST) Subject: Re: [PATCH] arm64: dts: ti: k3-am65: mark dss as dma-coherent To: Tomi Valkeinen , Nishanth Menon , Nikhil Devshatwar Cc: Tero Kristo , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20201029141159.190621-1-tomi.valkeinen@ti.com> <20201029144100.bf35vierhfignips@NiksLab> <20201029145217.zjazhjvylgwez4do@husked> <8532a1c0-29db-d67a-441f-b58b232f7c98@ti.com> From: Robin Murphy Message-ID: <59747093-4171-937d-70a3-ce6ee788cf79@arm.com> Date: Mon, 2 Nov 2020 13:01:34 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:78.0) Gecko/20100101 Thunderbird/78.4.0 MIME-Version: 1.0 In-Reply-To: <8532a1c0-29db-d67a-441f-b58b232f7c98@ti.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 2020-10-30 14:08, Tomi Valkeinen wrote: > On 29/10/2020 16:52, Nishanth Menon wrote: >> On 20:11-20201029, Nikhil Devshatwar wrote: >>> On 16:11-20201029, Tomi Valkeinen wrote: >>>> DSS is IO coherent on AM65, so we can mark it as such with >>>> 'dma-coherent' property in the DT file. >>>> >>>> Signed-off-by: Tomi Valkeinen >>> Acked-by: Nikhil Devshatwar >>> >> >> Tomi: Do you need to add Fixes: tag to percolate this to stable? if >> yes, please comment, makes it easier for me to queue for 5.10 if >> possible > > I don't see this as a fix, but an optimization. Nothing is broken without this. Note that if the driver doesn't have explicit control over what type of memory access the device makes, that's not necessarily true. If coherent DMA buffers are allocated from regular kernel memory, there's still a cacheable alias kicking around that can be speculatively fetched into a cache somewhere. If the device is genuinely non-coherent, or configured to make non-snooping accesses, then that's not an issue, but it it's hard-wired to make snooping accesses it can start hitting that cached alias and not see subsequent updates to the buffer, since those are written straight to RAM via the non-cacheable mapping. At that point it becomes an actual problem (and it's not just theoretical - we've hit a real-world example of this recently with GPUs on certain Amlogic devices). Robin.