[PATCH v4 0/7] SMP and CPU hotplug support for Meson8/Meson8b

[PATCH v4 0/7] SMP and CPU hotplug support for Meson8/Meson8b

[Martin Blumenstingl]

This patchset adds support for booting the secondary CPU cores (and
taking them offline again) on Amlogic Meson8 and Meson8b SoCs.
It is based on an earlier version from Carlo Caione - this helped me
a lot to get a better understanding of how SMP/CPU hotplug works
(compared to the code found in Amlogic's GPL kernel sources from
year 2015).


The .dts changes from series depend on:
- "add the reset controller to the Meson8b clkc" version 2, see [1]
- "ARM: dts: meson: add a node which describes the SRAM", see [2]


Changes since v3 from [3]:
- added Rob's ACK to patch #1
- replaced a msleep(10) with usleep_range(10000, 15000) in patch #4
- removed all "pen" code from patch #4 as that code was not needed
  at all (it was left-over while trying to fix Meson8 secondary CPU
  boot - which turned out to have nothing to do with this "pen" code)
- removed all memory barrier operations as they were added based on
  the code in the Amlogic GPL kernel tree (while trying to fix the
  Meson8 secondary CPU boot - just like the "pen" code). Everything
  still works fine with these on my Meson8m2 and Meson8b boards.
- added PATCH #5 as we now have to export the reset identifiers
  (just like we do it with the clock identifiers / preprocessor
  macros) - this is the result of a change in the reset controller
  patch in version 2, see [1]
- use the reset line preprocessor macros (from patch #5) in patches
  #6 and #7

Changes since v2 from [0]:
- added support for Meson8 (which requires a slightly different
  enable-method)
- implemented CPU hotplug support which allows taking a CPU core
  offline for both, Meson8 and Meson8b
- add a function to smp_scu.c which allows enabling a CPU core from
  a different CPU (previously only the power mode for the current CPU
  could be changed). Without this the CPU cores on Meson8 won't come
  up (Amlogic's vendor GPL kernel sources also enable power through
  SCU as very first step for Meson8b as well)
- add a function to smp_scu.c to get the power status of a CPU core
  (which is needed because the code in .cpu_kill needs to wait until
  the core is actually powered off)
- dropped patch "ARM: DTS: meson8b: Extend L2 cache controller node"
  as it is already applied (for both, Meson8 and Meson8b)
- dropped the patches which implement the reset controller which is
  built into the clock-controller, these are a separate series: [1]
- moved the enable-method property to each CPU node


[0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390355.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004352.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004282.html
[3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004297.html

Carlo Caione (2):
  dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation
  ARM: dts: meson8b: add support for booting the secondary CPU cores

Martin Blumenstingl (5):
  ARM: smp_scu: add a helper for powering on a specific CPU
  ARM: smp_scu: allow the platform code to read the SCU CPU status
  ARM: meson: Add SMP bringup code for Meson8 and Meson8b
  clk: meson: meson8b: export the CPU soft reset lines
  ARM: dts: meson8: add support for booting the secondary CPU cores

 .../devicetree/bindings/arm/amlogic/pmu.txt        |  18 +
 .../devicetree/bindings/arm/amlogic/smp-sram.txt   |  32 ++
 Documentation/devicetree/bindings/arm/cpus.txt     |   2 +
 arch/arm/Makefile                                  |   1 +
 arch/arm/boot/dts/meson8.dtsi                      |  20 +
 arch/arm/boot/dts/meson8b.dtsi                     |  20 +
 arch/arm/include/asm/smp_scu.h                     |  12 +
 arch/arm/kernel/smp_scu.c                          |  47 ++-
 arch/arm/mach-meson/Kconfig                        |   1 +
 arch/arm/mach-meson/Makefile                       |   1 +
 arch/arm/mach-meson/platsmp.c                      | 440 +++++++++++++++++++++
 drivers/clk/meson/meson8b.h                        |   8 +-
 include/dt-bindings/clock/meson8b-clkc.h           |   7 +-
 13 files changed, 598 insertions(+), 11 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/amlogic/pmu.txt
 create mode 100644 Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt
 create mode 100644 arch/arm/mach-meson/platsmp.c

-- 
2.13.3

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[PATCH v4 1/7] dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation

[Martin Blumenstingl]

From: Carlo Caione <carlo-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>

With this patch we add documentation for:

* power-management-unit: the PMU is used to bring up the cores during
  SMP operations
* sram: among other things the sram is used to store the first code
  executed by the core when it is powered up
* cpu-enable-method: the CPU enable method used by Amlogic Meson8 and
  Meson8b SoCs

Signed-off-by: Carlo Caione <carlo-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>
[also add Meson8 to the documentation]
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
 .../devicetree/bindings/arm/amlogic/pmu.txt        | 18 ++++++++++++
 .../devicetree/bindings/arm/amlogic/smp-sram.txt   | 32 ++++++++++++++++++++++
 Documentation/devicetree/bindings/arm/cpus.txt     |  2 ++
 3 files changed, 52 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/amlogic/pmu.txt
 create mode 100644 Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt

diff --git a/Documentation/devicetree/bindings/arm/amlogic/pmu.txt b/Documentation/devicetree/bindings/arm/amlogic/pmu.txt
new file mode 100644
index 000000000000..72f8d08198b6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/amlogic/pmu.txt
@@ -0,0 +1,18 @@
+Amlogic Meson8 and Meson8b power-management-unit:
+-------------------------------------------------
+
+The pmu is used to turn off and on different power domains of the SoCs
+This includes the power to the CPU cores.
+
+Required node properties:
+- compatible value : depending on the SoC this should be one of:
+			"amlogic,meson8-pmu"
+			"amlogic,meson8b-pmu"
+- reg : physical base address and the size of the registers window
+
+Example:
+
+	pmu@c81000e4 {
+		compatible = "amlogic,meson8b-pmu", "syscon";
+		reg = <0xc81000e0 0x18>;
+	};
diff --git a/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt b/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt
new file mode 100644
index 000000000000..3473ddaadfac
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt
@@ -0,0 +1,32 @@
+Amlogic Meson8 and Meson8b SRAM for smp bringup:
+------------------------------------------------
+
+Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
+Once the core gets powered up it executes the code that is residing at a
+specific location.
+
+Therefore a reserved section sub-node has to be added to the mmio-sram
+declaration.
+
+Required sub-node properties:
+- compatible : depending on the SoC this should be one of:
+		"amlogic,meson8-smp-sram"
+		"amlogic,meson8b-smp-sram"
+
+The rest of the properties should follow the generic mmio-sram discription
+found in ../../misc/sram.txt
+
+Example:
+
+	sram: sram@d9000000 {
+		compatible = "mmio-sram";
+		reg = <0xd9000000 0x20000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xd9000000 0x20000>;
+
+		smp-sram@1ff80 {
+			compatible = "amlogic,meson8b-smp-sram";
+			reg = <0x1ff80 0x8>;
+		};
+	};
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index a44253cad269..1ef3e53b9be7 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -197,6 +197,8 @@ described below.
 			    "actions,s500-smp"
 			    "allwinner,sun6i-a31"
 			    "allwinner,sun8i-a23"
+			    "amlogic,meson8-smp"
+			    "amlogic,meson8b-smp"
 			    "arm,realview-smp"
 			    "brcm,bcm11351-cpu-method"
 			    "brcm,bcm23550"
-- 
2.13.3

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Re: [PATCH v4 1/7] dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation

[Neil Armstrong]

Le 22/07/2017 21:19, Martin Blumenstingl a écrit :
> From: Carlo Caione <carlo-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>
> 
> With this patch we add documentation for:
> 
> * power-management-unit: the PMU is used to bring up the cores during
>   SMP operations
> * sram: among other things the sram is used to store the first code
>   executed by the core when it is powered up
> * cpu-enable-method: the CPU enable method used by Amlogic Meson8 and
>   Meson8b SoCs
> 
> Signed-off-by: Carlo Caione <carlo-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>
> [also add Meson8 to the documentation]
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> ---
>  .../devicetree/bindings/arm/amlogic/pmu.txt        | 18 ++++++++++++
>  .../devicetree/bindings/arm/amlogic/smp-sram.txt   | 32 ++++++++++++++++++++++
>  Documentation/devicetree/bindings/arm/cpus.txt     |  2 ++
>  3 files changed, 52 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/amlogic/pmu.txt
>  create mode 100644 Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/amlogic/pmu.txt b/Documentation/devicetree/bindings/arm/amlogic/pmu.txt
> new file mode 100644
> index 000000000000..72f8d08198b6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/amlogic/pmu.txt
> @@ -0,0 +1,18 @@
> +Amlogic Meson8 and Meson8b power-management-unit:
> +-------------------------------------------------
> +
> +The pmu is used to turn off and on different power domains of the SoCs
> +This includes the power to the CPU cores.
> +
> +Required node properties:
> +- compatible value : depending on the SoC this should be one of:
> +			"amlogic,meson8-pmu"
> +			"amlogic,meson8b-pmu"
> +- reg : physical base address and the size of the registers window
> +
> +Example:
> +
> +	pmu@c81000e4 {
> +		compatible = "amlogic,meson8b-pmu", "syscon";
> +		reg = <0xc81000e0 0x18>;
> +	};
> diff --git a/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt b/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt
> new file mode 100644
> index 000000000000..3473ddaadfac
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt
> @@ -0,0 +1,32 @@
> +Amlogic Meson8 and Meson8b SRAM for smp bringup:
> +------------------------------------------------
> +
> +Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
> +Once the core gets powered up it executes the code that is residing at a
> +specific location.
> +
> +Therefore a reserved section sub-node has to be added to the mmio-sram
> +declaration.
> +
> +Required sub-node properties:
> +- compatible : depending on the SoC this should be one of:
> +		"amlogic,meson8-smp-sram"
> +		"amlogic,meson8b-smp-sram"
> +
> +The rest of the properties should follow the generic mmio-sram discription
> +found in ../../misc/sram.txt
> +
> +Example:
> +
> +	sram: sram@d9000000 {
> +		compatible = "mmio-sram";
> +		reg = <0xd9000000 0x20000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0 0xd9000000 0x20000>;
> +
> +		smp-sram@1ff80 {
> +			compatible = "amlogic,meson8b-smp-sram";
> +			reg = <0x1ff80 0x8>;
> +		};
> +	};
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index a44253cad269..1ef3e53b9be7 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -197,6 +197,8 @@ described below.
>  			    "actions,s500-smp"
>  			    "allwinner,sun6i-a31"
>  			    "allwinner,sun8i-a23"
> +			    "amlogic,meson8-smp"
> +			    "amlogic,meson8b-smp"
>  			    "arm,realview-smp"
>  			    "brcm,bcm11351-cpu-method"
>  			    "brcm,bcm23550"
> 

Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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[PATCH v4 2/7] ARM: smp_scu: add a helper for powering on a specific CPU

[Martin Blumenstingl]

To boot the secondary CPUs on the Amlogic Meson8/Meson8m2 (Cortex-A9)
and Meson8b (Cortex-A5) SoCs we have to enable SCU mode SCU_PM_NORMAL,
otherwise the secondary cores will not start.
This patch adds a scu_cpu_power_enable() function which can be used to
enable SCU_PM_NORMAL for a specific (logical) CPU. An internal helper
function is also created, to avoid code duplication with
scu_power_mode().

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 arch/arm/include/asm/smp_scu.h |  6 ++++++
 arch/arm/kernel/smp_scu.c      | 39 +++++++++++++++++++++++++++++----------
 2 files changed, 35 insertions(+), 10 deletions(-)

diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h
index bfe163c40024..11e636f33ed9 100644
--- a/arch/arm/include/asm/smp_scu.h
+++ b/arch/arm/include/asm/smp_scu.h
@@ -26,6 +26,7 @@ static inline unsigned long scu_a9_get_base(void)
 #ifdef CONFIG_HAVE_ARM_SCU
 unsigned int scu_get_core_count(void __iomem *);
 int scu_power_mode(void __iomem *, unsigned int);
+int scu_cpu_power_enable(void __iomem *, unsigned int);
 #else
 static inline unsigned int scu_get_core_count(void __iomem *scu_base)
 {
@@ -35,6 +36,11 @@ static inline int scu_power_mode(void __iomem *scu_base, unsigned int mode)
 {
 	return -EINVAL;
 }
+static inline int scu_cpu_power_enable(void __iomem *scu_base,
+				       unsigned int mode)
+{
+	return -EINVAL;
+}
 #endif
 
 #if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU)
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
index 72f9241ad5db..ef09121b18eb 100644
--- a/arch/arm/kernel/smp_scu.c
+++ b/arch/arm/kernel/smp_scu.c
@@ -72,18 +72,12 @@ void scu_enable(void __iomem *scu_base)
 }
 #endif
 
-/*
- * Set the executing CPUs power mode as defined.  This will be in
- * preparation for it executing a WFI instruction.
- *
- * This function must be called with preemption disabled, and as it
- * has the side effect of disabling coherency, caches must have been
- * flushed.  Interrupts must also have been disabled.
- */
-int scu_power_mode(void __iomem *scu_base, unsigned int mode)
+static int scu_set_power_mode_internal(void __iomem *scu_base,
+				       unsigned int logical_cpu,
+				       unsigned int mode)
 {
 	unsigned int val;
-	int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
+	int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0);
 
 	if (mode > 3 || mode == 1 || cpu > 3)
 		return -EINVAL;
@@ -94,3 +88,28 @@ int scu_power_mode(void __iomem *scu_base, unsigned int mode)
 
 	return 0;
 }
+
+/*
+ * Set the executing CPUs power mode as defined.  This will be in
+ * preparation for it executing a WFI instruction.
+ *
+ * This function must be called with preemption disabled, and as it
+ * has the side effect of disabling coherency, caches must have been
+ * flushed.  Interrupts must also have been disabled.
+ */
+int scu_power_mode(void __iomem *scu_base, unsigned int mode)
+{
+	return scu_set_power_mode_internal(scu_base, smp_processor_id(), mode);
+}
+
+/*
+ * Set the executing CPUs power mode to SCU_PM_NORMAL.
+ *
+ * This function must be called with preemption disabled, and as it
+ * has the side effect of disabling coherency, caches must have been
+ * flushed. Interrupts must also have been disabled.
+ */
+int scu_cpu_power_enable(void __iomem *scu_base, unsigned int cpu)
+{
+	return scu_set_power_mode_internal(scu_base, cpu, SCU_PM_NORMAL);
+}
-- 
2.13.3

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[PATCH v4 3/7] ARM: smp_scu: allow the platform code to read the SCU CPU status

[Martin Blumenstingl]

On Amlogic Meson8 / Meson8m2 (both Cortex-A9) and Meson8b (Cortex-A5)
the CPU hotplug code needs to wait until the SCU status of the CPU that
is being taken offline is SCU_PM_POWEROFF.
Provide a utility function (which can be invoked for example from
.cpu_kill()) which allows reading the SCU status of a CPU.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 arch/arm/include/asm/smp_scu.h |  6 ++++++
 arch/arm/kernel/smp_scu.c      | 18 +++++++++++++++++-
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h
index 11e636f33ed9..992b34c4267f 100644
--- a/arch/arm/include/asm/smp_scu.h
+++ b/arch/arm/include/asm/smp_scu.h
@@ -27,6 +27,7 @@ static inline unsigned long scu_a9_get_base(void)
 unsigned int scu_get_core_count(void __iomem *);
 int scu_power_mode(void __iomem *, unsigned int);
 int scu_cpu_power_enable(void __iomem *, unsigned int);
+int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu);
 #else
 static inline unsigned int scu_get_core_count(void __iomem *scu_base)
 {
@@ -41,6 +42,11 @@ static inline int scu_cpu_power_enable(void __iomem *scu_base,
 {
 	return -EINVAL;
 }
+static inline int scu_get_cpu_power_mode(void __iomem *scu_base,
+					 unsigned int logical_cpu)
+{
+	return -EINVAL;
+}
 #endif
 
 #if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU)
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
index ef09121b18eb..942f8acb82c1 100644
--- a/arch/arm/kernel/smp_scu.c
+++ b/arch/arm/kernel/smp_scu.c
@@ -21,6 +21,7 @@
 #define SCU_STANDBY_ENABLE	(1 << 5)
 #define SCU_CONFIG		0x04
 #define SCU_CPU_STATUS		0x08
+#define SCU_CPU_STATUS_MASK	GENMASK(1, 0)
 #define SCU_INVALIDATE		0x0c
 #define SCU_FPGA_REVISION	0x10
 
@@ -82,7 +83,8 @@ static int scu_set_power_mode_internal(void __iomem *scu_base,
 	if (mode > 3 || mode == 1 || cpu > 3)
 		return -EINVAL;
 
-	val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
+	val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
+	val &= ~SCU_CPU_STATUS_MASK;
 	val |= mode;
 	writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);
 
@@ -113,3 +115,17 @@ int scu_cpu_power_enable(void __iomem *scu_base, unsigned int cpu)
 {
 	return scu_set_power_mode_internal(scu_base, cpu, SCU_PM_NORMAL);
 }
+
+int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu)
+{
+	unsigned int val;
+	int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0);
+
+	if (cpu > 3)
+		return -EINVAL;
+
+	val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
+	val &= SCU_CPU_STATUS_MASK;
+
+	return val;
+}
-- 
2.13.3

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[PATCH v4 4/7] ARM: meson: Add SMP bringup code for Meson8 and Meson8b

[Martin Blumenstingl]

This adds the necessary SMP-operations and startup code to use the
additional cores on the Amlogic Meson8/Meson8m2 (both are using the same
sequence) and Meson8b (using a slightly difference sequence) SoCs.

Signed-off-by: Carlo Caione <carlo-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>
[add Meson8/Meson8m2 support and allow taking CPU cores offline as well]
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 arch/arm/Makefile             |   1 +
 arch/arm/mach-meson/Kconfig   |   1 +
 arch/arm/mach-meson/Makefile  |   1 +
 arch/arm/mach-meson/platsmp.c | 440 ++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 443 insertions(+)
 create mode 100644 arch/arm/mach-meson/platsmp.c

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 47d3a1ab08d2..82faa958ab88 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -147,6 +147,7 @@ textofs-$(CONFIG_SA1111) := 0x00208000
 endif
 textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
 textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
+textofs-$(CONFIG_ARCH_MESON) := 0x00208000
 textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
 
 # Machine directory name.  This list is sorted alphanumerically
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index ee30511849ca..a0c64762d961 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -9,6 +9,7 @@ menuconfig ARCH_MESON
 	select PINCTRL_MESON
 	select COMMON_CLK
 	select COMMON_CLK_AMLOGIC
+	select HAVE_ARM_SCU if SMP
 
 if ARCH_MESON
 
diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
index 9d7380eeeedd..bc26c85a7e8f 100644
--- a/arch/arm/mach-meson/Makefile
+++ b/arch/arm/mach-meson/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_ARCH_MESON) += meson.o
+obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-meson/platsmp.c b/arch/arm/mach-meson/platsmp.c
new file mode 100644
index 000000000000..97c36f0e55fe
--- /dev/null
+++ b/arch/arm/mach-meson/platsmp.c
@@ -0,0 +1,440 @@
+/*
+ * Copyright (C) 2015 Carlo Caione <carlo-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>
+ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/smp.h>
+#include <linux/mfd/syscon.h>
+
+#include <asm/cacheflush.h>
+#include <asm/cp15.h>
+#include <asm/smp_scu.h>
+#include <asm/smp_plat.h>
+
+#define MESON_SMP_SRAM_CPU_CTRL_REG		(0x00)
+#define MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(c)	(0x04 + ((c - 1) << 2))
+
+#define MESON_CPU_AO_RTI_PWR_A9_CNTL0		(0x00)
+#define MESON_CPU_AO_RTI_PWR_A9_CNTL1		(0x04)
+#define MESON_CPU_AO_RTI_PWR_A9_MEM_PD0		(0x14)
+
+#define MESON_CPU_PWR_A9_CNTL0_M(c)		(0x03 << ((c * 2) + 16))
+#define MESON_CPU_PWR_A9_CNTL1_M(c)		(0x03 << ((c + 1) << 1))
+#define MESON_CPU_PWR_A9_MEM_PD0_M(c)		(0x0f << (32 - (c * 4)))
+#define MESON_CPU_PWR_A9_CNTL1_ST(c)		(0x01 << (c + 16))
+
+static void __iomem *sram_base;
+static void __iomem *scu_base;
+static struct regmap *pmu;
+
+static struct reset_control *meson_smp_get_core_reset(int cpu)
+{
+	struct device_node *np = of_get_cpu_node(cpu, 0);
+
+	return of_reset_control_get_exclusive(np, NULL);
+}
+
+static void meson_smp_set_cpu_ctrl(int cpu, bool on_off)
+{
+	u32 val = readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_REG);
+
+	if (on_off)
+		val |= BIT(cpu);
+	else
+		val &= ~BIT(cpu);
+
+	/* keep bit 0 always enabled */
+	val |= BIT(0);
+
+	writel(val, sram_base + MESON_SMP_SRAM_CPU_CTRL_REG);
+}
+
+static void __init meson_smp_prepare_cpus(const char *scu_compatible,
+					  const char *pmu_compatible,
+					  const char *sram_compatible)
+{
+	static struct device_node *node;
+
+	/* SMP SRAM */
+	node = of_find_compatible_node(NULL, NULL, sram_compatible);
+	if (!node) {
+		pr_err("Missing SRAM node\n");
+		return;
+	}
+
+	sram_base = of_iomap(node, 0);
+	if (!sram_base) {
+		pr_err("Couldn't map SRAM registers\n");
+		return;
+	}
+
+	/* PMU */
+	pmu = syscon_regmap_lookup_by_compatible(pmu_compatible);
+	if (IS_ERR(pmu)) {
+		pr_err("Couldn't map PMU registers\n");
+		return;
+	}
+
+	/* SCU */
+	node = of_find_compatible_node(NULL, NULL, scu_compatible);
+	if (!node) {
+		pr_err("Missing SCU node\n");
+		return;
+	}
+
+	scu_base = of_iomap(node, 0);
+	if (!scu_base) {
+		pr_err("Couln't map SCU registers\n");
+		return;
+	}
+
+	scu_enable(scu_base);
+}
+
+static void __init meson8b_smp_prepare_cpus(unsigned int max_cpus)
+{
+	meson_smp_prepare_cpus("arm,cortex-a5-scu", "amlogic,meson8b-pmu",
+			       "amlogic,meson8b-smp-sram");
+}
+
+static void __init meson8_smp_prepare_cpus(unsigned int max_cpus)
+{
+	meson_smp_prepare_cpus("arm,cortex-a9-scu", "amlogic,meson8-pmu",
+			       "amlogic,meson8-smp-sram");
+}
+
+static void meson_smp_begin_secondary_boot(unsigned int cpu)
+{
+	/*
+	 * Set the entry point before powering on the CPU through the SCU. This
+	 * is needed if the CPU is in "warm" state (= after rebooting the
+	 * system without power-cycling, or when taking the CPU offline and
+	 * then taking it online again.
+	 */
+	writel(virt_to_phys(secondary_startup),
+	       sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu));
+
+	/*
+	 * SCU Power on CPU (needs to be done before starting the CPU,
+	 * otherwise the secondary CPU will not start).
+	 */
+	scu_cpu_power_enable(scu_base, cpu);
+}
+
+static int meson_smp_finalize_secondary_boot(unsigned int cpu)
+{
+	unsigned long timeout;
+
+	timeout = jiffies + (10 * HZ);
+	while (readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu))) {
+		if (!time_before(jiffies, timeout)) {
+			pr_err("Timeout while waiting for CPU%d status\n",
+			       cpu);
+			return -ETIMEDOUT;
+		}
+	}
+
+	writel(virt_to_phys(secondary_startup),
+	       sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu));
+
+	meson_smp_set_cpu_ctrl(cpu, true);
+
+	return 0;
+}
+
+static int meson8_smp_boot_secondary(unsigned int cpu,
+				     struct task_struct *idle)
+{
+	struct reset_control *rstc;
+	int ret;
+
+	rstc = meson_smp_get_core_reset(cpu);
+	if (IS_ERR(rstc)) {
+		pr_err("Couldn't get the reset controller for CPU%d\n", cpu);
+		return PTR_ERR(rstc);
+	}
+
+	meson_smp_begin_secondary_boot(cpu);
+
+	/* Reset enable */
+	ret = reset_control_assert(rstc);
+	if (ret) {
+		pr_err("Failed to assert CPU%d reset\n", cpu);
+		goto out;
+	}
+
+	/* CPU power ON */
+	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
+				 MESON_CPU_PWR_A9_CNTL1_M(cpu), 0);
+	if (ret < 0) {
+		pr_err("Couldn't wake up CPU%d\n", cpu);
+		goto out;
+	}
+
+	udelay(10);
+
+	/* Isolation disable */
+	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
+				 0);
+	if (ret < 0) {
+		pr_err("Error when disabling isolation of CPU%d\n", cpu);
+		goto out;
+	}
+
+	/* Reset disable */
+	ret = reset_control_deassert(rstc);
+	if (ret) {
+		pr_err("Failed to de-assert CPU%d reset\n", cpu);
+		goto out;
+	}
+
+	ret = meson_smp_finalize_secondary_boot(cpu);
+	if (ret)
+		goto out;
+
+out:
+	reset_control_put(rstc);
+
+	return 0;
+}
+
+static int meson8b_smp_boot_secondary(unsigned int cpu,
+				     struct task_struct *idle)
+{
+	struct reset_control *rstc;
+	int ret;
+	u32 val;
+
+	rstc = meson_smp_get_core_reset(cpu);
+	if (IS_ERR(rstc)) {
+		pr_err("Couldn't get the reset controller for CPU%d\n", cpu);
+		return PTR_ERR(rstc);
+	}
+
+	meson_smp_begin_secondary_boot(cpu);
+
+	/* CPU power UP */
+	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0,
+				 MESON_CPU_PWR_A9_CNTL0_M(cpu), 0);
+	if (ret < 0) {
+		pr_err("Couldn't power up CPU%d\n", cpu);
+		goto out;
+	}
+
+	udelay(5);
+
+	/* Reset enable */
+	ret = reset_control_assert(rstc);
+	if (ret) {
+		pr_err("Failed to assert CPU%d reset\n", cpu);
+		goto out;
+	}
+
+	/* Memory power UP */
+	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0,
+				 MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0);
+	if (ret < 0) {
+		pr_err("Couldn't power up the memory for CPU%d\n", cpu);
+		goto out;
+	}
+
+	/* Wake up CPU */
+	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
+				 MESON_CPU_PWR_A9_CNTL1_M(cpu), 0);
+	if (ret < 0) {
+		pr_err("Couldn't wake up CPU%d\n", cpu);
+		goto out;
+	}
+
+	udelay(10);
+
+	ret = regmap_read_poll_timeout(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, val,
+				       val & MESON_CPU_PWR_A9_CNTL1_ST(cpu),
+				       10, 10000);
+	if (ret) {
+		pr_err("Timeout while polling PMU for CPU%d status\n", cpu);
+		goto out;
+	}
+
+	/* Isolation disable */
+	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
+				 0);
+	if (ret < 0) {
+		pr_err("Error when disabling isolation of CPU%d\n", cpu);
+		goto out;
+	}
+
+	/* Reset disable */
+	ret = reset_control_deassert(rstc);
+	if (ret) {
+		pr_err("Failed to de-assert CPU%d reset\n", cpu);
+		goto out;
+	}
+
+	ret = meson_smp_finalize_secondary_boot(cpu);
+	if (ret)
+		goto out;
+
+out:
+	reset_control_put(rstc);
+
+	return 0;
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+static void meson8_smp_cpu_die(unsigned int cpu)
+{
+	meson_smp_set_cpu_ctrl(cpu, false);
+
+	v7_exit_coherency_flush(louis);
+
+	scu_power_mode(scu_base, SCU_PM_POWEROFF);
+
+	dsb();
+	wfi();
+
+	/* we should never get here */
+	WARN_ON(1);
+}
+
+static int meson8_smp_cpu_kill(unsigned int cpu)
+{
+	int ret, power_mode;
+	unsigned long timeout;
+
+	timeout = jiffies + (50 * HZ);
+	do {
+		power_mode = scu_get_cpu_power_mode(scu_base, cpu);
+
+		if (power_mode == SCU_PM_POWEROFF)
+			break;
+
+		usleep_range(10000, 15000);
+	} while (time_before(jiffies, timeout));
+
+	if (power_mode != SCU_PM_POWEROFF) {
+		pr_err("Error while waiting for SCU power-off on CPU%d\n",
+		       cpu);
+		return -ETIMEDOUT;
+	}
+
+	msleep(30);
+
+	/* Isolation enable */
+	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
+				 0x3);
+	if (ret < 0) {
+		pr_err("Error when enabling isolation for CPU%d\n", cpu);
+		return ret;
+	}
+
+	udelay(10);
+
+	/* CPU power OFF */
+	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
+				 MESON_CPU_PWR_A9_CNTL1_M(cpu), 0x3);
+	if (ret < 0) {
+		pr_err("Couldn't change sleep status of CPU%d\n", cpu);
+		return ret;
+	}
+
+	return 1;
+}
+
+static int meson8b_smp_cpu_kill(unsigned int cpu)
+{
+	int ret, power_mode, count = 5000;
+
+	do {
+		power_mode = scu_get_cpu_power_mode(scu_base, cpu);
+
+		if (power_mode == SCU_PM_POWEROFF)
+			break;
+
+		udelay(10);
+	} while (++count);
+
+	if (power_mode != SCU_PM_POWEROFF) {
+		pr_err("Error while waiting for SCU power-off on CPU%d\n",
+		       cpu);
+		return -ETIMEDOUT;
+	}
+
+	udelay(10);
+
+	/* CPU power DOWN */
+	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0,
+				 MESON_CPU_PWR_A9_CNTL0_M(cpu), 0x3);
+	if (ret < 0) {
+		pr_err("Couldn't power down CPU%d\n", cpu);
+		return ret;
+	}
+
+	/* Isolation enable */
+	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
+				 0x3);
+	if (ret < 0) {
+		pr_err("Error when enabling isolation for CPU%d\n", cpu);
+		return ret;
+	}
+
+	udelay(10);
+
+	/* Sleep status */
+	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
+				 MESON_CPU_PWR_A9_CNTL1_M(cpu), 0x3);
+	if (ret < 0) {
+		pr_err("Couldn't change sleep status of CPU%d\n", cpu);
+		return ret;
+	}
+
+	/* Memory power DOWN */
+	ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0,
+				 MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0xf);
+	if (ret < 0) {
+		pr_err("Couldn't power down the memory of CPU%d\n", cpu);
+		return ret;
+	}
+
+	return 1;
+}
+#endif
+
+static struct smp_operations meson8_smp_ops __initdata = {
+	.smp_prepare_cpus	= meson8_smp_prepare_cpus,
+	.smp_boot_secondary	= meson8_smp_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+	.cpu_die		= meson8_smp_cpu_die,
+	.cpu_kill		= meson8_smp_cpu_kill,
+#endif
+};
+
+static struct smp_operations meson8b_smp_ops __initdata = {
+	.smp_prepare_cpus	= meson8b_smp_prepare_cpus,
+	.smp_boot_secondary	= meson8b_smp_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+	.cpu_die		= meson8_smp_cpu_die,
+	.cpu_kill		= meson8b_smp_cpu_kill,
+#endif
+};
+
+CPU_METHOD_OF_DECLARE(meson8_smp, "amlogic,meson8-smp", &meson8_smp_ops);
+CPU_METHOD_OF_DECLARE(meson8b_smp, "amlogic,meson8b-smp", &meson8b_smp_ops);
-- 
2.13.3

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Re: [PATCH v4 4/7] ARM: meson: Add SMP bringup code for Meson8 and Meson8b

[Florian Fainelli]

On July 22, 2017 12:19:43 PM PDT, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
>This adds the necessary SMP-operations and startup code to use the
>additional cores on the Amlogic Meson8/Meson8m2 (both are using the
>same
>sequence) and Meson8b (using a slightly difference sequence) SoCs.
>
>Signed-off-by: Carlo Caione <carlo@endlessm.com>
>[add Meson8/Meson8m2 support and allow taking CPU cores offline as
>well]
>Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>---

>+static void meson_smp_begin_secondary_boot(unsigned int cpu)
>+{
>+	/*
>+	 * Set the entry point before powering on the CPU through the SCU.
>This
>+	 * is needed if the CPU is in "warm" state (= after rebooting the
>+	 * system without power-cycling, or when taking the CPU offline and
>+	 * then taking it online again.
>+	 */
>+	writel(virt_to_phys(secondary_startup),
>+	       sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu));

Please use __pa_symbol() since secondary startup is a kernel image symbol.

>+
>+	/*
>+	 * SCU Power on CPU (needs to be done before starting the CPU,
>+	 * otherwise the secondary CPU will not start).
>+	 */
>+	scu_cpu_power_enable(scu_base, cpu);
>+}
>+
>+static int meson_smp_finalize_secondary_boot(unsigned int cpu)
>+{
>+	unsigned long timeout;
>+
>+	timeout = jiffies + (10 * HZ);
>+	while (readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu))) {
>+		if (!time_before(jiffies, timeout)) {
>+			pr_err("Timeout while waiting for CPU%d status\n",
>+			       cpu);
>+			return -ETIMEDOUT;
>+		}
>+	}
>+
>+	writel(virt_to_phys(secondary_startup),
>+	       sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu));

Same here.

Thanks!

-- 
Florian
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[PATCH v4 5/7] clk: meson: meson8b: export the CPU soft reset lines

[Martin Blumenstingl]

Export the soft reset lines for the CPU cores so they can be used in the
dt-bindings (required for SMP booting the CPU cores).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 drivers/clk/meson/meson8b.h              | 8 ++++----
 include/dt-bindings/clock/meson8b-clkc.h | 7 ++++++-
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 5f4d8e49dd4d..d6e35c1acc05 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -169,10 +169,10 @@
 #define RESETID_L2_CACHE_SOFT_RESET				0
 #define RESETID_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET		1
 #define RESETID_SCU_SOFT_RESET					2
-#define RESETID_CPU0_SOFT_RESET					3
-#define RESETID_CPU1_SOFT_RESET					4
-#define RESETID_CPU2_SOFT_RESET					5
-#define RESETID_CPU3_SOFT_RESET					6
+/* RESETID_CPU0_SOFT_RESET */
+/* RESETID_CPU1_SOFT_RESET */
+/* RESETID_CPU2_SOFT_RESET */
+/* RESETID_CPU3_SOFT_RESET */
 #define RESETID_A5_GLOBAL_RESET					7
 #define RESETID_A5_AXI_SOFT_RESET				8
 #define RESETID_A5_ABP_SOFT_RESET				9
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index e29227fb52a1..76920cfd1f33 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -1,5 +1,5 @@
 /*
- * Meson8b clock tree IDs
+ * Meson8b clock and reset tree IDs
  */
 
 #ifndef __MESON8B_CLKC_H
@@ -32,4 +32,9 @@
 #define CLKID_USB0_DDR_BRIDGE	65
 #define CLKID_SANA		69
 
+#define RESETID_CPU0_SOFT_RESET					3
+#define RESETID_CPU1_SOFT_RESET					4
+#define RESETID_CPU2_SOFT_RESET					5
+#define RESETID_CPU3_SOFT_RESET					6
+
 #endif /* __MESON8B_CLKC_H */
-- 
2.13.3

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Re: [PATCH v4 5/7] clk: meson: meson8b: export the CPU soft reset lines

[Neil Armstrong]

Le 22/07/2017 21:19, Martin Blumenstingl a écrit :
> Export the soft reset lines for the CPU cores so they can be used in the
> dt-bindings (required for SMP booting the CPU cores).
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> ---
>  drivers/clk/meson/meson8b.h              | 8 ++++----
>  include/dt-bindings/clock/meson8b-clkc.h | 7 ++++++-
>  2 files changed, 10 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
> index 5f4d8e49dd4d..d6e35c1acc05 100644
> --- a/drivers/clk/meson/meson8b.h
> +++ b/drivers/clk/meson/meson8b.h
> @@ -169,10 +169,10 @@
>  #define RESETID_L2_CACHE_SOFT_RESET				0
>  #define RESETID_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET		1
>  #define RESETID_SCU_SOFT_RESET					2
> -#define RESETID_CPU0_SOFT_RESET					3
> -#define RESETID_CPU1_SOFT_RESET					4
> -#define RESETID_CPU2_SOFT_RESET					5
> -#define RESETID_CPU3_SOFT_RESET					6
> +/* RESETID_CPU0_SOFT_RESET */
> +/* RESETID_CPU1_SOFT_RESET */
> +/* RESETID_CPU2_SOFT_RESET */
> +/* RESETID_CPU3_SOFT_RESET */
>  #define RESETID_A5_GLOBAL_RESET					7
>  #define RESETID_A5_AXI_SOFT_RESET				8
>  #define RESETID_A5_ABP_SOFT_RESET				9
> diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
> index e29227fb52a1..76920cfd1f33 100644
> --- a/include/dt-bindings/clock/meson8b-clkc.h
> +++ b/include/dt-bindings/clock/meson8b-clkc.h
> @@ -1,5 +1,5 @@
>  /*
> - * Meson8b clock tree IDs
> + * Meson8b clock and reset tree IDs
>   */
>  
>  #ifndef __MESON8B_CLKC_H
> @@ -32,4 +32,9 @@
>  #define CLKID_USB0_DDR_BRIDGE	65
>  #define CLKID_SANA		69
>  
> +#define RESETID_CPU0_SOFT_RESET					3
> +#define RESETID_CPU1_SOFT_RESET					4
> +#define RESETID_CPU2_SOFT_RESET					5
> +#define RESETID_CPU3_SOFT_RESET					6
> +
>  #endif /* __MESON8B_CLKC_H */
> 

In line with the comment on your clk patch, I think now we should "expose" everything.

Neil
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[PATCH v4 6/7] ARM: dts: meson8: add support for booting the secondary CPU cores

[Martin Blumenstingl]

Booting the secondary CPU cores involves the following nodes/devices:
- SCU (Snoop-Control-Unit, for which we already have a DT node)
- a reset line for each CPU core, provided by the reset-controller
  which is built into the clock-controller
- the PMU (power management unit) which controls the power of the CPU
  cores
- a range in the SRAM specifically reserved for booting secondary CPU
  cores
- the "enable-method" which activates booting the secondary CPU cores

This adds all required nodes and properties to boot the secondary CPU
cores.

Suggested-by: Carlo Caione <carlo-KA+7E9HrN00dnm+yROfE0A@public.gmane.org>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 arch/arm/boot/dts/meson8.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index b98d44fde6b6..44515733df29 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -60,6 +60,8 @@
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
 			reg = <0x200>;
+			enable-method = "amlogic,meson8-smp";
+			resets = <&clkc RESETID_CPU0_SOFT_RESET>;
 		};
 
 		cpu@201 {
@@ -67,6 +69,8 @@
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
 			reg = <0x201>;
+			enable-method = "amlogic,meson8-smp";
+			resets = <&clkc RESETID_CPU1_SOFT_RESET>;
 		};
 
 		cpu@202 {
@@ -74,6 +78,8 @@
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
 			reg = <0x202>;
+			enable-method = "amlogic,meson8-smp";
+			resets = <&clkc RESETID_CPU2_SOFT_RESET>;
 		};
 
 		cpu@203 {
@@ -81,6 +87,8 @@
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
 			reg = <0x203>;
+			enable-method = "amlogic,meson8-smp";
+			resets = <&clkc RESETID_CPU3_SOFT_RESET>;
 		};
 	};
 
@@ -118,6 +126,11 @@
 }; /* end of / */
 
 &aobus {
+	pmu: pmu@e0 {
+		compatible = "amlogic,meson8-pmu", "syscon";
+		reg = <0xe0 0x8>;
+	};
+
 	pinctrl_aobus: pinctrl@84 {
 		compatible = "amlogic,meson8-aobus-pinctrl";
 		reg = <0x84 0xc>;
@@ -249,6 +262,13 @@
 	};
 };
 
+&ahb_sram {
+	smp-sram@1ff80 {
+		compatible = "amlogic,meson8-smp-sram";
+		reg = <0x1ff80 0x8>;
+	};
+};
+
 &ethmac {
 	clocks = <&clkc CLKID_ETH>;
 	clock-names = "stmmaceth";
-- 
2.13.3

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Re: [PATCH v4 6/7] ARM: dts: meson8: add support for booting the secondary CPU cores

[Neil Armstrong]

Le 22/07/2017 21:19, Martin Blumenstingl a écrit :
> Booting the secondary CPU cores involves the following nodes/devices:
> - SCU (Snoop-Control-Unit, for which we already have a DT node)
> - a reset line for each CPU core, provided by the reset-controller
>   which is built into the clock-controller
> - the PMU (power management unit) which controls the power of the CPU
>   cores
> - a range in the SRAM specifically reserved for booting secondary CPU
>   cores
> - the "enable-method" which activates booting the secondary CPU cores
> 
> This adds all required nodes and properties to boot the secondary CPU
> cores.
> 
> Suggested-by: Carlo Caione <carlo-KA+7E9HrN00dnm+yROfE0A@public.gmane.org>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> ---
>  arch/arm/boot/dts/meson8.dtsi | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
> index b98d44fde6b6..44515733df29 100644
> --- a/arch/arm/boot/dts/meson8.dtsi
> +++ b/arch/arm/boot/dts/meson8.dtsi
> @@ -60,6 +60,8 @@
>  			compatible = "arm,cortex-a9";
>  			next-level-cache = <&L2>;
>  			reg = <0x200>;
> +			enable-method = "amlogic,meson8-smp";
> +			resets = <&clkc RESETID_CPU0_SOFT_RESET>;
>  		};
>  
>  		cpu@201 {
> @@ -67,6 +69,8 @@
>  			compatible = "arm,cortex-a9";
>  			next-level-cache = <&L2>;
>  			reg = <0x201>;
> +			enable-method = "amlogic,meson8-smp";
> +			resets = <&clkc RESETID_CPU1_SOFT_RESET>;
>  		};
>  
>  		cpu@202 {
> @@ -74,6 +78,8 @@
>  			compatible = "arm,cortex-a9";
>  			next-level-cache = <&L2>;
>  			reg = <0x202>;
> +			enable-method = "amlogic,meson8-smp";
> +			resets = <&clkc RESETID_CPU2_SOFT_RESET>;
>  		};
>  
>  		cpu@203 {
> @@ -81,6 +87,8 @@
>  			compatible = "arm,cortex-a9";
>  			next-level-cache = <&L2>;
>  			reg = <0x203>;
> +			enable-method = "amlogic,meson8-smp";
> +			resets = <&clkc RESETID_CPU3_SOFT_RESET>;
>  		};
>  	};
>  
> @@ -118,6 +126,11 @@
>  }; /* end of / */
>  
>  &aobus {
> +	pmu: pmu@e0 {
> +		compatible = "amlogic,meson8-pmu", "syscon";
> +		reg = <0xe0 0x8>;
> +	};
> +
>  	pinctrl_aobus: pinctrl@84 {
>  		compatible = "amlogic,meson8-aobus-pinctrl";
>  		reg = <0x84 0xc>;
> @@ -249,6 +262,13 @@
>  	};
>  };
>  
> +&ahb_sram {
> +	smp-sram@1ff80 {
> +		compatible = "amlogic,meson8-smp-sram";
> +		reg = <0x1ff80 0x8>;
> +	};
> +};
> +
>  &ethmac {
>  	clocks = <&clkc CLKID_ETH>;
>  	clock-names = "stmmaceth";
> 

Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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[PATCH v4 7/7] ARM: dts: meson8b: add support for booting the secondary CPU cores

[Martin Blumenstingl]

From: Carlo Caione <carlo-KA+7E9HrN00dnm+yROfE0A@public.gmane.org>

Booting the secondary CPU cores involves the following nodes/devices:
- SCU (Snoop-Control-Unit, for which we already have a DT node)
- a reset line for each CPU core, provided by the reset-controller
  which is built into the clock-controller
- the PMU (power management unit) which controls the power of the CPU
  cores
- a range in the SRAM specifically reserved for booting secondary CPU
  cores
- the "enable-method" which activates booting the secondary CPU cores

This adds all required nodes and properties to boot the secondary CPU
cores.

Signed-off-by: Carlo Caione <carlo-KA+7E9HrN00dnm+yROfE0A@public.gmane.org>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
 arch/arm/boot/dts/meson8b.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index bc278da7df0d..c9e74d2fcbdf 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -59,6 +59,8 @@
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
 			reg = <0x200>;
+			enable-method = "amlogic,meson8b-smp";
+			resets = <&clkc RESETID_CPU0_SOFT_RESET>;
 		};
 
 		cpu@201 {
@@ -66,6 +68,8 @@
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
 			reg = <0x201>;
+			enable-method = "amlogic,meson8b-smp";
+			resets = <&clkc RESETID_CPU1_SOFT_RESET>;
 		};
 
 		cpu@202 {
@@ -73,6 +77,8 @@
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
 			reg = <0x202>;
+			enable-method = "amlogic,meson8b-smp";
+			resets = <&clkc RESETID_CPU2_SOFT_RESET>;
 		};
 
 		cpu@203 {
@@ -80,6 +86,8 @@
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
 			reg = <0x203>;
+			enable-method = "amlogic,meson8b-smp";
+			resets = <&clkc RESETID_CPU3_SOFT_RESET>;
 		};
 	};
 
@@ -90,6 +98,11 @@
 }; /* end of / */
 
 &aobus {
+	pmu: pmu@e0 {
+		compatible = "amlogic,meson8b-pmu", "syscon";
+		reg = <0xe0 0x18>;
+	};
+
 	pinctrl_aobus: pinctrl@84 {
 		compatible = "amlogic,meson8b-aobus-pinctrl";
 		reg = <0x84 0xc>;
@@ -157,6 +170,13 @@
 	};
 };
 
+&ahb_sram {
+	smp-sram@1ff80 {
+		compatible = "amlogic,meson8b-smp-sram";
+		reg = <0x1ff80 0x8>;
+	};
+};
+
 &ethmac {
 	clocks = <&clkc CLKID_ETH>;
 	clock-names = "stmmaceth";
-- 
2.13.3

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Re: [PATCH v4 7/7] ARM: dts: meson8b: add support for booting the secondary CPU cores

[Neil Armstrong]

Le 22/07/2017 21:19, Martin Blumenstingl a écrit :
> From: Carlo Caione <carlo-KA+7E9HrN00dnm+yROfE0A@public.gmane.org>
> 
> Booting the secondary CPU cores involves the following nodes/devices:
> - SCU (Snoop-Control-Unit, for which we already have a DT node)
> - a reset line for each CPU core, provided by the reset-controller
>   which is built into the clock-controller
> - the PMU (power management unit) which controls the power of the CPU
>   cores
> - a range in the SRAM specifically reserved for booting secondary CPU
>   cores
> - the "enable-method" which activates booting the secondary CPU cores
> 
> This adds all required nodes and properties to boot the secondary CPU
> cores.
> 
> Signed-off-by: Carlo Caione <carlo-KA+7E9HrN00dnm+yROfE0A@public.gmane.org>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> ---
>  arch/arm/boot/dts/meson8b.dtsi | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
> index bc278da7df0d..c9e74d2fcbdf 100644
> --- a/arch/arm/boot/dts/meson8b.dtsi
> +++ b/arch/arm/boot/dts/meson8b.dtsi
> @@ -59,6 +59,8 @@
>  			compatible = "arm,cortex-a5";
>  			next-level-cache = <&L2>;
>  			reg = <0x200>;
> +			enable-method = "amlogic,meson8b-smp";
> +			resets = <&clkc RESETID_CPU0_SOFT_RESET>;
>  		};
>  
>  		cpu@201 {
> @@ -66,6 +68,8 @@
>  			compatible = "arm,cortex-a5";
>  			next-level-cache = <&L2>;
>  			reg = <0x201>;
> +			enable-method = "amlogic,meson8b-smp";
> +			resets = <&clkc RESETID_CPU1_SOFT_RESET>;
>  		};
>  
>  		cpu@202 {
> @@ -73,6 +77,8 @@
>  			compatible = "arm,cortex-a5";
>  			next-level-cache = <&L2>;
>  			reg = <0x202>;
> +			enable-method = "amlogic,meson8b-smp";
> +			resets = <&clkc RESETID_CPU2_SOFT_RESET>;
>  		};
>  
>  		cpu@203 {
> @@ -80,6 +86,8 @@
>  			compatible = "arm,cortex-a5";
>  			next-level-cache = <&L2>;
>  			reg = <0x203>;
> +			enable-method = "amlogic,meson8b-smp";
> +			resets = <&clkc RESETID_CPU3_SOFT_RESET>;
>  		};
>  	};
>  
> @@ -90,6 +98,11 @@
>  }; /* end of / */
>  
>  &aobus {
> +	pmu: pmu@e0 {
> +		compatible = "amlogic,meson8b-pmu", "syscon";
> +		reg = <0xe0 0x18>;
> +	};
> +
>  	pinctrl_aobus: pinctrl@84 {
>  		compatible = "amlogic,meson8b-aobus-pinctrl";
>  		reg = <0x84 0xc>;
> @@ -157,6 +170,13 @@
>  	};
>  };
>  
> +&ahb_sram {
> +	smp-sram@1ff80 {
> +		compatible = "amlogic,meson8b-smp-sram";
> +		reg = <0x1ff80 0x8>;
> +	};
> +};
> +
>  &ethmac {
>  	clocks = <&clkc CLKID_ETH>;
>  	clock-names = "stmmaceth";
> 

Reviewed-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
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