From mboxrd@z Thu Jan 1 00:00:00 1970 From: Frank Rowand Subject: Re: more pedantic proofing of DTSpec version 0.1 Date: Tue, 5 Sep 2017 14:14:03 -0700 Message-ID: <59AF139B.5090501@gmail.com> References: <20170831205659.67fvxjdgggbifuy6@rob-hp-laptop> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20170831205659.67fvxjdgggbifuy6@rob-hp-laptop> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Rob Herring , "Robert P. J. Day" Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org On 08/31/17 13:56, Rob Herring wrote: > On Sat, Aug 26, 2017 at 10:50:46AM -0400, Robert P. J. Day wrote: >> < snip > >> p. 25: table 3.6, the acronym "PIR" comes out of nowhere, perhaps >> explain it the first time? > > I'm drawing a blank as to what that is. According to the Mindshare book: PowerPC System Architecture: "Processor ID Register (PIR) The PIR is a 32-bit register that can be used by the OS to assign an ID to the processor. Aside from any OS-specific usage of the assigned ID, the processor uses the ID when communicating with I/O devices." < snip > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html