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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id a7-20020a056402236700b0043570d96d25sm4522957eda.95.2022.06.25.13.01.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 25 Jun 2022 13:01:39 -0700 (PDT) Message-ID: <59c043a4-dd40-1f6b-69d2-bc32b970e874@linaro.org> Date: Sat, 25 Jun 2022 22:01:38 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH 1/2] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC Content-Language: en-US To: Lad Prabhakar , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Sagar Kadam , Palmer Dabbelt , Paul Walmsley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das References: <20220624180311.3007-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220624180311.3007-2-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Krzysztof Kozlowski In-Reply-To: <20220624180311.3007-2-prabhakar.mahadev-lad.rj@bp.renesas.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 24/06/2022 20:03, Lad Prabhakar wrote: > Document Renesas RZ/Five (R9A07G043) SoC. > > Signed-off-by: Lad Prabhakar > --- > RFC->v1: > * Fixed Review comments pointed by Geert and Rob > --- > .../sifive,plic-1.0.0.yaml | 40 +++++++++++++++++-- > 1 file changed, 36 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > index 27092c6a86c4..5eebe0b01b4d 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > @@ -28,7 +28,10 @@ description: > > While the PLIC supports both edge-triggered and level-triggered interrupts, > interrupt handlers are oblivious to this distinction and therefore it is not > - specified in the PLIC device-tree binding. > + specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's), > + but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need > + to specify the interrupt type as the flow for EDGE interrupts is different > + compared to LEVEL interrupts. > > While the RISC-V ISA doesn't specify a memory layout for the PLIC, the > "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that > @@ -57,6 +60,7 @@ properties: > - enum: > - allwinner,sun20i-d1-plic > - const: thead,c900-plic > + - const: renesas,r9a07g043-plic > > reg: > maxItems: 1 > @@ -64,8 +68,7 @@ properties: > '#address-cells': > const: 0 > > - '#interrupt-cells': > - const: 1 > + '#interrupt-cells': true > > interrupt-controller: true > > @@ -91,7 +94,36 @@ required: > - interrupts-extended > - riscv,ndev > > -additionalProperties: false > +if: Make it inside allOf. Avoids further indentation change on next variant. > + properties: > + compatible: > + contains: > + const: renesas,r9a07g043-plic > +then: > + properties: > + clocks: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + '#interrupt-cells': > + const: 2 > + > + required: > + - clocks > + - resets > + - power-domains > + > +else: > + properties: > + '#interrupt-cells': > + const: 1 > + > +unevaluatedProperties: false This does not look correct, why changing additional->unevaluated here? Best regards, Krzysztof