From: Wei Xu <xuwei5@hisilicon.com>
To: Krzysztof Kozlowski <krzk@kernel.org>, <linux-kernel@vger.kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>
Subject: Re: [PATCH] ARM: dts: hisilicon: Align L2 cache-controller nodename with dtschema
Date: Tue, 21 Jul 2020 10:43:59 +0800 [thread overview]
Message-ID: <5F16566F.1010807@hisilicon.com> (raw)
In-Reply-To: <20200626080637.4191-1-krzk@kernel.org>
Hi Krzysztof,
On 2020/6/26 16:06, Krzysztof Kozlowski wrote:
> Fix dtschema validator warnings like:
> l2-cache: $nodename:0: 'l2-cache' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Thanks!
Applied to the hisilicon arm32 dt tree.
Best Regards,
Wei
> ---
> arch/arm/boot/dts/hi3620.dtsi | 2 +-
> arch/arm/boot/dts/hisi-x5hd2.dtsi | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
> index 9c207a690df5..f0af1bf2b4d8 100644
> --- a/arch/arm/boot/dts/hi3620.dtsi
> +++ b/arch/arm/boot/dts/hi3620.dtsi
> @@ -71,7 +71,7 @@
> interrupt-parent = <&gic>;
> ranges = <0 0xfc000000 0x2000000>;
>
> - L2: l2-cache {
> + L2: cache-controller {
> compatible = "arm,pl310-cache";
> reg = <0x100000 0x100000>;
> interrupts = <0 15 4>;
> diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi
> index 696e6982a688..3ee7967c202d 100644
> --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
> +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
> @@ -381,7 +381,7 @@
> interrupts = <1 13 0xf01>;
> };
>
> - l2: l2-cache {
> + l2: cache-controller {
> compatible = "arm,pl310-cache";
> reg = <0x00a10000 0x100000>;
> interrupts = <0 15 4>;
>
prev parent reply other threads:[~2020-07-21 2:44 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-26 8:06 [PATCH] ARM: dts: hisilicon: Align L2 cache-controller nodename with dtschema Krzysztof Kozlowski
2020-07-21 2:43 ` Wei Xu [this message]
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