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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34912d36fc0sm1546875a91.12.2025.12.03.18.53.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 Dec 2025 18:54:04 -0800 (PST) Message-ID: <5a0e4abf-9e7f-4ef9-af02-dd6e34f5cfa8@oss.qualcomm.com> Date: Thu, 4 Dec 2025 10:53:55 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 6/9] dt-bindings: arm: add an interrupt property for Coresight CTCU To: Suzuki K Poulose , Jie Gan , Mike Leach , James Clark , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Jinlong Mao , Bjorn Andersson , Konrad Dybcio Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski References: <20250908-enable-byte-cntr-for-tmc-v6-0-1db9e621441a@oss.qualcomm.com> <20250908-enable-byte-cntr-for-tmc-v6-6-1db9e621441a@oss.qualcomm.com> <66d4488f-941a-4716-b81f-e0f9e1165931@arm.com> Content-Language: en-US From: Jie Gan In-Reply-To: <66d4488f-941a-4716-b81f-e0f9e1165931@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: yYaQaUWeQ8lbk1SG1Ub4Rglrb1iB1XfX X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA0MDAyMSBTYWx0ZWRfX6ZpMCqXPf+4O ES2gfN7lTr1F1pKF7T9HjRXRomH/+s0hDGzQq3qRalP2XY38dzTZ4nFsBnZexWXBQbTCpSuhqSx ob03ksKsgWET8aiCT7a9YvLFGnO+QxrCvfToZi+yf5zRswRJotm6+BHMBt9QSre+Cgaes4ilC5/ R4EKUAxyga5hiwA7oJgqAtXtmPXublmPVyaMfQNf8WWc/rR62ElMDz3SPee8zYmeMo2WV6K5eUf T9gWippYGic1wVwGYTzB6iOc0m7qqswKAebpD9DClI3CTMnOlz7+sd/iVFPUxeQJG+PMr/QtY82 iWAQXP3rMbnWriLO5P1y2lyl85S13CnvDRvtAJazAcvaU6r9fVOyxLZ+0TmuUIWJIoDI1o+M23l OvqOZLdBQ0vtGOduFTK47CHK0NX5Iw== X-Authority-Analysis: v=2.4 cv=dfONHHXe c=1 sm=1 tr=0 ts=6930f7ce cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=SkUS4XPTP4F0jhogtscA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: yYaQaUWeQ8lbk1SG1Ub4Rglrb1iB1XfX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-04_01,2025-12-03_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 phishscore=0 clxscore=1015 spamscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512040021 On 12/4/2025 2:14 AM, Suzuki K Poulose wrote: > On 08/09/2025 03:01, Jie Gan wrote: >> Add an interrupt property to CTCU device. The interrupt will be triggered >> when the data size in the ETR buffer exceeds the threshold of the >> BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register >> of CTCU device will enable the interrupt. >> >> Acked-by: Krzysztof Kozlowski >> Signed-off-by: Jie Gan >> --- >>   .../devicetree/bindings/arm/qcom,coresight-ctcu.yaml    | 17 +++++++ >> ++++++++++ >>   1 file changed, 17 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight- >> ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight- >> ctcu.yaml >> index 843b52eaf872..ea05ad8f3dd3 100644 >> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml >> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml >> @@ -39,6 +39,16 @@ properties: >>       items: >>         - const: apb >> +  interrupts: >> +    items: >> +      - description: Byte cntr interrupt for etr0 >> +      - description: Byte cntr interrupt for etr1 >> + >> +  interrupt-names: >> +    items: >> +      - const: etr0 >> +      - const: etr1 > Hi Suzuki, > Why are they named "etr0" "etr1" ? That would be confusing, isn't it, > especially with the Linux driver naming things randomly for the TMC-ETRs. > Yes, it will cause misunderstandings since the "etr0" here may not the right device we are expecting. > > What we want is the "port" number corresponding to the "TMC-ETR" being > monitored ? > > Have you explored other options, "port-0", "port-1" ? > I think it's much better. Will update in next version. Thanks, Jie > Suzuki > >> + >>     in-ports: >>       $ref: /schemas/graph.yaml#/properties/ports >> @@ -56,6 +66,8 @@ additionalProperties: false >>   examples: >>     - | >> +    #include >> + >>       ctcu@1001000 { >>           compatible = "qcom,sa8775p-ctcu"; >>           reg = <0x1001000 0x1000>; >> @@ -63,6 +75,11 @@ examples: >>           clocks = <&aoss_qmp>; >>           clock-names = "apb"; >> +        interrupts = , >> +                     ; >> +        interrupt-names = "etr0", >> +                          "etr1"; >> + >>           in-ports { >>               #address-cells = <1>; >>               #size-cells = <0>; >> > >