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[2003:f6:ef1c:c500:ee59:d953:f148:40ba]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5a3228723bcsm7059341a12.48.2024.07.23.00.57.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jul 2024 00:57:35 -0700 (PDT) Message-ID: <5b246e7628ea189be5f8430dac4cffde723b7907.camel@gmail.com> Subject: Re: [PATCH RFC v3 6/9] spi: axi-spi-engine: implement offload support From: Nuno =?ISO-8859-1?Q?S=E1?= To: David Lechner , Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nuno =?ISO-8859-1?Q?S=E1?= Cc: Michael Hennerich , Lars-Peter Clausen , David Jander , Martin Sperl , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org Date: Tue, 23 Jul 2024 10:01:32 +0200 In-Reply-To: <20240722-dlech-mainline-spi-engine-offload-2-v3-6-7420e45df69b@baylibre.com> References: <20240722-dlech-mainline-spi-engine-offload-2-v3-0-7420e45df69b@baylibre.com> <20240722-dlech-mainline-spi-engine-offload-2-v3-6-7420e45df69b@baylibre.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.3 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Mon, 2024-07-22 at 16:57 -0500, David Lechner wrote: > This implements SPI offload support for the AXI SPI Engine. Currently, > the hardware only supports triggering offload transfers with a hardware > trigger so attempting to use an offload message in the regular SPI > message queue will fail. Also, only allows streaming rx data to an > external sink, so attempts to use a rx_buf in the offload message will > fail. >=20 > Signed-off-by: David Lechner > --- >=20 ... I'm likely missing something but you already have: priv =3D &spi_engine->offload_priv[args[0]]; which seems that from FW you already got the offload index you need. Can't = we just save that index in struct spi_device and use that directly in the othe= r operations? Saving the trouble to save the id string and having to always c= all=20 spi_engine_get_offload()? > + >=20 ... > +} > + > +static void spi_engine_offload_unprepare(struct spi_device *spi, const c= har > *id) > +{ > + struct spi_controller *host =3D spi->controller; > + struct spi_engine *spi_engine =3D spi_controller_get_devdata(host); > + struct spi_engine_offload *priv; > + unsigned int offload_num; > + > + priv =3D spi_engine_get_offload(spi, id, &offload_num); > + if (IS_ERR(priv)) { > + dev_warn(&spi->dev, "failed match offload in unprepare\n"); > + return; > + } > + > + writel_relaxed(1, spi_engine->base + > SPI_ENGINE_REG_OFFLOAD_RESET(offload_num)); > + writel_relaxed(0, spi_engine->base + > SPI_ENGINE_REG_OFFLOAD_RESET(offload_num)); > + > + priv->prepared =3D false; > +} > + > +static int spi_engine_hw_trigger_mode_enable(struct spi_device *spi, > + =C2=A0=C2=A0=C2=A0=C2=A0 const char *id) > +{ > + struct spi_controller *host =3D spi->controller; > + struct spi_engine *spi_engine =3D spi_controller_get_devdata(host); > + struct spi_engine_offload *priv; > + unsigned int offload_num, reg; > + > + priv =3D spi_engine_get_offload(spi, id, &offload_num); > + if (IS_ERR(priv)) > + return PTR_ERR(priv); > + > + reg =3D readl_relaxed(spi_engine->base + > + =C2=A0=C2=A0=C2=A0 SPI_ENGINE_REG_OFFLOAD_CTRL(offload_num)); > + reg |=3D SPI_ENGINE_OFFLOAD_CTRL_ENABLE; > + writel_relaxed(reg, spi_engine->base + > + =C2=A0=C2=A0=C2=A0 SPI_ENGINE_REG_OFFLOAD_CTRL(offload_num)); > + > + return 0; > +} > + > +static void spi_engine_hw_trigger_mode_disable(struct spi_device *spi, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 const char *id) > +{ > + struct spi_controller *host =3D spi->controller; > + struct spi_engine *spi_engine =3D spi_controller_get_devdata(host); > + struct spi_engine_offload *priv; > + unsigned int offload_num, reg; > + > + priv =3D spi_engine_get_offload(spi, id, &offload_num); > + if (IS_ERR(priv)) { > + dev_warn(&spi->dev, "failed match offload in disable\n"); > + return; > + } > + > + reg =3D readl_relaxed(spi_engine->base + > + =C2=A0=C2=A0=C2=A0 SPI_ENGINE_REG_OFFLOAD_CTRL(offload_num)); > + reg &=3D ~SPI_ENGINE_OFFLOAD_CTRL_ENABLE; > + writel_relaxed(reg, spi_engine->base + > + =C2=A0=C2=A0=C2=A0 SPI_ENGINE_REG_OFFLOAD_CTRL(offload_num)); > +} > + I would expect for the enable/disable() operations to act on the trigger. I= n this case to enable/disable the clock... - Nuno S=C3=A1