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Mon, 21 Jul 2025 10:13:11 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGe2/ShNvywiZ+DxmeZg+ZMZ/GKOcyhXqBS+iKk7LMIrbdvIY81RYqsoTDycOuer7bfi9e1ag== X-Received: by 2002:a05:6a20:9392:b0:1f5:8a1d:3905 with SMTP id adf61e73a8af0-23810d55d86mr34423411637.7.1753117991359; Mon, 21 Jul 2025 10:13:11 -0700 (PDT) Received: from [192.168.0.195] ([49.204.29.160]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b3f2fe659a5sm5633550a12.4.2025.07.21.10.13.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 21 Jul 2025 10:13:10 -0700 (PDT) Message-ID: <5b569e5f-066b-4e12-8a05-d77852ce11f6@oss.qualcomm.com> Date: Mon, 21 Jul 2025 22:43:05 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 7/7] clk: qcom: gcc: Add support for Global Clock Controller To: Bjorn Andersson Cc: Krzysztof Kozlowski , Abel Vesa , Pankaj Patil , sboyd@kernel.org, mturquette@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_rjendra@quicinc.com, linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250716152017.4070029-1-pankaj.patil@oss.qualcomm.com> <20250716152017.4070029-8-pankaj.patil@oss.qualcomm.com> <40534488-24f6-4958-b032-d45a177dfd80@kernel.org> <2f5b5e6e-5041-453e-b3f7-b10b40bc6f57@oss.qualcomm.com> <52ytt5ag5l65hdjjmvjft2l7ofvt4rgdn6r3bytcpjvyqia7ry@uzajn7qjng4a> Content-Language: en-US From: Taniya Das In-Reply-To: <52ytt5ag5l65hdjjmvjft2l7ofvt4rgdn6r3bytcpjvyqia7ry@uzajn7qjng4a> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIxMDE1MSBTYWx0ZWRfX4Hg4SVWXBOHO vcMnnnxTp9X5WESHLxLjBujDzx4fKbCkJzCPUZS/bVaQ6gbA/NSz8uaBM+G1h3jxBr6BDvHMz0b siqVbQu6eXWAGgjW0qG4u5WKwCXVZ7UsSc/dqDJgZFq8uDkZVrBn0HWQuCPmXxVkDWU1Vc718Xj c/yXG0jxLqs874j6a/ZIAkXvyrB9nrUXXhoF+/53kk27CbM8UbmJjuPx4vTRpaBl3zTepgTfBg7 LYC7/dW/g3wWsUdriCt072ZzqBgy4SXEhBDg8B9cEvxYhhfVPNVgDSUkp+PD+CiMENwFqja+cFP ge5tSXxZMepldkFrdjI65oF9U1nVMVBMvwuZQMxIANckJm+qgLkjt8XS1EBj6oipvyhFy7q7d+u lXyz0TVvLtvSViowTAytbq84dod676U9Jsv6jIfRyEl/+eaEIUWnZkOqvUxOKHNmzyNIe0E8 X-Proofpoint-ORIG-GUID: nwxUbZqIGFxGLLzy24iIKntORuJl-KVe X-Proofpoint-GUID: nwxUbZqIGFxGLLzy24iIKntORuJl-KVe X-Authority-Analysis: v=2.4 cv=IrMecK/g c=1 sm=1 tr=0 ts=687e7529 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=7nFZtJUvBAfdOgjOLm7NAA==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=9SSxU1ZdH87hVqYcdAkA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-21_04,2025-07-21_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 clxscore=1015 priorityscore=1501 spamscore=0 mlxscore=0 mlxlogscore=999 phishscore=0 impostorscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507210151 On 7/20/2025 9:30 AM, Bjorn Andersson wrote: > On Fri, Jul 18, 2025 at 11:07:23PM +0530, Taniya Das wrote: >> >> >> On 7/17/2025 3:38 PM, Krzysztof Kozlowski wrote: >>> On 17/07/2025 11:57, Abel Vesa wrote: >>>> On 25-07-16 20:50:17, Pankaj Patil wrote: >>>>> From: Taniya Das >>>>> >>>>> Add support for Global clock controller for Glymur platform. >>>>> >>>>> Signed-off-by: Taniya Das >>>>> Signed-off-by: Pankaj Patil >>>>> --- >>>>> drivers/clk/qcom/Kconfig | 10 + >>>>> drivers/clk/qcom/Makefile | 1 + >>>>> drivers/clk/qcom/gcc-glymur.c | 8623 +++++++++++++++++++++++++++++++++ >>>>> 3 files changed, 8634 insertions(+) >>>>> create mode 100644 drivers/clk/qcom/gcc-glymur.c >>>>> >>>>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig >>>>> index 051301007aa6..1d9e8c6aeaed 100644 >>>>> --- a/drivers/clk/qcom/Kconfig >>>>> +++ b/drivers/clk/qcom/Kconfig >>>>> @@ -645,6 +645,16 @@ config SAR_GPUCC_2130P >>>>> Say Y if you want to support graphics controller devices and >>>>> functionality such as 3D graphics. >>>>> >>>>> +config SC_GCC_GLYMUR >>>> >>>> Wait, are we going back to this now? >>>> >>>> X Elite had CLK_X1E80100_GCC, so maybe this should be CLK_GLYMUR_GCC >>>> then. >>> >>> >>> Yeah, the SC is meaningless here, unless you call it CLK_SC8480XP_GCC, >>> so the authors need to decide on one naming. Not mixtures.. >>> >>> >> Glymur follows the "SC" naming convention, and historically we've >> adhered to the format: "SC/SM/SDX/SA__> Chipset>". This structure has helped maintain consistency and clarity >> across platforms. >> > > The platform isn't named SCGLYMUR - which is where the SC prefix would > come from. > > I'm not sure there's a benefit to quickly be able to know if a clock > controller is for a SC, SM, SA, MSM, etc platform. Please let me know if > I'm missing something. > Bjorn it was more of an alignment for "Compute", "Mobile" and so on and such was the definition to be used for the clock controllers as well. >> The case of X1E80100 appears to be an exception—likely influenced by its >> unique naming convention at the time. >> >> That said, I’d prefer to stay aligned with the established convention >> used for earlier chipsets to preserve continuity. I’d appreciate hearing >> your thoughts on this as well. >> > > We're changing the naming model completely, so there is no continuity. > In fact the Hamoa "exception" would suite us very well for Glymur. > > And look how nicely the CLK_X1E80100_* entries are grouped together in > the Kconfig. > > Change to CLK_GLYMUR_* please. > Sure, will align, but hope we are all good with the clock driver name -.c. -- Thanks, Taniya Das