From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49B8D29405; Mon, 28 Jul 2025 05:01:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753678899; cv=none; b=XH0SzjCN18DiGLVq0iz49VpXeQT6NoRYNJuhVI5HB4O7jmg6uBzhNWLLeWq1+oj4gMcwSxtQsw4A1WP9+fdNQYul9LByZniyC16xKo0nlqU/1ftABjteISYKgPgOxH5eFhHLeg1TtR/QOx/yHFMUXM8tUx9Lr4yS/8L8BYUDXDU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753678899; c=relaxed/simple; bh=h2t9VTTQvPqtnd9UzMdzQzgUqidHexMKRE2szkipEdA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=ZSQvK+mVmzq3ZomhnFGudu86eHYOQIWiMGccYX3Gm3zeq9lnbUnPM0S4YafPFCUJ5gjO8/vgYCXytAlRcfDi6xlg1ji//ZLbp+1/FhE4om7xYgYgTgYdGtwc5RpgM7weUsbxAds8VkqCsubP6OCylrAO/gu1M49huZTIWmPJk84= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EXNaKFBR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EXNaKFBR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BE5D3C4CEE7; Mon, 28 Jul 2025 05:01:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753678896; bh=h2t9VTTQvPqtnd9UzMdzQzgUqidHexMKRE2szkipEdA=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=EXNaKFBRdbopl6nr3kNPc+/DouSIxexmqT5HFrpckAEnXXMGix6yizKJoWFAoxdkJ b+bVnnmmdkE9iFP8603Szq479ZfWotj+5h6TcepiUsrO/EJSU18AUqeAPMd/FfmSjd DNVgEzSIBtSv5Hnq8nyIJYf8XCyjdbk5lyXb0T4WbcqBbOSaDYc/E54Xj7oIfI9njV 3mD9FKjD6iadgDe3tkoNi5yCc1XvLEReI+/a6/zvn03wCp1WFUnYPZVTR6vt6saGkr Y216jJKItQto4xX1digPCX6XOAPmj5C5H1TcUVGQxyRtr78ME8DuEJ6C8iZuuxkR4W 3+FzZ0o0lraOw== Message-ID: <5b8d42d5-d034-4495-9d28-27478a606d62@kernel.org> Date: Mon, 28 Jul 2025 07:01:31 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] dt-bindings: clock: qcom: Add SM8750 GPU clocks To: Konrad Dybcio , Konrad Dybcio Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250723-topic-8750_gpucc-v2-0-56c93b84c390@oss.qualcomm.com> <20250723-topic-8750_gpucc-v2-1-56c93b84c390@oss.qualcomm.com> <20250724-blazing-therapeutic-python-1e96ca@kuoka> <54b617c1-bd1b-4244-b75d-57eaaa2c083d@oss.qualcomm.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 25/07/2025 11:30, Konrad Dybcio wrote: >>> >>> @@ -40,6 +42,9 @@ properties: >>> - description: GPLL0 main branch source >>> - description: GPLL0 div branch source >>> >>> + power-domains: >>> + maxItems: 1 >> >> This should be a different binding or you need to restrict other >> variants here. > > Actually looks like this is the same case as the recent videocc changes > (15 year old technical debt catching up to us..) > > I'll send a mass-fixup for this. > > Some platforms require 2 and some require 3 entries here. Do I have to > restrict them very specifically, or can I do: > > power-domains: > description: > Power domains required for the clock controller to operate > minItems: 2 > items: > - description: CX power domain > - description: MX power domain > - description: MXC power domain > > ? This is correct and should be in top level, but you still need to restrict them per each variant (minItems: 3 or maxItems: 2). > > Konrad Best regards, Krzysztof