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Tue, 22 Apr 2025 16:23:08 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 53MGN7IT009702 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Apr 2025 16:23:07 GMT Received: from [10.216.4.61] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 22 Apr 2025 09:23:03 -0700 Message-ID: <5be729d9-aef0-4c35-a09e-06bb24ad5427@quicinc.com> Date: Tue, 22 Apr 2025 21:52:59 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 2/8] arm64: dts: qcom: sc7280: Add WSA SoundWire and LPASS support To: Bryan O'Donoghue , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , , Mohammad Rafi Shaik References: <20250317054151.6095-1-quic_pkumpatl@quicinc.com> <20250317054151.6095-3-quic_pkumpatl@quicinc.com> <9fd63681-28c3-4797-9ed0-f4b05e77e330@linaro.org> Content-Language: en-US From: Prasad Kumpatla In-Reply-To: <9fd63681-28c3-4797-9ed0-f4b05e77e330@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=EOYG00ZC c=1 sm=1 tr=0 ts=6807c26c cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=SpwO9IhAAyP49T1mwoIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: l3htXu3c7S_uMD42e52exv54Qt98Ln3k X-Proofpoint-ORIG-GUID: l3htXu3c7S_uMD42e52exv54Qt98Ln3k X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-22_08,2025-04-22_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=999 mlxscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 priorityscore=1501 phishscore=0 spamscore=0 adultscore=0 impostorscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504220122 On 3/27/2025 4:32 AM, Bryan O'Donoghue wrote: > On 17/03/2025 05:41, Prasad Kumpatla wrote: >> From: Mohammad Rafi Shaik >> >> Add WSA macroLPASS Codecs along with SoundWire controller. >> >> Signed-off-by: Mohammad Rafi Shaik >> Co-developed-by: Prasad Kumpatla >> Signed-off-by: Prasad Kumpatla >> --- >>   arch/arm64/boot/dts/qcom/sc7280.dtsi | 68 ++++++++++++++++++++++++++++ >>   1 file changed, 68 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 39fbd3c40e47..90b2f6e2b7c0 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -2602,6 +2602,64 @@ swr1: soundwire@3230000 { >>               status = "disabled"; >>           }; >> >> +        lpass_wsa_macro: codec@3240000 { >> +            compatible = "qcom,sc7280-lpass-wsa-macro"; >> +            reg = <0x0 0x03240000 0x0 0x1000>; >> + >> +            pinctrl-names = "default"; >> +            pinctrl-0 = <&lpass_wsa_swr_clk>, <&lpass_wsa_swr_data>; >> + >> +            clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, >> +                 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, >> +                 <&lpass_va_macro>; >> +            clock-names = "mclk", "npl", "fsgen"; > > clocks* go before pinctrl* ACK, > >> + >> +            power-domains = <&lpass_hm >> LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, >> +                    <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; >> +            power-domain-names = "macro", "dcodec"; >> + >> +            #clock-cells = <0>; >> +            clock-output-names = "mclk"; >> +            #sound-dai-cells = <1>; >> + >> +            status = "disabled"; >> +        }; >> + >> +        swr2: soundwire@3250000 { >> +            compatible = "qcom,soundwire-v1.6.0"; >> +            reg = <0x0 0x03250000 0x0 0x2000>; >> + >> +            interrupts = ; >> +            clocks = <&lpass_wsa_macro>; >> +            clock-names = "iface"; >> + >> +            qcom,din-ports = <2>; >> +            qcom,dout-ports = <6>; >> + >> +            resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; >> +            reset-names = "swr_audio_cgcr"; > > vendor prefixes should come after standard names > > Documentation/devicetree/bindings/dts-coding-style.rst > "Order of Properties in Device Node" ACK, will check and update in next patch version. Thanks, Prasad > >> + >> +            qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 >> +                                0x1f 0x3f 0x0f 0x0f>; >> +            qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 >> 0x0d 0x07 0x0a>; >> +            qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 >> 0x1f 0x00 0x00>; >> +            qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff >> 0xff 0xff 0xff>; >> +            qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff >> 0xff 0xff 0xff>; >> +            qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff >> 0xff 0xff 0xff 0xff>; >> +            qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 >> 0xff 0xff 0x01 >> +                                   0xff 0xff>; >> +            qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff >> 0xff 0xff 0xff >> +                                0xff 0xff>; >> +            qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff >> 0xff 0xff >> +                                0xff 0xff>; >> + >> +            #address-cells = <2>; >> +            #size-cells = <0>; >> +            #sound-dai-cells = <1>; >> + >> +            status = "disabled"; >> +        }; >> + >>           lpass_audiocc: clock-controller@3300000 { >>               compatible = "qcom,sc7280-lpassaudiocc"; >>               reg = <0 0x03300000 0 0x30000>, >> @@ -2808,6 +2866,16 @@ lpass_tx_swr_data: tx-swr-data-state { >>                   pins = "gpio1", "gpio2", "gpio14"; >>                   function = "swr_tx_data"; >>               }; >> + >> +            lpass_wsa_swr_clk: wsa-swr-clk-state { >> +                pins = "gpio10"; >> +                function = "wsa_swr_clk"; >> +            }; >> + >> +            lpass_wsa_swr_data: wsa-swr-data-state { >> +                pins = "gpio11"; >> +                function = "wsa_swr_data"; >> +            }; >>           }; >> >>           gpu: gpu@3d00000 { >> -- >> 2.34.1 >> >> >