From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Cc: Abhinav Kumar <quic_abhinavk@quicinc.com>,
Sean Paul <sean@poorly.run>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Krishna Manikandan <quic_mkrishn@quicinc.com>,
Jonathan Marek <jonathan@marek.ca>,
Kuogee Hsieh <quic_khsieh@quicinc.com>,
Neil Armstrong <neil.armstrong@linaro.org>,
Dmitry Baryshkov <lumag@kernel.org>,
Rob Clark <robdclark@gmail.com>,
Bjorn Andersson <andersson@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Rob Clark <robdclark@chromium.org>,
linux-clk@vger.kernel.org, Srinivas Kandagatla <srini@kernel.org>
Subject: Re: [PATCH v5 19/24] drm/msm/dsi: Add support for SM8750
Date: Mon, 5 May 2025 08:45:01 +0200 [thread overview]
Message-ID: <5c307e88-a3fc-430b-8ccc-af59e2097da3@linaro.org> (raw)
In-Reply-To: <ahx623ttvzd62u4fri6iqguj7mirlf22tvwbu6k2ngxw6hwbcp@oh7mmex5fjmz>
On 03/05/2025 00:52, Dmitry Baryshkov wrote:
> On Wed, Apr 30, 2025 at 03:00:49PM +0200, Krzysztof Kozlowski wrote:
>> Add support for DSI on Qualcomm SM8750 SoC with notable difference:
>>
>> DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
>> parents before DSI PHY is configured, the PLLs are prepared and their
>> initial rate is set. Therefore assigned-clock-parents are not working
>> here and driver is responsible for reparenting clocks with proper
>> procedure: see dsi_clk_init_6g_v2_9().
>
> Is it still the case? I thought you've said that with the proper flags
Yes, as we discussed many times - this is still needed even with the
proper flags.
> there would be no need to perform this in the driver.
assigned-clock-xxx are not respecting that flag and anyway, even if that
was solved, they are executed too early - before PHY is initialized. You
cannot prepare PHY PLL before PHY is initialized and enabled.
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-05-05 6:45 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-30 13:00 [PATCH v5 00/24] drm/msm: Add support for SM8750 Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 01/24] dt-bindings: display/msm: dsi-phy-7nm: Add SM8750 Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 02/24] dt-bindings: display/msm: dsi-controller-main: " Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 03/24] dt-bindings: display/msm: dp-controller: " Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 04/24] dt-bindings: display/msm: qcom,sm8650-dpu: " Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 05/24] dt-bindings: display/msm: qcom,sm8750-mdss: " Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 06/24] clk: qcom: dispcc-sm8750: Fix setting rate byte and pixel clocks Krzysztof Kozlowski
2025-05-02 22:42 ` Dmitry Baryshkov
2025-05-05 6:15 ` Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 07/24] drm/msm/dpu: Add missing "fetch" name to set_active_pipes() Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 08/24] drm/msm/dpu: Clear CTL_FETCH_PIPE_ACTIVE on mixer reset Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 09/24] drm/msm/dpu: Clear CTL_FETCH_PIPE_ACTIVE on ctl_path reset Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 10/24] drm/msm/dpu: Clear CTL_FETCH_PIPE_ACTIVE before blend setup Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 11/24] drm/msm/dpu: Drop useless comments Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 12/24] drm/msm/dpu: Add LM_7, DSC_[67], PP_[67] and MERGE_3D_5 Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 13/24] drm/msm/dpu: Add handling of LM_6 and LM_7 bits in pending flush mask Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 14/24] drm/msm/dsi/phy: Toggle back buffer resync after preparing PLL Krzysztof Kozlowski
2025-05-02 22:43 ` Dmitry Baryshkov
2025-04-30 13:00 ` [PATCH v5 15/24] drm/msm/dsi/phy: Define PHY_CMN_CTRL_0 bitfields Krzysztof Kozlowski
2025-05-02 22:44 ` Dmitry Baryshkov
2025-05-05 6:17 ` Krzysztof Kozlowski
2025-05-05 14:14 ` Dmitry Baryshkov
2025-05-20 10:57 ` Krzysztof Kozlowski
2025-05-20 21:23 ` Dmitry Baryshkov
2025-05-21 6:11 ` Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 16/24] drm/msm/dsi/phy: Fix reading zero as PLL rates when unprepared Krzysztof Kozlowski
2025-04-30 13:11 ` Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 17/24] drm/msm/dsi/phy: Fix missing initial VCO rate Krzysztof Kozlowski
2025-05-02 22:48 ` Dmitry Baryshkov
2025-04-30 13:00 ` [PATCH v5 18/24] drm/msm/dsi/phy: Add support for SM8750 Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 19/24] drm/msm/dsi: " Krzysztof Kozlowski
2025-05-02 22:52 ` Dmitry Baryshkov
2025-05-05 6:45 ` Krzysztof Kozlowski [this message]
2025-05-05 12:26 ` Dmitry Baryshkov
2025-05-05 12:35 ` Dmitry Baryshkov
2025-05-05 21:28 ` Abhinav Kumar
2025-05-19 15:11 ` Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 20/24] drm/msm/dpu: " Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 21/24] drm/msm/dpu: Implement 10-bit color alpha for v12.0 DPU Krzysztof Kozlowski
2025-05-05 12:24 ` Dmitry Baryshkov
2025-05-19 16:49 ` Abhinav Kumar
2025-05-19 16:53 ` Dmitry Baryshkov
2025-05-23 6:55 ` Abel Vesa
2025-05-23 7:02 ` Abel Vesa
2025-05-23 8:29 ` Dmitry Baryshkov
2025-05-23 9:50 ` Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 22/24] drm/msm/dpu: Implement CTL_PIPE_ACTIVE " Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 23/24] drm/msm/dpu: Implement LM crossbar " Krzysztof Kozlowski
2025-04-30 13:00 ` [PATCH v5 24/24] drm/msm/mdss: Add support for SM8750 Krzysztof Kozlowski
2025-05-17 0:08 ` [PATCH v5 00/24] drm/msm: " Jessica Zhang
2025-05-19 14:52 ` Krzysztof Kozlowski
2025-05-19 15:07 ` Dmitry Baryshkov
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