From: "Jiaxun Yang" <jiaxun.yang@flygoat.com>
To: "Conor Dooley" <conor@kernel.org>
Cc: "Rob Herring" <robh@kernel.org>, "Lee Jones" <lee@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"paulburton@kernel.org" <paulburton@kernel.org>,
"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
"linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>
Subject: Re: [PATCH v2 7/8] du-bindings: mips: cpu: Add img,mips compatible
Date: Sat, 15 Jun 2024 20:16:11 +0100 [thread overview]
Message-ID: <5c51085b-6e6c-47f8-a68a-829ddc7ba74d@app.fastmail.com> (raw)
In-Reply-To: <20240615-reaction-movie-b4c21f2c7d91@spud>
在2024年6月15日六月 下午1:28,Conor Dooley写道:
> On Thu, Jun 13, 2024 at 08:40:18PM +0100, Jiaxun Yang wrote:
>>
>>
>> 在2024年6月13日六月 下午7:59,Rob Herring写道:
>> > On Wed, Jun 12, 2024 at 05:59:24PM +0100, Jiaxun Yang wrote:
>> >>
>> >>
>> >> 在2024年6月12日六月 下午5:39,Conor Dooley写道:
>> >> > On Wed, Jun 12, 2024 at 12:56:26PM +0100, Jiaxun Yang wrote:
>> >> >> This compatible is used by boston.dts.
>> >> >>
>> >> >> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> >> >> ---
>> >> >> note: This is a wildcard compatible for all MIPS CPUs,
>> >> >> I think we should use something like "riscv" for riscv.
>> >> >
>> >> > riscv systems, other than simulators etc are not meant to use the
>> >> > "riscv" compatible. All of the real CPUs use "vendor,cpu", "riscv".
>> >> > I'd suggest you add specific compatibles for your CPUs.
>> >>
>> >> Boston can be combined with many different CPUs, thus we need to have
>> >> such compatibles.
>> >
>> > Then you'll need different DTs. Different h/w, different DT.
>>
>> The board have 9 CPU types in total, with hundreds of different possible
>> CPU topologies. Maintaining separate DT for them seems impossible in kernel.
>
> But you could definitely add 9 different compatibles for each of these
> different CPUs.
They are already in current bindings, but we need a default one to fill
in kernel dts.
>
>> We can potentially patch this in bootloader, but for existing firmware it's
>> being doing like this for years. I can see for RISC-V QEMU generated DTB is
>> using a single "riscv" compatible and I do think it's a similar problem.
>
> That "riscv" compatible is only supposed to be used for
> simulators/software models. Real CPUs are not meant to use it. AFAICT,
> your boston is a real platform, even if the CPUs are implemented on an
> FPGA they should still have one. If you take the OpenC906 RISC-V CPU and
> put it on an FPGA, you're still meant to put "thead,c906" in your DT.
>
And sadly, boston is also the platform used by MIPS internal emulators :-(
Thanks
- Jiaxun
>
> 附件:
> * signature.asc
--
- Jiaxun
next prev parent reply other threads:[~2024-06-15 19:16 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-12 11:56 [PATCH v2 0/8] MIPS: Boston: Fix syscon devicetree binding and node Jiaxun Yang
2024-06-12 11:56 ` [PATCH v2 1/8] MIPS: dts: Boston: Add simple-mfd compatible for syscon Jiaxun Yang
2024-06-12 11:56 ` [PATCH v2 2/8] MIPS: dts: Boston: Move syscon-reboot node under syscon Jiaxun Yang
2024-06-12 11:56 ` [PATCH v2 3/8] MIPS: dts: Boston: Remove unused #interrupt-cells Jiaxun Yang
2024-06-12 11:56 ` [PATCH v2 4/8] MIPS: dts: Boston: Add model property Jiaxun Yang
2024-06-12 11:56 ` [PATCH v2 5/8] MIPS: dts: Boston: Rename uart node Jiaxun Yang
2024-06-12 11:56 ` [PATCH v2 6/8] dt-bindings: mfd: Add img,boston-platform-regs Jiaxun Yang
2024-06-13 19:04 ` Rob Herring
2024-06-13 19:31 ` Jiaxun Yang
2024-06-12 11:56 ` [PATCH v2 7/8] du-bindings: mips: cpu: Add img,mips compatible Jiaxun Yang
2024-06-12 16:39 ` Conor Dooley
2024-06-12 16:59 ` Jiaxun Yang
2024-06-13 18:59 ` Rob Herring
2024-06-13 19:40 ` Jiaxun Yang
2024-06-15 12:28 ` Conor Dooley
2024-06-15 19:16 ` Jiaxun Yang [this message]
2024-06-19 18:13 ` Conor Dooley
2024-06-12 11:56 ` [PATCH v2 8/8] dt-bindings: mips: img: Add devices binding Jiaxun Yang
2024-06-12 16:43 ` Conor Dooley
2024-06-12 16:57 ` Jiaxun Yang
2024-06-12 16:59 ` Conor Dooley
2024-06-13 18:56 ` Rob Herring
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