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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34ed530475bsm3298572a91.8.2025.12.24.18.57.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 24 Dec 2025 18:57:52 -0800 (PST) Message-ID: <5c67a270-dc9e-4ada-af56-e97d4a925e47@oss.qualcomm.com> Date: Thu, 25 Dec 2025 10:57:46 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 1/7] dt-bindings: arm: Add support for Qualcomm TGU trace To: Songwei Chai , andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org, Rob Herring References: <20251219065902.2296896-1-songwei.chai@oss.qualcomm.com> <20251219065902.2296896-2-songwei.chai@oss.qualcomm.com> Content-Language: en-US From: Jie Gan In-Reply-To: <20251219065902.2296896-2-songwei.chai@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: Qhq7LeLpQk0Y_W3hNLWjgqXLw519K0ba X-Authority-Analysis: v=2.4 cv=esbSD4pX c=1 sm=1 tr=0 ts=694ca832 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gEfo2CItAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=IwjJGIUIzvyStixYlZUA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjI1MDAyNiBTYWx0ZWRfX/4jA6HOvscYW urEYhXH0lqo67zAPvRYTjgEY0trzZHPOj+SPHIRhZFgtUTi7mw0z0GvPGzJ/ppZJJn+tmk1Q9QH v9ZUuTymTW3RLI1UDbuT2cmYKU6HDwPGWcSTzDfpvF7epylZ4VTJyCgpqcqchCAmmbY1//qOYyw bjnpanrCWnVCZKgs8ODmjiPcGluI62XlJf3I6tUr0hNAwxOIr0O+EI0qh/d1Xn4F+1SlkIHbHID E4Pnn3K5cLTyjB+H8dWDUp8+zG0/aTEeJr3J0ubOJdoaW8xi1cG226Bjx/mCbv5FrEFe5yqBGwY zYNrpa5fl/whsWn5ROrExT51BfMeinUSc2rHM/5hkwm4Z2Yh8xSuyQxFypT4jjIhrC8+4mS+BH7 ZqaRPVkc6gp+41JNMLvA1MdhesldbaKamUlyNLtQOjFwJzNpZpqguGZR1NhNKra8sY7u5pTibFE 6+JAixT3oE6IeAtEBlQ== X-Proofpoint-GUID: Qhq7LeLpQk0Y_W3hNLWjgqXLw519K0ba X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-24_04,2025-12-22_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 bulkscore=0 impostorscore=0 adultscore=0 malwarescore=0 clxscore=1015 suspectscore=0 priorityscore=1501 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512250026 On 12/19/2025 2:58 PM, Songwei Chai wrote: > The Trigger Generation Unit (TGU) is designed to detect patterns or > sequences within a specific region of the System on Chip (SoC). Once > configured and activated, it monitors sense inputs and can detect a > pre-programmed state or sequence across clock cycles, subsequently > producing a trigger. > > TGU configuration space > offset table > x-------------------------x > | | > | | > | | Step configuration > | | space layout > | coresight management | x-------------x > | registers | |---> | | > | | | | reserve | > | | | | | > |-------------------------| | |-------------| > | | | | priority[3] | > | step[7] |<-- | |-------------| > |-------------------------| | | | priority[2] | > | | | | |-------------| > | ... | |Steps region | | priority[1] | > | | | | |-------------| > |-------------------------| | | | priority[0] | > | |<-- | |-------------| > | step[0] |--------------------> | | > |-------------------------| | condition | > | | | | > | control and status | x-------------x > | space | | | > x-------------------------x |Timer/Counter| > | | > x-------------x > TGU Configuration in Hardware > > The TGU provides a step region for user configuration, similar > to a flow chart. Each step region consists of three register clusters: > > 1.Priority Region: Sets the required signals with priority. > 2.Condition Region: Defines specific requirements (e.g., signal A > reaches three times) and the subsequent action once the requirement is > met. > 3.Timer/Counter (Optional): Provides timing or counting functionality. > > Add a new tgu.yaml file to describe the bindings required to > define the TGU in the device trees. > > Reviewed-by: Rob Herring (Arm) > Signed-off-by: Songwei Chai > --- > .../devicetree/bindings/arm/qcom,tgu.yaml | 92 +++++++++++++++++++ > 1 file changed, 92 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/qcom,tgu.yaml > > diff --git a/Documentation/devicetree/bindings/arm/qcom,tgu.yaml b/Documentation/devicetree/bindings/arm/qcom,tgu.yaml > new file mode 100644 > index 000000000000..5b6a58ebe691 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/qcom,tgu.yaml > @@ -0,0 +1,92 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +# Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. Thanks, Jie > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/qcom,tgu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Trigger Generation Unit - TGU > + > +description: | > + The Trigger Generation Unit (TGU) is a Data Engine which can be utilized > + to sense a plurality of signals and create a trigger into the CTI or > + generate interrupts to processors. The TGU is like the trigger circuit > + of a Logic Analyzer. The corresponding trigger logic can be realized by > + configuring the conditions for each step after sensing the signal. > + Once setup and enabled, it will observe sense inputs and based upon > + the activity of those inputs, even over clock cycles, may detect a > + preprogrammed state/sequence and then produce a trigger or interrupt. > + > + The primary use case of the TGU is to detect patterns or sequences on a > + given set of signals within some region to identify the issue in time > + once there is abnormal behavior in the subsystem. > + > +maintainers: > + - Mao Jinlong > + - Songwei Chai > + > +# Need a custom select here or 'arm,primecell' will match on lots of nodes > +select: > + properties: > + compatible: > + contains: > + enum: > + - qcom,tgu > + required: > + - compatible > + > +properties: > + compatible: > + items: > + - const: qcom,tgu > + - const: arm,primecell > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + items: > + - const: apb_pclk > + > + in-ports: > + $ref: /schemas/graph.yaml#/properties/ports > + additionalProperties: false > + > + properties: > + port: > + description: > + The port mechanism here ensures the relationship between TGU and > + TPDM, as TPDM is one of the inputs for TGU. It will allow TGU to > + function as TPDM's helper and enable TGU when the connected > + TPDM is enabled. > + $ref: /schemas/graph.yaml#/properties/port > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + tgu@10b0e000 { > + compatible = "qcom,tgu", "arm,primecell"; > + reg = <0x10b0e000 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + in-ports { > + port { > + tgu_in_tpdm_swao: endpoint{ > + remote-endpoint = <&tpdm_swao_out_tgu>; > + }; > + }; > + }; > + }; > +...