Re: [PATCH 1/3] arm64: dts: qcom: eliza: Describe the ADSP and USB related nodes

Krishna Kurapati PSSNV
2026-04-28T05:47:09Z

On Wed, Apr 22, 2026 at 3:55 PM Abel Vesa <abel.vesa@oss.qualcomm.com> wrote:
>
> On 26-04-22 12:09:31, Konrad Dybcio wrote:
> > On 4/22/26 11:41 AM, Abel Vesa wrote:
> > > On 26-03-31 15:37:08, Konrad Dybcio wrote:
> > >> On 3/31/26 12:37 PM, Abel Vesa wrote:
> > >>> Describe the ADSP remoteproc node along with its dependencies, including
> > >>> the IPCC mailbox, AOSS QMP and SMP2P links used for communication.
> > >>>
> > >>> The Eliza SoC features a USB 3.1 Gen 2 controller connected to a QMP
> > >>> combo PHY and an SNPS eUSB2 PHY. Describe them.
> > >>>
> > >>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> > >>> ---
> > >>
> > >> [...]
> > >>
> > >>> + usb_hsphy: phy@88e3000 {
> > >>> + compatible = "qcom,eliza-snps-eusb2-phy",
> > >>> + "qcom,sm8550-snps-eusb2-phy";
> > >>> + reg = <0x0 0x088e3000 0x0 0x154>;
> > >>> + #phy-cells = <0>;
> > >>> +
> > >>> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> > >>
> > >> This is TCSR_USB2_CLKREF_EN
> > >
> > > Good point. Will fix.
> > >
> > >>
> > >>
> > >>> + usb: usb@a600000 {
> > >>> + compatible = "qcom,eliza-dwc3", "qcom,snps-dwc3";
> > >>
> > >> Does the device suspend and resume successfully?
> > >
> > > Well, tested with pm_test devices and it does suspend and resume
> > > successfully, but there is this:
> > >
> > > [ 54.584126] dwc3-qcom a600000.usb: port-1 HS-PHY not in L2
> > >
> > > But if I'm not mistaken, this is valid accross all SNPS eUSB2 PHYs, on
> > > all platforms that have them.
> >
> > Well it's not fatal, but ideally this wouldn't be there. Maybe you're missing
> > some DWC quirk in the list, although it seems pretty long already. Perhaps
> > Wesley would know more.
>
> + Wesley
>

As per HPG and downstream, this is what needs to be done while entering suspend:

1. Clear PWR_EVNT_LPM_IN_L2_MASK bit of pwr_evnt_irq_stat_reg
2. Clear PWR_EVNT_LPM_OUT_L2_MASK bit of pwr_evnt_irq_stat_reg
3. Set the following bits in the pwr_evnt_irq_stat_reg:
a) DWC3_GUSB2PHYCFG_ENBLSLPM and DWC3_GUSB2PHYCFG_SUSPHY
4. Wait for 3ms for PWR_EVNT_LPM_IN_L2_MASK to be set
5. If it is not set, then we can print the error
6. If its set, then we need to clear the bits.

Regards,
Krishna,