Re: [PATCH 1/3] arm64: dts: qcom: eliza: Describe the ADSP and USB related nodes

Abel Vesa
2026-05-04T10:30:47Z

On 26-05-04 12:25:36, Konrad Dybcio wrote:
> On 5/4/26 12:06 PM, Abel Vesa wrote:
> > On 26-04-29 11:45:10, Konrad Dybcio wrote:
> >> On 4/29/26 3:57 AM, Krishna Kurapati PSSNV wrote:
> >>> On Tue, Apr 28, 2026 at 2:54 PM Konrad Dybcio
> >>> <konrad.dybcio@oss.qualcomm.com> wrote:
> >>>>
> >>>> On 4/28/26 7:46 AM, Krishna Kurapati PSSNV wrote:
> >>>>> On Wed, Apr 22, 2026 at 3:55 PM Abel Vesa <abel.vesa@oss.qualcomm.com> wrote:
> >>>>>>
> >>>>>> On 26-04-22 12:09:31, Konrad Dybcio wrote:
> >>>>>>> On 4/22/26 11:41 AM, Abel Vesa wrote:
> >>>>>>>> On 26-03-31 15:37:08, Konrad Dybcio wrote:
> >>>>>>>>> On 3/31/26 12:37 PM, Abel Vesa wrote:
> >>>>>>>>>> Describe the ADSP remoteproc node along with its dependencies, including
> >>>>>>>>>> the IPCC mailbox, AOSS QMP and SMP2P links used for communication.
> >>>>>>>>>>
> >>>>>>>>>> The Eliza SoC features a USB 3.1 Gen 2 controller connected to a QMP
> >>>>>>>>>> combo PHY and an SNPS eUSB2 PHY. Describe them.
> >>>>>>>>>>
> >>>>>>>>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> >>>>>>>>>> ---
> >>>>>>>>>
> >>>>>>>>> [...]
> >>>>>>>>>
> >>>>>>>>>> + usb_hsphy: phy@88e3000 {
> >>>>>>>>>> + compatible = "qcom,eliza-snps-eusb2-phy",
> >>>>>>>>>> + "qcom,sm8550-snps-eusb2-phy";
> >>>>>>>>>> + reg = <0x0 0x088e3000 0x0 0x154>;
> >>>>>>>>>> + #phy-cells = <0>;
> >>>>>>>>>> +
> >>>>>>>>>> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> >>>>>>>>>
> >>>>>>>>> This is TCSR_USB2_CLKREF_EN
> >>>>>>>>
> >>>>>>>> Good point. Will fix.
> >>>>>>>>
> >>>>>>>>>
> >>>>>>>>>
> >>>>>>>>>> + usb: usb@a600000 {
> >>>>>>>>>> + compatible = "qcom,eliza-dwc3", "qcom,snps-dwc3";
> >>>>>>>>>
> >>>>>>>>> Does the device suspend and resume successfully?
> >>>>>>>>
> >>>>>>>> Well, tested with pm_test devices and it does suspend and resume
> >>>>>>>> successfully, but there is this:
> >>>>>>>>
> >>>>>>>> [ 54.584126] dwc3-qcom a600000.usb: port-1 HS-PHY not in L2
> >>>>>>>>
> >>>>>>>> But if I'm not mistaken, this is valid accross all SNPS eUSB2 PHYs, on
> >>>>>>>> all platforms that have them.
> >>>>>>>
> >>>>>>> Well it's not fatal, but ideally this wouldn't be there. Maybe you're missing
> >>>>>>> some DWC quirk in the list, although it seems pretty long already. Perhaps
> >>>>>>> Wesley would know more.
> >>>>>>
> >>>>>> + Wesley
> >>>>>>
> >>>>>
> >>>>> As per HPG and downstream, this is what needs to be done while entering suspend:
> >>>>>
> >>>>> 1. Clear PWR_EVNT_LPM_IN_L2_MASK bit of pwr_evnt_irq_stat_reg
> >>>>> 2. Clear PWR_EVNT_LPM_OUT_L2_MASK bit of pwr_evnt_irq_stat_reg
> >>>>> 3. Set the following bits in the pwr_evnt_irq_stat_reg:
> >>>>> a) DWC3_GUSB2PHYCFG_ENBLSLPM and DWC3_GUSB2PHYCFG_SUSPHY
> >>>>
> >>>> In case that's related, most platforms (including this one), set
> >>>> snps,dis_enblslpm_quirk which prevents the first bit from being set
> >>>>
> >>>> Likewise, snps,dis_u2_susphy_quirk for the second one
> >>>>
> >>>> (although it looks like setting these bits is currently
> >>>> unconditional upon suspend in HOST mode?)
> >>>>
> >>>>
> >>>> As for the sequence you mentioned, I believe the diff below should be
> >>>> OK - although it _really_ just adds some delay vs the current state,
> >>>> since the bits are cleared in the resume call
> >>>>
> >>>> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> >>>> index f43f73ac36ff..e7b1775b7207 100644
> >>>> --- a/drivers/usb/dwc3/dwc3-qcom.c
> >>>> +++ b/drivers/usb/dwc3/dwc3-qcom.c
> >>>> @@ -12,6 +12,7 @@
> >>>> #include <linux/module.h>
> >>>> #include <linux/kernel.h>
> >>>> #include <linux/interconnect.h>
> >>>> +#include <linux/iopoll.h>
> >>>> #include <linux/platform_device.h>
> >>>> #include <linux/phy/phy.h>
> >>>> #include <linux/usb/of.h>
> >>>> @@ -344,10 +345,18 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
> >>>> return 0;
> >>>>
> >>>> for (i = 0; i < qcom->num_ports; i++) {
> >>>> - val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg[i]);
> >>>> - if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
> >>>> + /* Wait for the PHYs to go into L2 */
> >>>> + ret = readl_poll_timeout(qcom->qscratch_base + pwr_evnt_irq_stat_reg[i],
> >>>> + val, val & PWR_EVNT_LPM_IN_L2_MASK,
> >>>> + 10, 3 * USEC_PER_MSEC);
> >>>> +
> >>>> + if (ret == -ETIMEDOUT)
> >>>> dev_err(qcom->dev, "port-%d HS-PHY not in L2\n", i + 1);
> >>>> }
> >>>> +
> >>>
> >>>
> >>> I think its best to set the DWC3_GUSB2PHYCFG_ENBLSLPM and
> >>> DWC3_GUSB2PHYCFG_SUSPHY here as well based on quirks before polling
> >>> for the irq_stat register.
> >>
> >> Hm, it seems like the dwc3 core layer only does so in the suspend
> >> path if dr_mode = "host"?
> >
> > OK, so I guess the quirk list is complete then, right ?
>
> Yeah, seems that way

Ok, will respin with your other comment addressed.

Thanks.