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charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.2 (3.52.2-1.fc40) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Thu, 2024-07-18 at 00:25 +0300, Alisa-Dariana Roman wrote: > Internal clock of AD719X devices can be made available on MCLK2 pin. Add > clock provider to support this functionality when clock cells property > is present. >=20 > Signed-off-by: Alisa-Dariana Roman > --- minor thing below you may consider if a re-spin is needed... Reviewed-by: Nuno Sa > =C2=A0drivers/iio/adc/ad7192.c | 92 +++++++++++++++++++++++++++++++++++++= +++ > =C2=A01 file changed, 92 insertions(+) >=20 > diff --git a/drivers/iio/adc/ad7192.c b/drivers/iio/adc/ad7192.c > index 042319f0c641..3f803b1eefcc 100644 > --- a/drivers/iio/adc/ad7192.c > +++ b/drivers/iio/adc/ad7192.c > @@ -8,6 +8,7 @@ > =C2=A0#include > =C2=A0#include > =C2=A0#include > +#include > =C2=A0#include > =C2=A0#include > =C2=A0#include > @@ -201,6 +202,7 @@ struct ad7192_chip_info { > =C2=A0struct ad7192_state { > =C2=A0 const struct ad7192_chip_info *chip_info; > =C2=A0 struct clk *mclk; > + struct clk_hw int_clk_hw; > =C2=A0 u16 int_vref_mv; > =C2=A0 u32 aincom_mv; > =C2=A0 u32 fclk; > @@ -406,6 +408,91 @@ static const char *const ad7192_clock_names[] =3D { > =C2=A0 "mclk" > =C2=A0}; > =C2=A0 > +static struct ad7192_state *clk_hw_to_ad7192(struct clk_hw *hw) > +{ > + return container_of(hw, struct ad7192_state, int_clk_hw); > +} > + > +static unsigned long ad7192_clk_recalc_rate(struct clk_hw *hw, > + =C2=A0=C2=A0=C2=A0 unsigned long parent_rate) > +{ > + return AD7192_INT_FREQ_MHZ; > +} > + > +static int ad7192_clk_output_is_enabled(struct clk_hw *hw) > +{ > + struct ad7192_state *st =3D clk_hw_to_ad7192(hw); > + > + return st->clock_sel =3D=3D AD7192_CLK_INT_CO; > +} > + > +static int ad7192_clk_prepare(struct clk_hw *hw) > +{ > + struct ad7192_state *st =3D clk_hw_to_ad7192(hw); > + int ret; > + > + st->mode &=3D ~AD7192_MODE_CLKSRC_MASK; > + st->mode |=3D AD7192_CLK_INT_CO; > + > + ret =3D ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); > + if (ret) > + return ret; > + > + st->clock_sel =3D AD7192_CLK_INT_CO; > + > + return 0; > +} > + > +static void ad7192_clk_unprepare(struct clk_hw *hw) > +{ > + struct ad7192_state *st =3D clk_hw_to_ad7192(hw); > + int ret; > + > + st->mode &=3D ~AD7192_MODE_CLKSRC_MASK; > + st->mode |=3D AD7192_CLK_INT; > + > + ret =3D ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); > + if (ret) > + return; > + > + st->clock_sel =3D AD7192_CLK_INT; > +} > + > +static const struct clk_ops ad7192_int_clk_ops =3D { > + .recalc_rate =3D ad7192_clk_recalc_rate, > + .is_enabled =3D ad7192_clk_output_is_enabled, > + .prepare =3D ad7192_clk_prepare, > + .unprepare =3D ad7192_clk_unprepare, > +}; > + > +static int ad7192_register_clk_provider(struct ad7192_state *st) > +{ > + struct device *dev =3D &st->sd.spi->dev; > + struct clk_init_data init =3D {}; > + int ret; > + > + if (!device_property_present(dev, "#clock-cells")) > + return 0; > + > + if (!IS_ENABLED(CONFIG_COMMON_CLK)) > + return 0; >=20 nit: This could be the first test to do. No point in calling device_property_present() if CONFIG_COMMON_CLK is disabled. FWIW, the compi= ler should be smart enough to sort things out but it would still be better (for readab= ility) to have this first. - Nuno S=C3=A1